global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index b4d113d..954fa5f 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -29,7 +29,7 @@
*/
static void __secure ls1_save_ddr_head(void)
{
- const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
+ const char *src = (const char *)CFG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ef71e2c..bbaa91f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1441,7 +1441,7 @@
}
#endif
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
@@ -1571,7 +1571,7 @@
if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
mmu_change_region_attr(
- CONFIG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_BASE,
gd->ram_size,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
@@ -1579,7 +1579,7 @@
PTE_TYPE_VALID);
} else {
mmu_change_region_attr(
- CONFIG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_BASE,
CONFIG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi
index 328ba90..d84c10c 100644
--- a/arch/arm/dts/rockchip-optee.dtsi
+++ b/arch/arm/dts/rockchip-optee.dtsi
@@ -32,8 +32,8 @@
arch = "arm";
os = "tee";
compression = "none";
- load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
- entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
+ load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+ entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
blob-ext {
filename = "tee.bin";
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 3542434..2141a45 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -583,7 +583,7 @@
(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
(DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
- (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
+ (CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\
(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h
index 4733c07..c63c27d 100644
--- a/arch/arm/include/asm/iproc-common/configs.h
+++ b/arch/arm/include/asm/iproc-common/configs.h
@@ -12,6 +12,6 @@
#define CONFIG_IPROC
/* Memory Info */
-#define CONFIG_SYS_SDRAM_BASE 0x61000000
+#define CFG_SYS_SDRAM_BASE 0x61000000
#endif /* __IPROC_COMMON_CONFIGS_H */
diff --git a/arch/arm/mach-aspeed/ast2500/board_common.c b/arch/arm/mach-aspeed/ast2500/board_common.c
index aca2002..bae1027 100644
--- a/arch/arm/mach-aspeed/ast2500/board_common.c
+++ b/arch/arm/mach-aspeed/ast2500/board_common.c
@@ -31,7 +31,7 @@
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c
index 82ff219..dc6cdc3 100644
--- a/arch/arm/mach-aspeed/ast2600/board_common.c
+++ b/arch/arm/mach-aspeed/ast2600/board_common.c
@@ -54,7 +54,7 @@
int i = 0, rc;
struct udevice *dev;
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
while (1) {
rc = uclass_get_device(UCLASS_MISC, i++, &dev);
diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S
index 57e51c8..3b91a0c 100644
--- a/arch/arm/mach-at91/arm920t/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S
@@ -114,38 +114,38 @@
.word CONFIG_SYS_SDRC_CR_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
- .word CONFIG_SYS_SDRAM1
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM1
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
SMRDATA1E:
/* SMRDATA1 is 176 bytes long */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
index c51eee2..ecfe589 100644
--- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
@@ -201,38 +201,38 @@
.word CONFIG_SYS_SDRC_MDR_VAL
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL1
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL1
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL3
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL4
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL5
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL6
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL7
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL8
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL9
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL2
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL3
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL4
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL5
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL6
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL7
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL8
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL9
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL4
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL10
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL10
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL5
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL11
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL11
.word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL12
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL12
/* User reset enable*/
.word AT91_ASM_RSTC_MR
.word CONFIG_SYS_RSTC_RMR_VAL
diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c
index 73fdd1f..42078b3 100644
--- a/arch/arm/mach-davinci/misc.c
+++ b/arch/arm/mach-davinci/misc.c
@@ -26,14 +26,14 @@
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
+ (void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c
index fa867f2..cad8ccc 100644
--- a/arch/arm/mach-exynos/dmc_init_ddr3.c
+++ b/arch/arm/mach-exynos/dmc_init_ddr3.c
@@ -236,7 +236,7 @@
* better have similar timings, since there's only a single adjustment that is
* shared by both chips).
*/
-const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
+const unsigned int test_addr = CFG_SYS_SDRAM_BASE;
/* Test pattern with which RAM will be tested */
static const unsigned int test_pattern[] = {
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index a486328..8050406 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -178,7 +178,7 @@
int i;
for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
- if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+ if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 802cb0e..5d95fb8 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -373,7 +373,7 @@
int i;
for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++)
- if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+ if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */
diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c
index 699a3dc..2ba3245 100644
--- a/arch/arm/mach-imx/mx6/litesom.c
+++ b/arch/arm/mach-imx/mx6/litesom.c
@@ -172,7 +172,7 @@
* Get actual RAM size, so we can adjust DDR row size for <512M
* memories
*/
- ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
+ ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M);
if (ram_size < SZ_512M) {
mem_ddr.rowaddr = 14;
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c
index e9d7874..38ead8a 100644
--- a/arch/arm/mach-imx/mx6/opos6ul.c
+++ b/arch/arm/mach-imx/mx6/opos6ul.c
@@ -44,7 +44,7 @@
int board_init(void)
{
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FEC_MXC
setup_fec();
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 6b8f411..cb9801b 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -349,7 +349,7 @@
#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = imx_ddr_size();
return 0;
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 227706e..d5e1f8e 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -561,7 +561,7 @@
void spl_enable_dcache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
- phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
+ phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
dram_init();
diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c
index 3d2ff67..2aec962 100644
--- a/arch/arm/mach-k3/r5_mpu.c
+++ b/arch/arm/mach-k3/r5_mpu.c
@@ -24,7 +24,7 @@
O_I_WB_RD_WR_ALLOC, REGION_8MB},
/* U-Boot's code area marking it as WB and Write allocate */
- {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
+ {CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_2GB},
/* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */
{0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC,
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index 53117c2..ea7d0b9 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -318,7 +318,7 @@
}
ddr3_ecc_init_range(base);
- ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
+ ddr3_reset_data(CFG_SYS_SDRAM_BASE, ddr3_size);
/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c
index 5d837e0..988b057 100644
--- a/arch/arm/mach-mediatek/mt7623/init.c
+++ b/arch/arm/mach-mediatek/mt7623/init.c
@@ -25,7 +25,7 @@
{
u32 i;
- if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) &&
+ if (((size_t)preloader_param >= CFG_SYS_SDRAM_BASE) &&
((size_t)preloader_param % sizeof(size_t) == 0) &&
preloader_param->magic == BOOT_ARGUMENT_MAGIC &&
preloader_param->dram_rank_num <=
@@ -35,7 +35,7 @@
for (i = 0; i < preloader_param->dram_rank_num; i++)
gd->ram_size += preloader_param->dram_rank_size[i];
} else {
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
SZ_2G);
}
diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c
index a895506..d8b10f0 100644
--- a/arch/arm/mach-mediatek/mt7981/init.c
+++ b/arch/arm/mach-mediatek/mt7981/init.c
@@ -14,7 +14,7 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
return 0;
}
diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c
index cf89e63..fb74b2f 100644
--- a/arch/arm/mach-mediatek/mt7986/init.c
+++ b/arch/arm/mach-mediatek/mt7986/init.c
@@ -14,7 +14,7 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
return 0;
}
diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c
index cc7f979..8204d96 100644
--- a/arch/arm/mach-mvebu/alleycat5/cpu.c
+++ b/arch/arm/mach-mvebu/alleycat5/cpu.c
@@ -21,8 +21,8 @@
static struct mm_region ac5_mem_map[] = {
{
/* RAM */
- .phys = CONFIG_SYS_SDRAM_BASE,
- .virt = CONFIG_SYS_SDRAM_BASE,
+ .phys = CFG_SYS_SDRAM_BASE,
+ .virt = CFG_SYS_SDRAM_BASE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
},
@@ -102,7 +102,7 @@
/*
* Config single DRAM bank
*/
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index e3098a7..2c94f89 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -32,7 +32,7 @@
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
- unsigned long top = CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
+ unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
return (gd->ram_top > top) ? top : gd->ram_top;
}
diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c
index bab375e..6c801bf 100644
--- a/arch/arm/mach-mvebu/armada8k/dram.c
+++ b/arch/arm/mach-mvebu/armada8k/dram.c
@@ -38,7 +38,7 @@
*/
phys_size_t max_bank0_size = SZ_4G - SZ_1G;
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size <= max_bank0_size) {
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 44d5214..86755d6 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -72,14 +72,14 @@
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
+ (void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
@@ -520,7 +520,7 @@
sdram_init();
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
+ (void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
}
#endif
diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c
index 312f868..a6a97af 100644
--- a/arch/arm/mach-omap2/emif-common.c
+++ b/arch/arm/mach-omap2/emif-common.c
@@ -389,7 +389,7 @@
/* Set region1 memory with 0 */
rgn_start = (regs->emif_ecc_address_range_1 &
EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
- rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
+ rgn = rgn_start + CFG_SYS_SDRAM_BASE;
size = (regs->emif_ecc_address_range_1 &
EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
@@ -400,7 +400,7 @@
/* Set region2 memory with 0 */
rgn_start = (regs->emif_ecc_address_range_2 &
EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
- rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
+ rgn = rgn_start + CFG_SYS_SDRAM_BASE;
size = (regs->emif_ecc_address_range_2 &
EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
@@ -1340,7 +1340,7 @@
mapped_size = 0;
section_cnt = 3;
- sys_addr = CONFIG_SYS_SDRAM_BASE;
+ sys_addr = CFG_SYS_SDRAM_BASE;
emif1_size = get_emif_mem_size(EMIF1_BASE);
emif2_size = get_emif_mem_size(EMIF2_BASE);
debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
@@ -1568,7 +1568,7 @@
size_prog = log_2_n_round_down(size_prog);
size_prog = (1 << size_prog);
- size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ size_detect = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
size_prog);
/* Compare with the size programmed */
if (size_detect != size_prog) {
diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c
index 0551bc1..0f9b915 100644
--- a/arch/arm/mach-omap2/sec-common.c
+++ b/arch/arm/mach-omap2/sec-common.c
@@ -198,11 +198,11 @@
*/
if (sec_mem_start == 0)
sec_mem_start =
- (CONFIG_SYS_SDRAM_BASE + (
+ (CFG_SYS_SDRAM_BASE + (
#if defined(CONFIG_OMAP54XX)
omap_sdram_size()
#else
- get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE)
#endif
- sec_mem_size));
diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c
index 4baef2e..f0f46f2 100644
--- a/arch/arm/mach-owl/soc.c
+++ b/arch/arm/mach-owl/soc.c
@@ -50,7 +50,7 @@
/* This is called after dram_init() so use get_ram_size result */
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 12f1d7e..e086c47 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -37,7 +37,7 @@
int dram_init_banksize(void)
{
- size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
+ size_t top = min((unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE),
(unsigned long)(gd->ram_top));
#ifdef CONFIG_ARM64
@@ -48,26 +48,26 @@
#ifdef CONFIG_SPL_OPTEE_IMAGE
struct tos_parameter_t *tos_parameter;
- tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
+ tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE +
TRUST_PARAMETER_OFFSET);
if (tos_parameter->tee_mem.flags == 1) {
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
- - CONFIG_SYS_SDRAM_BASE;
+ - CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
tos_parameter->tee_mem.size;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
} else {
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
/* Reserve 32M for OPTEE with TA */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0x2000000;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
}
#else
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
#endif
#endif
@@ -207,7 +207,7 @@
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
- unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
+ unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
return (gd->ram_top > top) ? top : gd->ram_top;
}
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index b49006c..09e0919 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -46,7 +46,7 @@
int board_init(void)
{
/* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index 2c87319..cdf2750 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -33,11 +33,11 @@
bool mctl_mem_matches(u32 offset)
{
/* Try to write different values to RAM at two addresses */
- writel(0, CONFIG_SYS_SDRAM_BASE);
- writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
+ writel(0, CFG_SYS_SDRAM_BASE);
+ writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
dsb();
/* Check if the same value is actually observed when reading back */
- return readl(CONFIG_SYS_SDRAM_BASE) ==
- readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
+ return readl(CFG_SYS_SDRAM_BASE) ==
+ readl((ulong)CFG_SYS_SDRAM_BASE + offset);
}
#endif
diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c
index 56c2d55..3aa3ce7 100644
--- a/arch/arm/mach-sunxi/dram_suniv.c
+++ b/arch/arm/mach-sunxi/dram_suniv.c
@@ -175,9 +175,9 @@
u32 k = 0;
for (k = 0; k < 32; k++)
- writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k);
+ writel(k, CFG_SYS_SDRAM_BASE + 4 * k);
for (k = 0; k < 32; k++) {
- if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k)
+ if (readl(CFG_SYS_SDRAM_BASE + 4 * k) != k)
return 0;
}
return 1;
@@ -266,11 +266,11 @@
dram_para_setup(para);
dram_scan_readpipe(para);
for (i = 0; i < 32; i++) {
- *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
- *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
+ *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
+ *((u8 *)(CFG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
}
for (i = 0; i < 32; i++) {
- val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i));
+ val1 = *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i));
if (val1 == 0x22)
count++;
}
@@ -283,11 +283,11 @@
para->row_width = rowflag;
dram_para_setup(para);
if (colflag == 10) {
- addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000;
- addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000;
+ addr1 = CFG_SYS_SDRAM_BASE + 0x400000;
+ addr2 = CFG_SYS_SDRAM_BASE + 0xc00000;
} else {
- addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000;
- addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000;
+ addr1 = CFG_SYS_SDRAM_BASE + 0x200000;
+ addr2 = CFG_SYS_SDRAM_BASE + 0x600000;
}
for (i = 0; i < 32; i++) {
*((u8 *)(addr1 + i)) = 0x33;
@@ -319,7 +319,7 @@
static void simple_dram_check(void)
{
- volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE;
+ volatile u32 *dram = (u32 *)CFG_SYS_SDRAM_BASE;
int i;
for (i = 0; i < 0x40; i++)
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 9107b11..4af5922 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -711,7 +711,7 @@
*/
static void mctl_r40_detect_rank_count(struct dram_para *para)
{
- ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE +
+ ulong rank1_base = (ulong) CFG_SYS_SDRAM_BASE +
mctl_calc_rank_size(¶->ranks[0]);
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
@@ -744,10 +744,10 @@
static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
{
- mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]);
+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE, ¶->ranks[0]);
if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) {
- mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]);
+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]);
}
}
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 82d3d33..54bbd8a 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -370,7 +370,7 @@
/* fall back to default DRAM bank size computation */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
#ifdef CONFIG_PCI
@@ -412,5 +412,5 @@
/* fall back to default usable RAM computation */
- return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
+ return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
}
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index ac595ee..3b6518c 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -54,7 +54,7 @@
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
-#if (CONFIG_SYS_SDRAM_BASE == 0)
+#if (CFG_SYS_SDRAM_BASE == 0)
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);