Merge patch series "Dockerfile: Build coreboot from source"
To make our CI loops more robust, switch to building and providing the
coreboot binary we test with rather than download from a Google Drive
link.
diff --git a/Kconfig b/Kconfig
index 00ed1ec..5710934 100644
--- a/Kconfig
+++ b/Kconfig
@@ -500,13 +500,14 @@
config HAS_BOARD_SIZE_LIMIT
bool "Define a maximum size for the U-Boot image"
- default y if RCAR_64
+ default y if RCAR_32 || RCAR_64
help
In some cases, we need to enforce a hard limit on how big the U-Boot
image itself can be.
config BOARD_SIZE_LIMIT
int "Maximum size of the U-Boot image in bytes"
+ default 524288 if RCAR_32
default 1048576 if RCAR_64
depends on HAS_BOARD_SIZE_LIMIT
help
diff --git a/MAINTAINERS b/MAINTAINERS
index 46ba176..0b08ca1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -62,6 +62,7 @@
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
R: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
+T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: boot/android_ab.c
F: cmd/ab_select.c
F: doc/android/ab.rst
@@ -72,6 +73,7 @@
M: Igor Opaniuk <igor.opaniuk@gmail.com>
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
S: Maintained
+T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: cmd/avb.c
F: common/avb_verify.c
F: doc/android/avb2.rst
@@ -453,7 +455,7 @@
ARM MSC SM2S IMX8MP SOM
M: Martyn Welch <martyn.welch@collabora.com>
-M: Ian Ray <ian.ray@ge.com>
+M: Ian Ray <ian.ray@gehealthcare.com>
S: Maintained
F: arch/arm/dts/imx8mp-msc-sm2s*
F: board/msc/sm2s_imx8mp/
@@ -565,6 +567,31 @@
F: arch/arm/mach-s5pc1xx/
F: arch/arm/cpu/armv7/s5p-common/
+ARM SAMSUNG CLOCK
+M: Sam Protsenko <semen.protsenko@linaro.org>
+S: Maintained
+F: drivers/clk/exynos/clk-pll.c
+F: drivers/clk/exynos/clk-pll.h
+F: drivers/clk/exynos/clk.c
+F: drivers/clk/exynos/clk.h
+
+ARM SAMSUNG EXYNOS850 SOC
+M: Sam Protsenko <semen.protsenko@linaro.org>
+S: Maintained
+F: arch/arm/dts/exynos850-pinctrl.dtsi
+F: arch/arm/dts/exynos850.dtsi
+F: doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
+F: drivers/clk/exynos/clk-exynos850.c
+F: drivers/pinctrl/exynos/pinctrl-exynos850.c
+F: include/dt-bindings/clock/exynos850.h
+
+ARM SAMSUNG SOC DRIVERS
+M: Sam Protsenko <semen.protsenko@linaro.org>
+S: Maintained
+F: doc/device-tree-bindings/soc/samsung/*
+F: drivers/soc/samsung/*
+F: include/dt-bindings/soc/samsung,*.h
+
ARM SANCLOUD
M: Paul Barker <paul.barker@sancloud.com>
R: Marc Murphy <marc.murphy@sancloud.com>
diff --git a/Makefile b/Makefile
index 3afe314..ec4990f 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2024
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b072be..fde85dc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1076,6 +1076,7 @@
select DM
select DM_SERIAL
select GPIO_EXTRA_HEADER
+ select LTO
imply BOARD_EARLY_INIT_F
imply CMD_DM
imply FAT_WRITE
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce10d3d..d972503 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -31,6 +31,7 @@
dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
+dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb
dtb-$(CONFIG_ARCH_APPLE) += \
t8103-j274.dtb \
@@ -930,6 +931,7 @@
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
+ imx6dl-sielaff.dtb \
imx6dl-wandboard-revd1.dtb \
imx6s-dhcom-drc02.dtb
diff --git a/arch/arm/dts/exynos-pinctrl.h b/arch/arm/dts/exynos-pinctrl.h
new file mode 100644
index 0000000..7dd94a9
--- /dev/null
+++ b/arch/arm/dts/exynos-pinctrl.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung Exynos DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
+#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
+
+#define EXYNOS_PIN_PULL_NONE 0
+#define EXYNOS_PIN_PULL_DOWN 1
+#define EXYNOS_PIN_PULL_UP 3
+
+/* Pin function in power down mode */
+#define EXYNOS_PIN_PDN_OUT0 0
+#define EXYNOS_PIN_PDN_OUT1 1
+#define EXYNOS_PIN_PDN_INPUT 2
+#define EXYNOS_PIN_PDN_PREV 3
+
+/*
+ * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850
+ * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1)
+ */
+#define EXYNOS5420_PIN_DRV_LV1 0
+#define EXYNOS5420_PIN_DRV_LV2 1
+#define EXYNOS5420_PIN_DRV_LV3 2
+#define EXYNOS5420_PIN_DRV_LV4 3
+
+/* Drive strengths for Exynos5433 */
+#define EXYNOS5433_PIN_DRV_FAST_SR1 0
+#define EXYNOS5433_PIN_DRV_FAST_SR2 1
+#define EXYNOS5433_PIN_DRV_FAST_SR3 2
+#define EXYNOS5433_PIN_DRV_FAST_SR4 3
+#define EXYNOS5433_PIN_DRV_FAST_SR5 4
+#define EXYNOS5433_PIN_DRV_FAST_SR6 5
+#define EXYNOS5433_PIN_DRV_SLOW_SR1 8
+#define EXYNOS5433_PIN_DRV_SLOW_SR2 9
+#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa
+#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb
+#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc
+#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf
+
+/* Drive strengths for Exynos7 (except FSYS1) */
+#define EXYNOS7_PIN_DRV_LV1 0
+#define EXYNOS7_PIN_DRV_LV2 2
+#define EXYNOS7_PIN_DRV_LV3 1
+#define EXYNOS7_PIN_DRV_LV4 3
+
+/* Drive strengths for Exynos7 FSYS1 block */
+#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
+#define EXYNOS7_FSYS1_PIN_DRV_LV2 4
+#define EXYNOS7_FSYS1_PIN_DRV_LV3 2
+#define EXYNOS7_FSYS1_PIN_DRV_LV4 6
+#define EXYNOS7_FSYS1_PIN_DRV_LV5 1
+#define EXYNOS7_FSYS1_PIN_DRV_LV6 5
+
+/* Drive strengths for Exynos850 GPIO_HSI block */
+#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */
+#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */
+#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */
+#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */
+#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */
+#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */
+
+#define EXYNOS_PIN_FUNC_INPUT 0
+#define EXYNOS_PIN_FUNC_OUTPUT 1
+#define EXYNOS_PIN_FUNC_2 2
+#define EXYNOS_PIN_FUNC_3 3
+#define EXYNOS_PIN_FUNC_4 4
+#define EXYNOS_PIN_FUNC_5 5
+#define EXYNOS_PIN_FUNC_6 6
+#define EXYNOS_PIN_FUNC_EINT 0xf
+#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
+
+#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */
diff --git a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
new file mode 100644
index 0000000..7ad11e9
--- /dev/null
+++ b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Linaro Ltd.
+ */
+
+&cmu_top {
+ bootph-all;
+};
+
+&cmu_peri {
+ bootph-all;
+};
+
+&oscclk {
+ bootph-all;
+};
+
+&pinctrl_alive {
+ bootph-all;
+};
+
+&pmu_system_controller {
+ bootph-all;
+ samsung,uart-debug-1;
+};
+
+&serial_0 {
+ bootph-all;
+};
+
+&uart1_pins {
+ bootph-all;
+};
+
+&usi_uart {
+ bootph-all;
+};
diff --git a/arch/arm/dts/exynos850-e850-96.dts b/arch/arm/dts/exynos850-e850-96.dts
new file mode 100644
index 0000000..f074df8
--- /dev/null
+++ b/arch/arm/dts/exynos850-e850-96.dts
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * WinLink E850-96 board device tree source
+ *
+ * Copyright (C) 2018 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2021 Linaro Ltd.
+ *
+ * Device tree source file for WinLink's E850-96 board which is based on
+ * Samsung Exynos850 SoC.
+ */
+
+/dts-v1/;
+
+#include "exynos850.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "WinLink E850-96 board";
+ compatible = "winlink,e850-96", "samsung,exynos850";
+
+ aliases {
+ mmc0 = &mmc_0;
+ serial0 = &serial_0;
+ };
+
+ chosen {
+ stdout-path = &serial_0;
+ };
+
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+ vbus-supply = <®_usb_host_vbus>;
+ id-gpios = <&gpa0 0 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <µ_usb_det_pins>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+
+ /*
+ * RAM: 4 GiB (eMCP):
+ * - 2 GiB at 0x80000000
+ * - 2 GiB at 0x880000000
+ *
+ * 0xbab00000..0xbfffffff: secure memory (85 MiB).
+ */
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x3ab00000>,
+ <0x0 0xc0000000 0x40000000>,
+ <0x8 0x80000000 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_voldown_pins &key_volup_pins>;
+
+ volume-down-key {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&gpa1 0 GPIO_ACTIVE_LOW>;
+ };
+
+ volume-up-key {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&gpa0 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ /* HEART_BEAT_LED */
+ user_led1: led-1 {
+ label = "yellow:user1";
+ gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ };
+
+ /* eMMC_LED */
+ user_led2: led-2 {
+ label = "yellow:user2";
+ gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_YELLOW>;
+ linux,default-trigger = "mmc0";
+ };
+
+ /* SD_LED */
+ user_led3: led-3 {
+ label = "white:user3";
+ gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_SD;
+ linux,default-trigger = "mmc2";
+ };
+
+ /* WIFI_LED */
+ wlan_active_led: led-4 {
+ label = "yellow:wlan";
+ gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_WLAN;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ /* BLUETOOTH_LED */
+ bt_active_led: led-5 {
+ label = "blue:bt";
+ gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_BLUETOOTH;
+ linux,default-trigger = "hci0-power";
+ default-state = "off";
+ };
+ };
+
+ /* TODO: Remove this once PMIC is implemented */
+ reg_dummy: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "dummy_reg";
+ };
+
+ reg_usb_host_vbus: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_host_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpa3 5 GPIO_ACTIVE_LOW>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ ramoops@f0000000 {
+ compatible = "ramoops";
+ reg = <0x0 0xf0000000 0x200000>;
+ record-size = <0x20000>;
+ console-size = <0x20000>;
+ ftrace-size = <0x100000>;
+ pmsg-size = <0x20000>;
+ };
+ };
+
+ /*
+ * RTC clock (XrtcXTI); external, must be 32.768 kHz.
+ *
+ * TODO: Remove this once RTC clock is implemented properly as part of
+ * PMIC driver.
+ */
+ rtcclk: clock-rtcclk {
+ compatible = "fixed-clock";
+ clock-output-names = "rtcclk";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+};
+
+&cmu_hsi {
+ clocks = <&oscclk>, <&rtcclk>,
+ <&cmu_top CLK_DOUT_HSI_BUS>,
+ <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
+ <&cmu_top CLK_DOUT_HSI_USB20DRD>;
+ clock-names = "oscclk", "rtcclk", "dout_hsi_bus",
+ "dout_hsi_mmc_card", "dout_hsi_usb20drd";
+};
+
+&mmc_0 {
+ status = "okay";
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cap-mmc-highspeed;
+ non-removable;
+ mmc-hs400-enhanced-strobe;
+ card-detect-delay = <200>;
+ clock-frequency = <800000000>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <2 4>;
+ samsung,dw-mshc-hs400-timing = <0 2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins
+ &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>;
+};
+
+&oscclk {
+ clock-frequency = <26000000>;
+};
+
+&pinctrl_alive {
+ key_voldown_pins: key-voldown-pins {
+ samsung,pins = "gpa1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ key_volup_pins: key-volup-pins {
+ samsung,pins = "gpa0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ micro_usb_det_pins: micro-usb-det-pins {
+ samsung,pins = "gpa0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+};
+
+&rtc {
+ status = "okay";
+ clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>;
+ clock-names = "rtc", "rtc_src";
+};
+
+&serial_0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
+&usbdrd {
+ status = "okay";
+ vdd10-supply = <®_dummy>;
+ vdd33-supply = <®_dummy>;
+};
+
+&usbdrd_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
+ };
+};
+
+&usbdrd_phy {
+ status = "okay";
+};
+
+&usi_uart {
+ samsung,clkreq-on; /* needed for UART mode */
+ status = "okay";
+};
+
+&watchdog_cl0 {
+ status = "okay";
+};
+
+&watchdog_cl1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/exynos850-pinctrl.dtsi b/arch/arm/dts/exynos850-pinctrl.dtsi
new file mode 100644
index 0000000..424bc80
--- /dev/null
+++ b/arch/arm/dts/exynos850-pinctrl.dtsi
@@ -0,0 +1,663 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (C) 2017 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2021 Linaro Ltd.
+ *
+ * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
+ * tree nodes in this file.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "exynos-pinctrl.h"
+
+&pinctrl_alive {
+ gpa0: gpa0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa1: gpa1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa2: gpa2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa3: gpa3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa4: gpa4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpq0: gpq0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* I2C5 (also called CAM_PMIC_I2C in TRM) */
+ i2c5_pins: i2c5-pins {
+ samsung,pins = "gpa3-5", "gpa3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* I2C6 (also called MOTOR_I2C in TRM) */
+ i2c6_pins: i2c6-pins {
+ samsung,pins = "gpa3-7", "gpa4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* USI: UART_DEBUG_0 pins */
+ uart0_pins: uart0-pins {
+ samsung,pins = "gpq0-0", "gpq0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI: UART_DEBUG_1 pins */
+ uart1_pins: uart1-pins {
+ samsung,pins = "gpa3-7", "gpa4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+};
+
+&pinctrl_cmgp {
+ gpm0: gpm0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm1: gpm1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm2: gpm2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm3: gpm3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm4: gpm4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm5: gpm5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm6: gpm6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm7: gpm7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* USI_CMGP0: HSI2C function */
+ hsi2c3_pins: hsi2c3-pins {
+ samsung,pins = "gpm0-0", "gpm1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */
+ uart1_single_pins: uart1-single-pins {
+ samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */
+ uart1_dual_pins: uart1-dual-pins {
+ samsung,pins = "gpm0-0", "gpm1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_CMGP0: SPI function */
+ spi1_pins: spi1-pins {
+ samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* USI_CMGP1: HSI2C function */
+ hsi2c4_pins: hsi2c4-pins {
+ samsung,pins = "gpm4-0", "gpm5-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */
+ uart2_single_pins: uart2-single-pins {
+ samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */
+ uart2_dual_pins: uart2-dual-pins {
+ samsung,pins = "gpm4-0", "gpm5-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI_CMGP1: SPI function */
+ spi2_pins: spi2-pins {
+ samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+};
+
+&pinctrl_aud {
+ gpb0: gpb0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ aud_codec_mclk_pins: aud-codec-mclk-pins {
+ samsung,pins = "gpb0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins {
+ samsung,pins = "gpb0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s0_pins: aud-i2s0-pins {
+ samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s0_idle_pins: aud-i2s0-idle-pins {
+ samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s1_pins: aud-i2s1-pins {
+ samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_i2s1_idle_pins: aud-i2s1-idle-pins {
+ samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_fm_pins: aud-fm-pins {
+ samsung,pins = "gpb1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_fm_idle_pins: aud-fm-idle-pins {
+ samsung,pins = "gpb1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+};
+
+&pinctrl_hsi {
+ gpf2: gpf2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sd2_clk_pins: sd2-clk-pins {
+ samsung,pins = "gpf2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
+ };
+
+ sd2_cmd_pins: sd2-cmd-pins {
+ samsung,pins = "gpf2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
+ };
+
+ sd2_bus1_pins: sd2-bus1-pins {
+ samsung,pins = "gpf2-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
+ };
+
+ sd2_bus4_pins: sd2-bus4-pins {
+ samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
+ };
+
+ sd2_pdn_pins: sd2-pdn-pins {
+ samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+ "gpf2-4", "gpf2-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+};
+
+&pinctrl_core {
+ gpf0: gpf0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sd0_clk_pins: sd0-clk-pins {
+ samsung,pins = "gpf0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ };
+
+ sd0_cmd_pins: sd0-cmd-pins {
+ samsung,pins = "gpf0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ };
+
+ sd0_rdqs_pins: sd0-rdqs-pins {
+ samsung,pins = "gpf0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ };
+
+ sd0_nreset_pins: sd0-nreset-pins {
+ samsung,pins = "gpf0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ };
+
+ sd0_bus1_pins: sd0-bus1-pins {
+ samsung,pins = "gpf1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ };
+
+ sd0_bus4_pins: sd0-bus4-pins {
+ samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ };
+
+ sd0_bus8_pins: sd0-bus8-pins {
+ samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ };
+};
+
+&pinctrl_peri {
+ gpc0: gpc0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg0: gpg0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg1: gpg1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg3: gpg3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp0: gpp0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ gpp1: gpp1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp2: gpp2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sensor_mclk0_in_pins: sensor-mclk0-in-pins {
+ samsung,pins = "gpc0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
+ };
+
+ sensor_mclk0_out_pins: sensor-mclk0-out-pins {
+ samsung,pins = "gpc0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
+ };
+
+ sensor_mclk0_fn_pins: sensor-mclk0-fn-pins {
+ samsung,pins = "gpc0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
+ };
+
+ sensor_mclk1_in_pins: sensor-mclk1-in-pins {
+ samsung,pins = "gpc0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
+ };
+
+ sensor_mclk1_out_pins: sensor-mclk1-out-pins {
+ samsung,pins = "gpc0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
+ };
+
+ sensor_mclk1_fn_pins: sensor-mclk1-fn-pins {
+ samsung,pins = "gpc0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
+ };
+
+ sensor_mclk2_in_pins: sensor-mclk2-in-pins {
+ samsung,pins = "gpc0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
+ };
+
+ sensor_mclk2_out_pins: sensor-mclk2-out-pins {
+ samsung,pins = "gpc0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
+ };
+
+ sensor_mclk2_fn_pins: sensor-mclk2-fn-pins {
+ samsung,pins = "gpc0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
+ };
+
+ /* USI: HSI2C0 */
+ hsi2c0_pins: hsi2c0-pins {
+ samsung,pins = "gpc1-0", "gpc1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* USI: HSI2C1 */
+ hsi2c1_pins: hsi2c1-pins {
+ samsung,pins = "gpc1-2", "gpc1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* USI: HSI2C2 */
+ hsi2c2_pins: hsi2c2-pins {
+ samsung,pins = "gpc1-4", "gpc1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ /* USI: SPI */
+ spi0_pins: spi0-pins {
+ samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ i2c0_pins: i2c0-pins {
+ samsung,pins = "gpp0-0", "gpp0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ i2c1_pins: i2c1-pins {
+ samsung,pins = "gpp0-2", "gpp0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ i2c2_pins: i2c2-pins {
+ samsung,pins = "gpp0-4", "gpp0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ i2c3_pins: i2c3-pins {
+ samsung,pins = "gpp1-0", "gpp1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ i2c4_pins: i2c4-pins {
+ samsung,pins = "gpp1-2", "gpp1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ xclkout_pins: xclkout-pins {
+ samsung,pins = "gpq0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+};
diff --git a/arch/arm/dts/exynos850.dtsi b/arch/arm/dts/exynos850.dtsi
new file mode 100644
index 0000000..53104e6
--- /dev/null
+++ b/arch/arm/dts/exynos850.dtsi
@@ -0,0 +1,809 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Exynos850 SoC device tree source
+ *
+ * Copyright (C) 2018 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2021 Linaro Ltd.
+ *
+ * Samsung Exynos850 SoC device nodes are listed in this file.
+ * Exynos850 based board files can include this file and provide
+ * values for board specific bindings.
+ */
+
+#include <dt-bindings/clock/exynos850.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/samsung,exynos-usi.h>
+
+/ {
+ /* Also known under engineering name Exynos3830 */
+ compatible = "samsung,exynos850";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ pinctrl0 = &pinctrl_alive;
+ pinctrl1 = &pinctrl_cmgp;
+ pinctrl2 = &pinctrl_aud;
+ pinctrl3 = &pinctrl_hsi;
+ pinctrl4 = &pinctrl_core;
+ pinctrl5 = &pinctrl_peri;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
+ <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ /* Main system clock (XTCXO); external, must be 26 MHz */
+ oscclk: clock-oscclk {
+ compatible = "fixed-clock";
+ clock-output-names = "oscclk";
+ #clock-cells = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x1>;
+ enable-method = "psci";
+ };
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x2>;
+ enable-method = "psci";
+ };
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x3>;
+ enable-method = "psci";
+ };
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x102>;
+ enable-method = "psci";
+ };
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x103>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ /* Hypervisor Virtual Timer interrupt is not wired to GIC */
+ interrupts =
+ <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x20000000>;
+
+ chipid@10000000 {
+ compatible = "samsung,exynos850-chipid";
+ reg = <0x10000000 0x100>;
+ };
+
+ timer@10040000 {
+ compatible = "samsung,exynos850-mct",
+ "samsung,exynos4210-mct";
+ reg = <0x10040000 0x800>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
+ clock-names = "fin_pll", "mct";
+ };
+
+ gic: interrupt-controller@12a01000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ reg = <0x12a01000 0x1000>,
+ <0x12a02000 0x2000>,
+ <0x12a04000 0x2000>,
+ <0x12a06000 0x2000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pmu_system_controller: system-controller@11860000 {
+ compatible = "samsung,exynos850-pmu", "syscon";
+ reg = <0x11860000 0x10000>;
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
+ mask = <0x2>; /* SWRESET_SYSTEM */
+ value = <0x2>; /* reset value */
+ };
+ };
+
+ watchdog_cl0: watchdog@10050000 {
+ compatible = "samsung,exynos850-wdt";
+ reg = <0x10050000 0x100>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
+ clock-names = "watchdog", "watchdog_src";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,cluster-index = <0>;
+ status = "disabled";
+ };
+
+ watchdog_cl1: watchdog@10060000 {
+ compatible = "samsung,exynos850-wdt";
+ reg = <0x10060000 0x100>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
+ clock-names = "watchdog", "watchdog_src";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,cluster-index = <1>;
+ status = "disabled";
+ };
+
+ cmu_peri: clock-controller@10030000 {
+ compatible = "samsung,exynos850-cmu-peri";
+ reg = <0x10030000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
+ <&cmu_top CLK_DOUT_PERI_UART>,
+ <&cmu_top CLK_DOUT_PERI_IP>;
+ clock-names = "oscclk", "dout_peri_bus",
+ "dout_peri_uart", "dout_peri_ip";
+ };
+
+ cmu_g3d: clock-controller@11400000 {
+ compatible = "samsung,exynos850-cmu-g3d";
+ reg = <0x11400000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
+ clock-names = "oscclk", "dout_g3d_switch";
+ };
+
+ cmu_apm: clock-controller@11800000 {
+ compatible = "samsung,exynos850-cmu-apm";
+ reg = <0x11800000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
+ clock-names = "oscclk", "dout_clkcmu_apm_bus";
+ };
+
+ cmu_cmgp: clock-controller@11c00000 {
+ compatible = "samsung,exynos850-cmu-cmgp";
+ reg = <0x11c00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>;
+ clock-names = "oscclk", "gout_clkcmu_cmgp_bus";
+ };
+
+ cmu_core: clock-controller@12000000 {
+ compatible = "samsung,exynos850-cmu-core";
+ reg = <0x12000000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
+ <&cmu_top CLK_DOUT_CORE_CCI>,
+ <&cmu_top CLK_DOUT_CORE_MMC_EMBD>,
+ <&cmu_top CLK_DOUT_CORE_SSS>;
+ clock-names = "oscclk", "dout_core_bus",
+ "dout_core_cci", "dout_core_mmc_embd",
+ "dout_core_sss";
+ };
+
+ cmu_top: clock-controller@120e0000 {
+ compatible = "samsung,exynos850-cmu-top";
+ reg = <0x120e0000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>;
+ clock-names = "oscclk";
+ };
+
+ cmu_mfcmscl: clock-controller@12c00000 {
+ compatible = "samsung,exynos850-cmu-mfcmscl";
+ reg = <0x12c00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_MFCMSCL_MFC>,
+ <&cmu_top CLK_DOUT_MFCMSCL_M2M>,
+ <&cmu_top CLK_DOUT_MFCMSCL_MCSC>,
+ <&cmu_top CLK_DOUT_MFCMSCL_JPEG>;
+ clock-names = "oscclk", "dout_mfcmscl_mfc",
+ "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",
+ "dout_mfcmscl_jpeg";
+ };
+
+ cmu_dpu: clock-controller@13000000 {
+ compatible = "samsung,exynos850-cmu-dpu";
+ reg = <0x13000000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>;
+ clock-names = "oscclk", "dout_dpu";
+ };
+
+ cmu_hsi: clock-controller@13400000 {
+ compatible = "samsung,exynos850-cmu-hsi";
+ reg = <0x13400000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_HSI_BUS>,
+ <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
+ <&cmu_top CLK_DOUT_HSI_USB20DRD>;
+ clock-names = "oscclk", "dout_hsi_bus",
+ "dout_hsi_mmc_card", "dout_hsi_usb20drd";
+ };
+
+ cmu_is: clock-controller@14500000 {
+ compatible = "samsung,exynos850-cmu-is";
+ reg = <0x14500000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_IS_BUS>,
+ <&cmu_top CLK_DOUT_IS_ITP>,
+ <&cmu_top CLK_DOUT_IS_VRA>,
+ <&cmu_top CLK_DOUT_IS_GDC>;
+ clock-names = "oscclk", "dout_is_bus", "dout_is_itp",
+ "dout_is_vra", "dout_is_gdc";
+ };
+
+ cmu_aud: clock-controller@14a00000 {
+ compatible = "samsung,exynos850-cmu-aud";
+ reg = <0x14a00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>;
+ clock-names = "oscclk", "dout_aud";
+ };
+
+ pinctrl_alive: pinctrl@11850000 {
+ compatible = "samsung,exynos850-pinctrl";
+ reg = <0x11850000 0x1000>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos850-wakeup-eint";
+ };
+ };
+
+ pinctrl_cmgp: pinctrl@11c30000 {
+ compatible = "samsung,exynos850-pinctrl";
+ reg = <0x11c30000 0x1000>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos850-wakeup-eint";
+ };
+ };
+
+ pinctrl_core: pinctrl@12070000 {
+ compatible = "samsung,exynos850-pinctrl";
+ reg = <0x12070000 0x1000>;
+ interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_hsi: pinctrl@13430000 {
+ compatible = "samsung,exynos850-pinctrl";
+ reg = <0x13430000 0x1000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_peri: pinctrl@139b0000 {
+ compatible = "samsung,exynos850-pinctrl";
+ reg = <0x139b0000 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_aud: pinctrl@14a60000 {
+ compatible = "samsung,exynos850-pinctrl";
+ reg = <0x14a60000 0x1000>;
+ };
+
+ rtc: rtc@11a30000 {
+ compatible = "samsung,s3c6410-rtc";
+ reg = <0x11a30000 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>;
+ clock-names = "rtc";
+ status = "disabled";
+ };
+
+ mmc_0: mmc@12100000 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ reg = <0x12100000 0x2000>;
+ interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>,
+ <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
+ i2c_0: i2c@13830000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13830000 0x100>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ i2c_1: i2c@13840000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13840000 0x100>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ i2c_2: i2c@13850000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13850000 0x100>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ i2c_3: i2c@13860000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13860000 0x100>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ i2c_4: i2c@13870000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13870000 0x100>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+ clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ /* I2C_5 (also called CAM_PMIC_I2C in TRM) */
+ i2c_5: i2c@13880000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13880000 0x100>;
+ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ /* I2C_6 (also called MOTOR_I2C in TRM) */
+ i2c_6: i2c@13890000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13890000 0x100>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ sysmmu_mfcmscl: sysmmu@12c50000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12c50000 0x9000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "sysmmu";
+ clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_dpu: sysmmu@130c0000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x130c0000 0x9000>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "sysmmu";
+ clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_is0: sysmmu@14550000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x14550000 0x9000>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "sysmmu";
+ clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_is1: sysmmu@14570000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x14570000 0x9000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "sysmmu";
+ clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_aud: sysmmu@14850000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x14850000 0x9000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "sysmmu";
+ clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
+ #iommu-cells = <0>;
+ };
+
+ sysreg_peri: syscon@10020000 {
+ compatible = "samsung,exynos850-peri-sysreg",
+ "samsung,exynos850-sysreg", "syscon";
+ reg = <0x10020000 0x10000>;
+ clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>;
+ };
+
+ sysreg_cmgp: syscon@11c20000 {
+ compatible = "samsung,exynos850-cmgp-sysreg",
+ "samsung,exynos850-sysreg", "syscon";
+ reg = <0x11c20000 0x10000>;
+ clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
+ };
+
+ usbdrd: usb@13600000 {
+ compatible = "samsung,exynos850-dwusb3";
+ ranges = <0x0 0x13600000 0x10000>;
+ clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>,
+ <&cmu_hsi CLK_GOUT_USB_REF_CLK>;
+ clock-names = "bus_early", "ref";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd_dwc3: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd_phy 0>;
+ phy-names = "usb2-phy";
+ };
+ };
+
+ usbdrd_phy: phy@135d0000 {
+ compatible = "samsung,exynos850-usbdrd-phy";
+ reg = <0x135d0000 0x100>;
+ clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>,
+ <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ usi_uart: usi@138200c0 {
+ compatible = "samsung,exynos850-usi";
+ reg = <0x138200c0 0x20>;
+ samsung,sysreg = <&sysreg_peri 0x1010>;
+ samsung,mode = <USI_V2_UART>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
+ <&cmu_peri CLK_GOUT_UART_IPCLK>;
+ clock-names = "pclk", "ipclk";
+ status = "disabled";
+
+ serial_0: serial@13820000 {
+ compatible = "samsung,exynos850-uart";
+ reg = <0x13820000 0xc0>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
+ <&cmu_peri CLK_GOUT_UART_IPCLK>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+ };
+
+ usi_hsi2c_0: usi@138a00c0 {
+ compatible = "samsung,exynos850-usi";
+ reg = <0x138a00c0 0x20>;
+ samsung,sysreg = <&sysreg_peri 0x1020>;
+ samsung,mode = <USI_V2_I2C>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>,
+ <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>;
+ clock-names = "pclk", "ipclk";
+ status = "disabled";
+
+ hsi2c_0: i2c@138a0000 {
+ compatible = "samsung,exynosautov9-hsi2c";
+ reg = <0x138a0000 0xc0>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsi2c0_pins>;
+ clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>,
+ <&cmu_peri CLK_GOUT_HSI2C0_PCLK>;
+ clock-names = "hsi2c", "hsi2c_pclk";
+ status = "disabled";
+ };
+ };
+
+ usi_hsi2c_1: usi@138b00c0 {
+ compatible = "samsung,exynos850-usi";
+ reg = <0x138b00c0 0x20>;
+ samsung,sysreg = <&sysreg_peri 0x1030>;
+ samsung,mode = <USI_V2_I2C>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>,
+ <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>;
+ clock-names = "pclk", "ipclk";
+ status = "disabled";
+
+ hsi2c_1: i2c@138b0000 {
+ compatible = "samsung,exynosautov9-hsi2c";
+ reg = <0x138b0000 0xc0>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsi2c1_pins>;
+ clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>,
+ <&cmu_peri CLK_GOUT_HSI2C1_PCLK>;
+ clock-names = "hsi2c", "hsi2c_pclk";
+ status = "disabled";
+ };
+ };
+
+ usi_hsi2c_2: usi@138c00c0 {
+ compatible = "samsung,exynos850-usi";
+ reg = <0x138c00c0 0x20>;
+ samsung,sysreg = <&sysreg_peri 0x1040>;
+ samsung,mode = <USI_V2_I2C>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>,
+ <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>;
+ clock-names = "pclk", "ipclk";
+ status = "disabled";
+
+ hsi2c_2: i2c@138c0000 {
+ compatible = "samsung,exynosautov9-hsi2c";
+ reg = <0x138c0000 0xc0>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsi2c2_pins>;
+ clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
+ <&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
+ clock-names = "hsi2c", "hsi2c_pclk";
+ status = "disabled";
+ };
+ };
+
+ usi_spi_0: usi@139400c0 {
+ compatible = "samsung,exynos850-usi";
+ reg = <0x139400c0 0x20>;
+ samsung,sysreg = <&sysreg_peri 0x1050>;
+ samsung,mode = <USI_V2_SPI>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
+ <&cmu_peri CLK_GOUT_SPI0_IPCLK>;
+ clock-names = "pclk", "ipclk";
+ status = "disabled";
+ };
+
+ usi_cmgp0: usi@11d000c0 {
+ compatible = "samsung,exynos850-usi";
+ reg = <0x11d000c0 0x20>;
+ samsung,sysreg = <&sysreg_cmgp 0x2000>;
+ samsung,mode = <USI_V2_I2C>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
+ <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
+ clock-names = "pclk", "ipclk";
+ status = "disabled";
+
+ hsi2c_3: i2c@11d00000 {
+ compatible = "samsung,exynosautov9-hsi2c";
+ reg = <0x11d00000 0xc0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsi2c3_pins>;
+ clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>,
+ <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>;
+ clock-names = "hsi2c", "hsi2c_pclk";
+ status = "disabled";
+ };
+
+ serial_1: serial@11d00000 {
+ compatible = "samsung,exynos850-uart";
+ reg = <0x11d00000 0xc0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_single_pins>;
+ clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
+ <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+ };
+
+ usi_cmgp1: usi@11d200c0 {
+ compatible = "samsung,exynos850-usi";
+ reg = <0x11d200c0 0x20>;
+ samsung,sysreg = <&sysreg_cmgp 0x2010>;
+ samsung,mode = <USI_V2_I2C>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
+ <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
+ clock-names = "pclk", "ipclk";
+ status = "disabled";
+
+ hsi2c_4: i2c@11d20000 {
+ compatible = "samsung,exynosautov9-hsi2c";
+ reg = <0x11d20000 0xc0>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsi2c4_pins>;
+ clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>,
+ <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>;
+ clock-names = "hsi2c", "hsi2c_pclk";
+ status = "disabled";
+ };
+
+ serial_2: serial@11d20000 {
+ compatible = "samsung,exynos850-uart";
+ reg = <0x11d20000 0xc0>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_single_pins>;
+ clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
+ <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+ };
+ };
+};
+
+#include "exynos850-pinctrl.dtsi"
diff --git a/arch/arm/dts/imx53-qsb-u-boot.dtsi b/arch/arm/dts/imx53-qsb-u-boot.dtsi
new file mode 100644
index 0000000..18cf708
--- /dev/null
+++ b/arch/arm/dts/imx53-qsb-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
+};
+
+&wdog1 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi b/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi
new file mode 100644
index 0000000..8f5a70c
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+/ {
+ binman: binman {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "SPL";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x11000>;
+ filename = "u-boot.img";
+ };
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ };
+};
+
+&fec {
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <100>;
+};
+
+&gpmi {
+ fsl,legacy-bch-geometry;
+};
diff --git a/arch/arm/dts/imx6dl-sielaff.dts b/arch/arm/dts/imx6dl-sielaff.dts
new file mode 100644
index 0000000..7de8d5f
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sielaff.dts
@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Sielaff i.MX6 Solo";
+ compatible = "sielaff,imx6dl-board", "fsl,imx6dl";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ pwms = <&pwm3 0 50000 0>;
+ brightness-levels = <0 0 64 88 112 136 184 232 255>;
+ default-brightness-level = <4>;
+ enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ power-supply = <®_backlight>;
+ };
+
+ cec {
+ compatible = "cec-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_cec>;
+ cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ hdmi-phandle = <&hdmi>;
+ };
+
+ enet_ref: clock-enet-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "enet-ref";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ key-0 {
+ gpios = <&gpio2 16 0>;
+ debounce-interval = <10>;
+ linux,code = <1>;
+ };
+
+ key-1 {
+ gpios = <&gpio3 27 0>;
+ debounce-interval = <10>;
+ linux,code = <2>;
+ };
+
+ key-2 {
+ gpios = <&gpio5 4 0>;
+ debounce-interval = <10>;
+ linux,code = <3>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-debug {
+ label = "debug-led";
+ gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ device_type = "memory";
+ };
+
+ osc_eth_phy: clock-osc-eth-phy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "osc-eth-phy";
+ };
+
+ panel {
+ compatible = "lg,lb070wv8";
+ backlight = <&backlight>;
+ power-supply = <®_3v3>;
+
+ port {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out>;
+ };
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_backlight: regulator-backlight {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_backlight>;
+ enable-active-high;
+ gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ regulator-name = "backlight";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
+ enable-active-high;
+ gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+&fec {
+ /*
+ * Set PTP clock to external instead of internal reference, as the
+ * REF_CLK from the PHY is fed back into the i.MX6 and the GPR
+ * register needs to be set accordingly (see mach-imx6q.c).
+ */
+ clocks = <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>,
+ <&enet_ref>,
+ <&clks IMX6QDL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp", "enet_out";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-connection-type = "rmii";
+ phy-handle = <ðphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&osc_eth_phy>;
+ clock-names = "rmii-ref";
+ micrel,led-mode = <1>;
+ reset-assert-us = <500>;
+ reset-deassert-us = <100>;
+ reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "key-out", "key-in",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "lan9500a-rst", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c4>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ touchscreen@55 {
+ compatible = "sitronix,st1633";
+ reg = <0x55>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpio5>;
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+ };
+
+ touchscreen@5d {
+ compatible = "goodix,gt928";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch>;
+ interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio5>;
+ irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&ldb {
+ status = "okay";
+
+ lvds: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds_out: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ disable-over-current;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb1@1 {
+ compatible = "usb4b4,6570";
+ reg = <1>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+
+ assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
+ <&clks IMX6QDL_CLK_CKO2_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
+ <&clks IMX6QDL_CLK_OSC>;
+ assigned-clock-rates = <12000000 0>;
+ };
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ dr_mode = "host";
+ over-current-active-low;
+ vbus-supply = <®_usb_otg_vbus>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+ >;
+ };
+
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
+
+ pinctrl_hdmi_cec: hdmicecgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_reg_backlight: regbacklightgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1
+ >;
+ };
+
+ pinctrl_reg_usbotg_vbus: regusbotgvbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1
+ >;
+ };
+
+ pinctrl_touch: touchgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi b/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi
index ebfb95d..e65eeb8 100644
--- a/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi
+++ b/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi
@@ -9,6 +9,12 @@
soc {
bootph-pre-ram;
};
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
};
&aips2 {
@@ -26,3 +32,7 @@
&usdhc1 {
bootph-pre-ram;
};
+
+&wdog1 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
index c398a74..ce61ca6 100644
--- a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
@@ -9,6 +9,11 @@
model = "MSC SM2S-IMX8MPLUS";
compatible = "avnet,sm2s-imx8mp", "fsl,imx8mp";
+ aliases {
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc2;
+ };
+
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
@@ -63,3 +68,11 @@
&pmic {
bootph-pre-ram;
};
+
+&uart2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart2 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx93-var-som-symphony.dts b/arch/arm/dts/imx93-var-som-symphony.dts
index a67bd00..1bc6194 100644
--- a/arch/arm/dts/imx93-var-som-symphony.dts
+++ b/arch/arm/dts/imx93-var-som-symphony.dts
@@ -285,6 +285,24 @@
status = "okay";
};
+&usbotg1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ disable-over-current;
+ status = "okay";
+};
+
/* SD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
index 90de635..d696471 100644
--- a/arch/arm/dts/imx93.dtsi
+++ b/arch/arm/dts/imx93.dtsi
@@ -149,6 +149,20 @@
};
};
+ usbphynop1: usbphynop1 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
+ clock-names = "main_clk";
+ };
+
+ usbphynop2: usbphynop2 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
+ clock-names = "main_clk";
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -844,5 +858,49 @@
#power-domain-cells = <1>;
status = "disabled";
};
+
+ usbotg1: usb@4c100000 {
+ compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
+ reg = <0x4c100000 0x200>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
+ <&clk IMX93_CLK_HSIO_32K_GATE>;
+ clock-names = "usb_ctrl_root_clk", "usb_wakeup";
+ assigned-clocks = <&clk IMX93_CLK_HSIO>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <133000000>;
+ phys = <&usbphynop1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@4c100200 {
+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
+ "fsl,imx6q-usbmisc";
+ reg = <0x4c100200 0x200>;
+ #index-cells = <1>;
+ };
+
+ usbotg2: usb@4c200000 {
+ compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
+ reg = <0x4c200000 0x200>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
+ <&clk IMX93_CLK_HSIO_32K_GATE>;
+ clock-names = "usb_ctrl_root_clk", "usb_wakeup";
+ assigned-clocks = <&clk IMX93_CLK_HSIO>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <133000000>;
+ phys = <&usbphynop2>;
+ fsl,usbmisc = <&usbmisc2 0>;
+ status = "disabled";
+ };
+
+ usbmisc2: usbmisc@4c200200 {
+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
+ "fsl,imx6q-usbmisc";
+ reg = <0x4c200200 0x200>;
+ #index-cells = <1>;
+ };
};
};
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 46928c0..e246de0 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -5,6 +5,10 @@
*/
/ {
+ binman: binman {
+ multiple-images;
+ };
+
chosen {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index a9095e7..3f54411 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -8,6 +8,10 @@
#include "imxrt1050-pinfunc.h"
/ {
+ binman: binman {
+ multiple-images;
+ };
+
aliases {
display0 = &lcdif;
usbphy0 = &usbphy1;
@@ -113,6 +117,33 @@
};
};
+&binman {
+#ifdef CONFIG_FSPI_CONF_HEADER
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ fspi_conf_block {
+ filename = CONFIG_FSPI_CONF_FILE;
+ type = "blob-ext";
+ offset = <0x0>;
+ };
+
+ spl {
+ filename = "SPL";
+ offset = <0x1000>;
+ type = "blob-ext";
+ };
+
+ binman_uboot: uboot {
+ filename = "u-boot.img";
+ offset = <0x10000>;
+ type = "blob-ext";
+ };
+ };
+#endif
+};
+
&osc {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
index f923a14..6e892c1 100644
--- a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
@@ -6,6 +6,10 @@
*/
/ {
+ binman: binman {
+ multiple-images;
+ };
+
chosen {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index f8c786a..75dfd2f 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -44,7 +44,7 @@
};
};
- fpga_full: fpga-full {
+ fpga_full: fpga-region {
compatible = "fpga-region";
fpga-mgr = <&devcfg>;
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index f1b0a4a..0b97fa3 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -449,6 +449,7 @@
factory-fout = <156250000>;
clock-frequency = <156250000>;
clock-output-names = "si570_zsfp_clk";
+ silabs,skip-recall;
};
};
i2c@6 { /* USER_SI570_1 */
@@ -463,6 +464,7 @@
factory-fout = <100000000>;
clock-frequency = <100000000>;
clock-output-names = "si570_user1";
+ silabs,skip-recall;
};
};
@@ -560,6 +562,7 @@
factory-fout = <200000000>;
clock-frequency = <200000000>;
clock-output-names = "si570_lpddr4_clk2";
+ silabs,skip-recall;
};
};
i2c@5 { /* LPDDR4_SI570_CLK1 */
@@ -574,6 +577,7 @@
factory-fout = <200000000>;
clock-frequency = <200000000>;
clock-output-names = "si570_lpddr4_clk1";
+ silabs,skip-recall;
};
};
i2c@6 { /* HSDP_SI570 */
@@ -588,6 +592,7 @@
factory-fout = <156250000>;
clock-frequency = <156250000>;
clock-output-names = "si570_hsdp_clk";
+ silabs,skip-recall;
};
};
i2c@7 { /* 8A34001 - U219B and J310 connector */
diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
index 766f783..5202b7c 100644
--- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -32,6 +32,18 @@
#clock-cells = <0>;
clock-frequency = <26000000>;
};
+
+ clk_25_0: clock4 { /* u92/u91 - GEM2 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ clk_25_1: clock5 { /* u92/u91 - GEM3 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
};
&can0 {
@@ -354,3 +366,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
+
+&zynqmp_dpsub {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
index 7717abf..ce7c5eb 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
@@ -25,37 +25,43 @@
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
};
- si5332_0: si5332-0 { /* u17 - GEM0/1 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- si5332_1: si5332-1 { /* u17 - DP */
+ clk_27: clock0 { /* u86 - DP */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
- si5332_2: si5332-2 { /* u17 - USB */
+ clk_125: si5332-0 { /* u17 - GEM0/1 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk_74: si5332-5 { /* u17 - SLVC-EC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+
+ clk_26: si5332-2 { /* u17 - USB */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
- si5332_3: si5332-3 { /* u17 - SFP+ */
+ clk_156: si5332-3 { /* u17 - SFP+ */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <156250000>;
};
- si5332_4: si5332-4 { /* u17 - GEM2 */
+ clk_25_0: si5332-1 { /* u17 - GEM2 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
- si5332_5: si5332-5 { /* u17 - GEM3 */
+ clk_25_1: si5332-4 { /* u17 - GEM3 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
@@ -115,7 +121,7 @@
&psgtr {
status = "okay";
/* gem0/1, dp, usb */
- clocks = <&si5332_0>, <&si5332_1>, <&si5332_2>;
+ clocks = <&clk_125>, <&clk_27>, <&clk_26>;
clock-names = "ref0", "ref1", "ref2";
};
@@ -168,12 +174,13 @@
phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
-
+#if 0
usbhub1: usb-hub { /* u84 */
i2c-bus = <&usbhub_i2c1>;
compatible = "microchip,usb5744";
reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
};
+#endif
};
&dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
index 2118739..6c29f65 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
@@ -60,6 +60,12 @@
#clock-cells = <0>;
clock-frequency = <25000000>;
};
+
+ clk_74: clock6 { /* u88 - SLVC-EC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
};
&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
@@ -169,11 +175,13 @@
reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
+#if 0
usbhub1: usb-hub { /* u84 */
i2c-bus = <&usbhub_i2c1>;
compatible = "microchip,usb5744";
reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
};
+#endif
};
&dwc3_1 {
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 63238c0..b50b83b 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -207,68 +207,71 @@
mbox-names = "tx", "rx";
};
- nvmem-firmware {
+ soc-nvmem {
compatible = "xlnx,zynqmp-nvmem-fw";
- #address-cells = <1>;
- #size-cells = <1>;
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
- soc_revision: soc-revision@0 {
- reg = <0x0 0x4>;
- };
- /* efuse access */
- efuse_dna: efuse-dna@c {
- reg = <0xc 0xc>;
- };
- efuse_usr0: efuse-usr0@20 {
- reg = <0x20 0x4>;
- };
- efuse_usr1: efuse-usr1@24 {
- reg = <0x24 0x4>;
- };
- efuse_usr2: efuse-usr2@28 {
- reg = <0x28 0x4>;
- };
- efuse_usr3: efuse-usr3@2c {
- reg = <0x2c 0x4>;
- };
- efuse_usr4: efuse-usr4@30 {
- reg = <0x30 0x4>;
- };
- efuse_usr5: efuse-usr5@34 {
- reg = <0x34 0x4>;
- };
- efuse_usr6: efuse-usr6@38 {
- reg = <0x38 0x4>;
- };
- efuse_usr7: efuse-usr7@3c {
- reg = <0x3c 0x4>;
- };
- efuse_miscusr: efuse-miscusr@40 {
- reg = <0x40 0x4>;
- };
- efuse_chash: efuse-chash@50 {
- reg = <0x50 0x4>;
- };
- efuse_pufmisc: efuse-pufmisc@54 {
- reg = <0x54 0x4>;
- };
- efuse_sec: efuse-sec@58 {
- reg = <0x58 0x4>;
- };
- efuse_spkid: efuse-spkid@5c {
- reg = <0x5c 0x4>;
- };
- efuse_aeskey: efuse-aeskey@60 {
- reg = <0x60 0x20>;
- };
- efuse_ppk0hash: efuse-ppk0hash@a0 {
- reg = <0xa0 0x30>;
- };
- efuse_ppk1hash: efuse-ppk1hash@d0 {
- reg = <0xd0 0x30>;
- };
- efuse_pufuser: efuse-pufuser@100 {
- reg = <0x100 0x7F>;
+ soc_revision: soc-revision@0 {
+ reg = <0x0 0x4>;
+ };
+ /* efuse access */
+ efuse_dna: efuse-dna@c {
+ reg = <0xc 0xc>;
+ };
+ efuse_usr0: efuse-usr0@20 {
+ reg = <0x20 0x4>;
+ };
+ efuse_usr1: efuse-usr1@24 {
+ reg = <0x24 0x4>;
+ };
+ efuse_usr2: efuse-usr2@28 {
+ reg = <0x28 0x4>;
+ };
+ efuse_usr3: efuse-usr3@2c {
+ reg = <0x2c 0x4>;
+ };
+ efuse_usr4: efuse-usr4@30 {
+ reg = <0x30 0x4>;
+ };
+ efuse_usr5: efuse-usr5@34 {
+ reg = <0x34 0x4>;
+ };
+ efuse_usr6: efuse-usr6@38 {
+ reg = <0x38 0x4>;
+ };
+ efuse_usr7: efuse-usr7@3c {
+ reg = <0x3c 0x4>;
+ };
+ efuse_miscusr: efuse-miscusr@40 {
+ reg = <0x40 0x4>;
+ };
+ efuse_chash: efuse-chash@50 {
+ reg = <0x50 0x4>;
+ };
+ efuse_pufmisc: efuse-pufmisc@54 {
+ reg = <0x54 0x4>;
+ };
+ efuse_sec: efuse-sec@58 {
+ reg = <0x58 0x4>;
+ };
+ efuse_spkid: efuse-spkid@5c {
+ reg = <0x5c 0x4>;
+ };
+ efuse_aeskey: efuse-aeskey@60 {
+ reg = <0x60 0x20>;
+ };
+ efuse_ppk0hash: efuse-ppk0hash@a0 {
+ reg = <0xa0 0x30>;
+ };
+ efuse_ppk1hash: efuse-ppk1hash@d0 {
+ reg = <0xd0 0x30>;
+ };
+ efuse_pufuser: efuse-pufuser@100 {
+ reg = <0x100 0x7F>;
+ };
};
};
@@ -303,11 +306,7 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
- edac {
- compatible = "arm,cortex-a53-edac";
- };
-
- fpga_full: fpga-full {
+ fpga_full: fpga-region {
compatible = "fpga-region";
fpga-mgr = <&zynqmp_pcap>;
#address-cells = <2>;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 8f3aee0..af00ee1 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -2,7 +2,7 @@
config BOARD_COMMON
def_bool y
- depends on !TARGET_SMDKV310 && !TARGET_ARNDALE
+ depends on !TARGET_SMDKV310 && !TARGET_ARNDALE && !TARGET_E850_96
config SPI_BOOTING
bool
@@ -58,6 +58,15 @@
Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
multiple SoCs in this family including Exynos7420.
+config ARCH_EXYNOS9
+ bool "Exynos9 SoC family"
+ select ARM64
+ select BLK
+ select DM_MMC
+ help
+ Samsung Exynos9 SoC family are based on ARMv8 Cortex CPU. There are
+ multiple SoCs in this family including Exynos850.
+
endchoice
if ARCH_EXYNOS4
@@ -228,6 +237,22 @@
endchoice
endif
+if ARCH_EXYNOS9
+
+choice
+ prompt "EXYNOS9 board select"
+
+config TARGET_E850_96
+ bool "WinLink E850-96 board"
+ select ARM64
+ select CLK_EXYNOS
+ select OF_CONTROL
+ select PINCTRL
+ select PINCTRL_EXYNOS850
+
+endchoice
+endif
+
config SYS_SOC
default "exynos"
@@ -252,5 +277,6 @@
source "board/samsung/smdk5420/Kconfig"
source "board/samsung/espresso7420/Kconfig"
source "board/samsung/axy17lte/Kconfig"
+source "board/samsung/e850-96/Kconfig"
endif
diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c
index 8d8c64e..30e5228 100644
--- a/arch/arm/mach-exynos/mmu-arm64.c
+++ b/arch/arm/mach-exynos/mmu-arm64.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
#if IS_ENABLED(CONFIG_EXYNOS7420)
@@ -95,4 +96,37 @@
};
struct mm_region *mem_map = exynos7880_mem_map;
+
+#elif IS_ENABLED(CONFIG_EXYNOS850)
+
+static struct mm_region exynos850_mem_map[] = {
+ {
+ /* Peripheral block */
+ .virt = 0x10000000UL,
+ .phys = 0x10000000UL,
+ .size = SZ_256M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* DDR, 32-bit area */
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = SZ_2G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* DDR, 64-bit area */
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = SZ_2G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ }
+};
+
+struct mm_region *mem_map = exynos850_mem_map;
+
#endif
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
index c1d6b09..ccccf70 100644
--- a/arch/arm/mach-imx/imxrt/Kconfig
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -2,6 +2,7 @@
config IMXRT
bool
+ select BINMAN
select SYS_FSL_ERRATUM_ESDHC135
config IMXRT1020
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 114cce4..15ee2b9 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -356,6 +356,15 @@
select DM_THERMAL
select SUPPORT_SPL
+config TARGET_MX6S_SIELAFF
+ bool "Sielaff i.MX6 Solo Board"
+ depends on MX6S
+ select BINMAN
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
+
config TARGET_MX6SABREAUTO
bool "mx6sabreauto"
depends on MX6QDL
@@ -708,6 +717,7 @@
source "board/liebherr/display5/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"
+source "board/sielaff/imx6dl-sielaff/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/somlabs/visionsom-6ull/Kconfig"
source "board/technexion/pico-imx6/Kconfig"
diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c
index c8c1c78..c5b4ff7 100644
--- a/board/beagle/beagleboneai64/beagleboneai64.c
+++ b/board/beagle/beagleboneai64/beagleboneai64.c
@@ -28,3 +28,17 @@
{
return fdtdec_setup_memory_banksize();
}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ char fdtfile[50];
+
+ snprintf(fdtfile, sizeof(fdtfile), "%s/%s.dtb",
+ CONFIG_TI_FDT_FOLDER_PATH, CONFIG_DEFAULT_DEVICE_TREE);
+
+ env_set("fdtfile", fdtfile);
+
+ return 0;
+}
+#endif
diff --git a/board/beagle/beagleboneai64/beagleboneai64.env b/board/beagle/beagleboneai64/beagleboneai64.env
index 4f0a94a..647b25d 100644
--- a/board/beagle/beagleboneai64/beagleboneai64.env
+++ b/board/beagle/beagleboneai64/beagleboneai64.env
@@ -1,5 +1,4 @@
#include <env/ti/ti_common.env>
-#include <env/ti/default_findfdt.env>
#include <env/ti/mmc.env>
name_kern=Image
diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c
index 1c376de..20819ec 100644
--- a/board/beagle/beagleplay/beagleplay.c
+++ b/board/beagle/beagleplay/beagleplay.c
@@ -27,3 +27,17 @@
{
return fdtdec_setup_memory_banksize();
}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ char fdtfile[50];
+
+ snprintf(fdtfile, sizeof(fdtfile), "%s/%s.dtb",
+ CONFIG_TI_FDT_FOLDER_PATH, CONFIG_DEFAULT_DEVICE_TREE);
+
+ env_set("fdtfile", fdtfile);
+
+ return 0;
+}
+#endif
diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env
index 4f0a94a..647b25d 100644
--- a/board/beagle/beagleplay/beagleplay.env
+++ b/board/beagle/beagleplay/beagleplay.env
@@ -1,5 +1,4 @@
#include <env/ti/ti_common.env>
-#include <env/ti/default_findfdt.env>
#include <env/ti/mmc.env>
name_kern=Image
diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS b/board/freescale/imxrt1050-evk/MAINTAINERS
index a872855..890825b 100644
--- a/board/freescale/imxrt1050-evk/MAINTAINERS
+++ b/board/freescale/imxrt1050-evk/MAINTAINERS
@@ -4,3 +4,4 @@
F: board/freescale/imxrt1050-evk
F: include/configs/imxrt1050-evk.h
F: configs/imxrt1050-evk_defconfig
+F: configs/imxrt1050-evk_fspi_defconfig
diff --git a/board/freescale/imxrt1050-evk/imximage-nor.cfg b/board/freescale/imxrt1050-evk/imximage-nor.cfg
new file mode 100644
index 0000000..829be6c
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imximage-nor.cfg
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024
+ * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM nor
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunately setting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configuration fortunately works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */
+DATA 4 0x400AC044 0x55aaaaaa
+/* Use FLEXRAM_BANK_CFG to config FlexRAM */
+SET_BIT 4 0x400AC040 0x4
diff --git a/board/freescale/imxrt1050-evk/imximage.cfg b/board/freescale/imxrt1050-evk/imximage.cfg
index f1f09fd..b30d852 100644
--- a/board/freescale/imxrt1050-evk/imximage.cfg
+++ b/board/freescale/imxrt1050-evk/imximage.cfg
@@ -29,7 +29,13 @@
* value value to be stored in the register
*/
-/* Set all FlexRAM as OCRAM(01b) */
-DATA 4 0x400AC044 0x55555555
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunately setting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configuration fortunately works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */
+DATA 4 0x400AC044 0x55aaaaaa
/* Use FLEXRAM_BANK_CFG to config FlexRAM */
SET_BIT 4 0x400AC040 0x4
diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
index 4b82ee5..4cc3def 100644
--- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c
+++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
@@ -68,7 +68,12 @@
u32 spl_boot_device(void)
{
- return BOOT_DEVICE_MMC1;
+ /* There is no way to find the boot device so look if there is a valid IVT in RAM for MMC */
+ u32 nor_ivt = *(u32 *)(CONFIG_SYS_LOAD_ADDR - 0xC00);
+
+ if (nor_ivt == 0x402000d1)
+ return BOOT_DEVICE_MMC1;
+ return BOOT_DEVICE_NOR;
}
#endif
diff --git a/board/ge/b1x5v2/MAINTAINERS b/board/ge/b1x5v2/MAINTAINERS
index 3196ddb..7312f4b 100644
--- a/board/ge/b1x5v2/MAINTAINERS
+++ b/board/ge/b1x5v2/MAINTAINERS
@@ -1,6 +1,6 @@
GE B1X5V2 BOARD
-M: Huan 'Kitty' Wang <HuanWang@ge.com>
-M: Ian Ray <ian.ray@ge.com>
+M: Huan 'Kitty' Wang <HuanWang@gehealthcare.com>
+M: Ian Ray <ian.ray@gehealthcare.com>
M: Martyn Welch <martyn.welch@collabora.com>
S: Maintained
F: arch/arm/dts/imx6dl-b1x5v2.dts
diff --git a/board/ge/bx50v3/MAINTAINERS b/board/ge/bx50v3/MAINTAINERS
index c165048..53a8d88 100644
--- a/board/ge/bx50v3/MAINTAINERS
+++ b/board/ge/bx50v3/MAINTAINERS
@@ -1,5 +1,5 @@
GE BX50V3 BOARD
-M: Ian Ray <ian.ray@ge.com>
+M: Ian Ray <ian.ray@gehealthcare.com>
M: Martyn Welch <martyn.welch@collabora.com>
S: Maintained
F: arch/arm/dts/imx6q-b450v3.dts
diff --git a/board/ge/mx53ppd/MAINTAINERS b/board/ge/mx53ppd/MAINTAINERS
index 146a460..19e4ea7 100644
--- a/board/ge/mx53ppd/MAINTAINERS
+++ b/board/ge/mx53ppd/MAINTAINERS
@@ -1,6 +1,5 @@
GE PPD BOARD
-M: Antti Mäentausta <antti.maentausta@ge.com>
-M: Ian Ray <ian.ray@ge.com>
+M: Ian Ray <ian.ray@gehealthcare.com>
M: Martyn Welch <martyn.welch@collabora.com>
S: Maintained
F: arch/arm/dts/imx53-ppd*
diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c
index fed0fbc..ed7a1b7 100644
--- a/board/msc/sm2s_imx8mp/spl.c
+++ b/board/msc/sm2s_imx8mp/spl.c
@@ -168,13 +168,6 @@
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-
-static const iomux_v3_cfg_t ser0_pads[] = {
- MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
@@ -182,8 +175,6 @@
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(ser0_pads, ARRAY_SIZE(ser0_pads));
-
return 0;
}
diff --git a/board/samsung/e850-96/Kconfig b/board/samsung/e850-96/Kconfig
new file mode 100644
index 0000000..f891a90
--- /dev/null
+++ b/board/samsung/e850-96/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_E850_96
+
+config EXYNOS850
+ bool "Exynos850 SoC support"
+ default y
+
+config SYS_BOARD
+ default "e850-96"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "e850-96"
+
+endif
diff --git a/board/samsung/e850-96/MAINTAINERS b/board/samsung/e850-96/MAINTAINERS
new file mode 100644
index 0000000..e8b9365
--- /dev/null
+++ b/board/samsung/e850-96/MAINTAINERS
@@ -0,0 +1,9 @@
+WINLINK E850-96 BOARD
+M: Sam Protsenko <semen.protsenko@linaro.org>
+S: Maintained
+F: arch/arm/dts/exynos850-e850-96-u-boot.dtsi
+F: arch/arm/dts/exynos850-e850-96.dts
+F: board/samsung/e850-96/
+F: configs/e850-96_defconfig
+F: doc/board/samsung/e850-96.rst
+F: include/configs/e850-96.h
diff --git a/board/samsung/e850-96/Makefile b/board/samsung/e850-96/Makefile
new file mode 100644
index 0000000..301c223
--- /dev/null
+++ b/board/samsung/e850-96/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020, Linaro Limited
+# Sam Protsenko <semen.protsenko@linaro.org>
+
+obj-y := e850-96.o
diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c
new file mode 100644
index 0000000..a00d81b
--- /dev/null
+++ b/board/samsung/e850-96/e850-96.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020, Linaro Limited
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ */
+
+#include <init.h>
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/board/sielaff/imx6dl-sielaff/Kconfig b/board/sielaff/imx6dl-sielaff/Kconfig
new file mode 100644
index 0000000..1b74a7d
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX6S_SIELAFF
+
+config SYS_BOARD
+ string
+ default "imx6dl-sielaff"
+
+config SYS_VENDOR
+ string
+ default "sielaff"
+
+config SYS_CONFIG_NAME
+ string
+ default "imx6dl-sielaff"
+
+endif
diff --git a/board/sielaff/imx6dl-sielaff/MAINTAINERS b/board/sielaff/imx6dl-sielaff/MAINTAINERS
new file mode 100644
index 0000000..c0d3a09
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/MAINTAINERS
@@ -0,0 +1,9 @@
+Sielaff i.MX6 Solo Board
+M: Frieder Schrempf <frieder.schrempf@kontron.de>
+S: Maintained
+F: arch/arm/dts/imx6dl-sielaff*
+F: board/sielaff/imx6dl-sielaff/
+F: configs/imx6dl_sielaff_defconfig
+F: doc/board/sielaff/imx6dl-sielaff.rst
+F: include/configs/imx6dl-sielaff.h
+F: include/configs/kontron-sl-mx6ul.h
diff --git a/board/sielaff/imx6dl-sielaff/Makefile b/board/sielaff/imx6dl-sielaff/Makefile
new file mode 100644
index 0000000..65cecfe
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2022 Kontron Electronics GmbH
+
+ifdef CONFIG_SPL_BUILD
+obj-y := spl.o
+else
+obj-y := imx6dl-sielaff.o
+endif
diff --git a/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c
new file mode 100644
index 0000000..4da084ed
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include <compiler.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/io.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const iomux_v3_cfg_t nfc_pads[] = {
+ MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(nfc_pads,
+ ARRAY_SIZE(nfc_pads));
+
+ /* gate ENFC_CLK_ROOT clock first,before clk source switch */
+ clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable ENFC_CLK_ROOT clock */
+ setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+
+int board_init(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+
+ setup_gpmi_nand();
+
+ /* Enable SPI2 clock */
+ enable_spi_clk(true, 1);
+
+ /*
+ * Configure clock output for USB hub
+ * 1. Disabling CLK01 and CLK02
+ */
+ clrbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKOL_EN);
+ clrbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKO2_EN_OFFSET);
+
+ /*
+ * 2. Setting ccm timer - osc_clk (24 MHz) divide by 2 -> 12 Mhz
+ * CLK02_DIV: 001b CLK02_SEL: 01110b -> 0010 1110b -> 0x2e
+ */
+ reg = readl(&mxc_ccm->ccosr);
+ reg &= ~MXC_CCM_CCOSR_CKO2_SEL_MASK;
+ reg &= ~MXC_CCM_CCOSR_CKO2_DIV_MASK;
+ reg |= (0x2e << MXC_CCM_CCOSR_CKO2_SEL_OFFSET);
+ writel(reg, &mxc_ccm->ccosr);
+
+ /* 3. Enabling CLK02 on output CCM_CLK01 */
+ setbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CLK_OUT_SEL);
+ setbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKO2_EN_OFFSET);
+
+ return 0;
+}
diff --git a/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.env b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.env
new file mode 100644
index 0000000..9aafa3c
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.env
@@ -0,0 +1,114 @@
+blkloadfdt=fatload ${device} ${devnum}:${partnum} ${fdt_addr} ${load_fdt_file}
+blkloadimage=fatload ${device} ${devnum}:${partnum} ${loadaddr} ${load_image}
+boot_devices=usb mmc ubi
+bootargs_base=vt.global_cursor_default=0 consoleblank=0 cma=200M fbcon=rotate:1
+bootdelay=3
+bootdir=
+console=ttymxc1,115200
+ethact=FEC0
+fdt_addr=0x18000000
+fdt_file_legacy=imx6dl_sielaff.dtb
+fdt_file=imx6dl-sielaff.dtb
+fdt_high=0xffffffff
+image_legacy=zImage
+image=fitImage
+initrd_high=0xffffffff
+ip_dyn=no
+loadaddr=0x12000000
+mmcargs=setenv bootargs ${bootargs_base} console=${console} root=${mmcroot}
+mmcroot=/dev/mmcblk2p2 rootwait rw
+ramdisk_addr=0x18C00000
+script=boot.scr
+touch_rst_gpio=2
+touch_irq_gpio=146
+ubiargs=setenv bootargs ${bootargs_base} console=${console} rootfstype=ubifs ubi.mtd=0 root=ubi0_0 rw
+ubiloadfdt=ubifsload ${fdt_addr} /boot/${load_fdt_file}
+ubiloadimage=ubifsload ${loadaddr} /boot/${load_image}
+usb_pgood_delay=2000
+usbargs=setenv bootargs ${bootargs_base} console=${console} root=${usbroot}
+usbroot=/dev/sda2 rootwait rw
+
+bootcmd=
+ for b in ${boot_devices}; do
+ if test ${b} = mmc; then
+ run mmcboot;
+ fi;
+ if test ${b} = net; then
+ run netboot;
+ fi;
+ if test ${b} = ubi; then
+ run ubiboot;
+ fi;
+ if test ${b} = usb; then
+ run usbboot;
+ fi;
+ done;
+
+boot=
+ load_image=${image};
+ run loadimagecmd;
+ if test $? = 0; then
+ imxtract ${loadaddr} fdt-${fdt_file} ${fdt_addr};
+ run detect_touch;
+ bootm ${loadaddr} - ${fdt_addr};
+ else
+ load_image=${image_legacy};
+ load_fdt_file=${fdt_file_legacy};
+ run loadimagecmd;
+ run loadfdtcmd;
+ if test $? = 0; then
+ run detect_touch;
+ bootz ${loadaddr} - ${fdt_addr};
+ fi;
+ fi;
+
+detect_touch=
+ gpio clear ${touch_irq_gpio};
+ gpio clear ${touch_rst_gpio};
+ sleep 0.02;
+ gpio set ${touch_rst_gpio};
+ sleep 0.1;
+ gpio input ${touch_irq_gpio};
+ i2c dev 2;
+ fdt addr ${fdt_addr};
+ if i2c probe 0x55; then
+ echo 'Detected Sitronix Touch';
+ fdt set /soc/bus@2100000/i2c@21a8000/touchscreen@55 status okay;
+ else
+ if i2c probe 0x5d; then
+ echo 'Detected Goodix Touch';
+ fdt set /soc/bus@2100000/i2c@21a8000/touchscreen@5d status okay;
+ fi;
+ fi;
+ gpio clear ${touch_rst_gpio};
+
+mmcboot=
+ echo Booting from MMC ...;
+ run mmcargs;
+ device=mmc;
+ devnum=2;
+ partnum=1;
+ setenv loadimagecmd ${blkloadimage};
+ setenv loadfdtcmd ${blkloadfdt};
+ run boot;
+
+ubiboot=
+ echo Booting from NAND (UBI);
+ run ubiargs;
+ ubi part rootfs;
+ ubifsmount ubi0;
+ setenv loadimagecmd ${ubiloadimage};
+ setenv loadfdtcmd ${ubiloadfdt};
+ load_image=${image};
+ run boot;
+
+usbboot=
+ echo Booting from USB Storage ...;
+ run usbargs;
+ usb start;
+ device=usb;
+ devnum=0;
+ partnum=1;
+ setenv loadimagecmd ${blkloadimage};
+ setenv loadfdtcmd ${blkloadfdt};
+ run boot;
diff --git a/board/sielaff/imx6dl-sielaff/spl.c b/board/sielaff/imx6dl-sielaff/spl.c
new file mode 100644
index 0000000..6815952
--- /dev/null
+++ b/board/sielaff/imx6dl-sielaff/spl.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/sections.h>
+#include <init.h>
+#include <spl.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define GPIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static const iomux_v3_cfg_t ecspi2_pads[] = {
+ MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t uart2_pads[] = {
+ MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 4)
+#define SPI2_CS_GPIO IMX_GPIO_NR(5, 29)
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
+ ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
+ i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static int mx6ssielaff_dcd_table[] = {
+ 0x020e0774, 0x000C0000,
+ 0x020e0754, 0x00000000,
+ 0x020e04ac, 0x00000030,
+ 0x020e04b0, 0x00000030,
+ 0x020e0464, 0x00000030,
+ 0x020e0490, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e0494, 0x00000030,
+ 0x020e04a0, 0x00000000,
+ 0x020e04b4, 0x00000030,
+ 0x020e04b8, 0x00000030,
+ 0x020e076c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e04bc, 0x00000030,
+ 0x020e04c0, 0x00000030,
+ 0x020e04c4, 0x00000030,
+ 0x020e04c8, 0x00000030,
+ 0x020e0760, 0x00020000,
+ 0x020e0764, 0x00000030,
+ 0x020e0770, 0x00000030,
+ 0x020e0778, 0x00000030,
+ 0x020e077c, 0x00000030,
+ 0x020e0470, 0x00000030,
+ 0x020e0474, 0x00000030,
+ 0x020e0478, 0x00000030,
+ 0x020e047c, 0x00000030,
+ 0x021b001c, 0x00008000,
+ 0x021b0800, 0xA1390003,
+ 0x021b080c, 0x00350035,
+ 0x021b0810, 0x002A0032,
+ 0x021b083c, 0x02340234,
+ 0x021b0840, 0x02200220,
+ 0x021b0848, 0x4650504E,
+ 0x021b0850, 0x3A342E34,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b08b8, 0x00000800,
+ 0x021b0004, 0x0002002D,
+ 0x021b0008, 0x00333040,
+ 0x021b000c, 0x676B52F3,
+ 0x021b0010, 0xB66D8B63,
+ 0x021b0014, 0x01FF00DB,
+ 0x021b0018, 0x00011740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026D2,
+ 0x021b0030, 0x006B1023,
+ 0x021b0040, 0x00000027,
+ 0x021b0000, 0x84190000,
+ 0x021b001c, 0x02008032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x15208030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00007800,
+ 0x021b0818, 0x00022227,
+ 0x021b0004, 0x0002556D,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+ 0x020c4068, 0x00C03F3F,
+ 0x020c406c, 0x0030FC03,
+ 0x020c4070, 0x0FFFC000,
+ 0x020c4074, 0x3FF00000,
+ 0x020c4078, 0xFFFFF300,
+ 0x020c407c, 0x0F0000C3,
+ 0x020c4080, 0x000003FF,
+ 0x020e0010, 0xF00000CF,
+ 0x020e0018, 0x007F007F,
+ 0x020e001c, 0x007F007F,
+};
+
+static void ddr_init(int *table, int size)
+{
+ int i;
+
+ for (i = 0; i < size / 2 ; i++)
+ writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+ ddr_init(mx6ssielaff_dcd_table, ARRAY_SIZE(mx6ssielaff_dcd_table));
+}
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+ return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+ ? SPI2_CS_GPIO : -1;
+}
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
+ gpio_request(SPI2_CS_GPIO, "spi2_cs0");
+ gpio_direction_output(SPI2_CS_GPIO, 1);
+ enable_spi_clk(true, 1);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* IOMUX UART */
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* SPI */
+ setup_spi();
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ u32 bootdev = spl_boot_device();
+
+ /*
+ * The default boot fuse settings use the SD card (MMC1) as primary
+ * boot device, but allow SPI NOR as a fallback boot device.
+ * We can't detect the fallback case and spl_boot_device() will return
+ * BOOT_DEVICE_MMC1 despite the actual boot device being SPI NOR.
+ * Therefore we try to load U-Boot proper vom SPI NOR after loading
+ * from MMC has failed.
+ */
+ spl_boot_list[0] = bootdev;
+
+ switch (bootdev) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+ break;
+ }
+}
diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env
index a6d967e..334374a 100644
--- a/board/ti/am62ax/am62ax.env
+++ b/board/ti/am62ax/am62ax.env
@@ -1,5 +1,4 @@
#include <env/ti/ti_common.env>
-#include <env/ti/default_findfdt.env>
#include <env/ti/mmc.env>
name_kern=Image
diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c
index cd3360a..62d3664 100644
--- a/board/ti/am62ax/evm.c
+++ b/board/ti/am62ax/evm.c
@@ -13,6 +13,8 @@
#include <fdt_support.h>
#include <spl.h>
+#include "../common/fdt_ops.h"
+
int board_init(void)
{
return 0;
@@ -27,3 +29,11 @@
{
return fdtdec_setup_memory_banksize();
}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ ti_set_fdt_env(NULL, NULL);
+ return 0;
+}
+#endif
diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env
index e53a55c..9cb186c 100644
--- a/board/ti/am62x/am62x.env
+++ b/board/ti/am62x/am62x.env
@@ -1,5 +1,4 @@
#include <env/ti/ti_common.env>
-#include <env/ti/default_findfdt.env>
#include <env/ti/mmc.env>
name_kern=Image
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index 88e0215..b3e8680 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -19,6 +19,8 @@
#include <asm/arch/hardware.h>
#include <dm/uclass.h>
+#include "../common/fdt_ops.h"
+
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(SPLASH_SCREEN)
@@ -54,6 +56,14 @@
return fdtdec_setup_mem_size_base();
}
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ ti_set_fdt_env(NULL, NULL);
+ return 0;
+}
+#endif
+
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env
index efd736b..9a8812d 100644
--- a/board/ti/am64x/am64x.env
+++ b/board/ti/am64x/am64x.env
@@ -2,14 +2,6 @@
#include <env/ti/mmc.env>
#include <env/ti/k3_dfu.env>
-findfdt=
- if test $board_name = am64x_gpevm; then
- setenv name_fdt ti/k3-am642-evm.dtb; fi;
- if test $board_name = am64x_skevm; then
- setenv name_fdt ti/k3-am642-sk.dtb; fi;
- if test $name_fdt = undefined; then
- echo WARNING: Could not determine device tree to use; fi;
- setenv fdtfile ${name_fdt}
name_kern=Image
console=ttyS2,115200n8
args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 ${mtdparts}
@@ -43,7 +35,6 @@
usbboot=setenv boot usb;
setenv bootpart 0:2;
usb start;
- run findfdt;
run init_usb;
run get_kern_usb;
run get_fdt_usb;
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index a7ca6be..b8de69d 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -16,6 +16,7 @@
#include <env.h>
#include "../common/board_detect.h"
+#include "../common/fdt_ops.h"
#define board_is_am64x_gpevm() (board_ti_k3_is("AM64-GPEVM") || \
board_ti_k3_is("AM64-EVM") || \
@@ -181,6 +182,12 @@
}
#ifdef CONFIG_BOARD_LATE_INIT
+static struct ti_fdt_map ti_am64_evm_fdt_map[] = {
+ {"am64x_gpevm", "k3-am642-evm.dtb"},
+ {"am64x_skevm", "k3-am642-sk.dtb"},
+ { /* Sentinel. */ }
+};
+
static void setup_board_eeprom_env(void)
{
char *name = "am64x_gpevm";
@@ -198,6 +205,7 @@
invalid_eeprom:
set_board_info_env_am6(name);
+ ti_set_fdt_env(name, ti_am64_evm_fdt_map);
}
static void setup_serial(void)
diff --git a/board/ti/am65x/am65x.env b/board/ti/am65x/am65x.env
index 286b9c3..814374d 100644
--- a/board/ti/am65x/am65x.env
+++ b/board/ti/am65x/am65x.env
@@ -5,9 +5,6 @@
#include <env/ti/k3_rproc.env>
#endif
-findfdt=
- setenv name_fdt ti/k3-am654-base-board.dtb;
- setenv fdtfile ${name_fdt}
name_kern=Image
console=ttyS2,115200n8
args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index df20902..3109c9a 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -22,6 +22,7 @@
#include <linux/printk.h>
#include "../common/board_detect.h"
+#include "../common/fdt_ops.h"
#define board_is_am65x_base_board() board_ti_is("AM6-COMPROCEVM")
@@ -141,6 +142,7 @@
invalid_eeprom:
set_board_info_env_am6(name);
+ ti_set_fdt_env(NULL, NULL);
}
static int init_daughtercard_det_gpio(char *gpio_name, struct gpio_desc *desc)
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index 49edd98..de44e4d 100644
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -49,3 +49,15 @@
imply CMD_SPI
imply CMD_TIME
imply CMD_USB if USB
+
+config TI_FDT_FOLDER_PATH
+ string "Location of Folder path where dtb is present"
+ default "ti/davinci" if ARCH_DAVINCI
+ default "ti/keystone" if ARCH_KEYSTONE
+ default "ti/omap" if ARCH_OMAP2PLUS
+ default "ti" if ARCH_K3
+ depends on ARCH_DAVINCI || ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
+ help
+ Folder path for kernel device tree default.
+ This is used along with fdtfile path to locate the kernel
+ device tree blob.
diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile
index 26bf12e..5ac361b 100644
--- a/board/ti/common/Makefile
+++ b/board/ti/common/Makefile
@@ -3,3 +3,4 @@
obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
obj-${CONFIG_CMD_EXTENSION} += cape_detect.o
+obj-${CONFIG_OF_LIBFDT} += fdt_ops.o
diff --git a/board/ti/common/fdt_ops.c b/board/ti/common/fdt_ops.c
new file mode 100644
index 0000000..eb917be
--- /dev/null
+++ b/board/ti/common/fdt_ops.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Library to support FDT file operations which are common
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <env.h>
+#include <vsprintf.h>
+#include "fdt_ops.h"
+
+void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map)
+{
+ char *fdt_file_name = NULL;
+ char fdtfile[TI_FDT_FILE_MAX];
+
+ if (board_name) {
+ while (fdt_map) {
+ /* Check for NULL terminator in the list */
+ if (!fdt_map->board_name)
+ break;
+ if (!strncmp(fdt_map->board_name, board_name, TI_BOARD_NAME_MAX)) {
+ fdt_file_name = fdt_map->fdt_file_name;
+ break;
+ }
+ fdt_map++;
+ }
+ }
+
+ /* match not found OR null board_name */
+ if (!fdt_file_name) {
+ /*
+ * Prioritize CONFIG_DEFAULT_FDT_FILE - if that is not defined,
+ * or is empty, then use CONFIG_DEFAULT_DEVICE_TREE
+ */
+#ifdef CONFIG_DEFAULT_FDT_FILE
+ if (strlen(CONFIG_DEFAULT_FDT_FILE)) {
+ snprintf(fdtfile, sizeof(fdtfile), "%s/%s",
+ CONFIG_TI_FDT_FOLDER_PATH, CONFIG_DEFAULT_FDT_FILE);
+ } else
+#endif
+ {
+ snprintf(fdtfile, sizeof(fdtfile), "%s/%s.dtb",
+ CONFIG_TI_FDT_FOLDER_PATH, CONFIG_DEFAULT_DEVICE_TREE);
+ }
+ } else {
+ snprintf(fdtfile, sizeof(fdtfile), "%s/%s", CONFIG_TI_FDT_FOLDER_PATH,
+ fdt_file_name);
+ }
+
+ env_set("fdtfile", fdtfile);
+
+ /*
+ * XXX: DEPRECATION WARNING: 2 u-boot versions (2024.10).
+ *
+ * Maintain compatibility with downstream scripts that may be using
+ * name_fdt
+ */
+ if (board_name)
+ env_set("name_fdt", fdtfile);
+ /* Also set the findfdt legacy script to warn users to stop using this */
+ env_set("findfdt",
+ "echo WARN: fdtfile already set. Stop using findfdt in script");
+}
diff --git a/board/ti/common/fdt_ops.h b/board/ti/common/fdt_ops.h
new file mode 100644
index 0000000..5d30499
--- /dev/null
+++ b/board/ti/common/fdt_ops.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Library to support common device tree manipulation for TI EVMs
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#ifndef __FDT_OPS_H
+#define __FDT_OPS_H
+
+#define TI_BOARD_NAME_MAX 20
+#define TI_FDT_FILE_MAX 200
+
+/**
+ * struct ti_fdt_map - mapping of device tree blob name to board name
+ * @board_name: board_name up to TI_BOARD_NAME_MAX long
+ * @fdt_file_name: device tree blob name as described by kernel
+ */
+struct ti_fdt_map {
+ const char *board_name;
+ char *fdt_file_name;
+};
+
+/**
+ * ti_set_fdt_env - Find the correct device tree file name based on the
+ * board name and set 'fdtfile' env variable with correct folder
+ * structure appropriate to the architecture and Linux kernel's
+ * 'make install_dtbs' conventions. This function is invoked typically
+ * as part of board_late_init.
+ *
+ * fdt name is picked by:
+ * a) If a board name match is found, use the match
+ * b) If not, CONFIG_DEFAULT_FDT_FILE (Boot OS device tree) if that is defined
+ * and not null
+ * c) If not, Use CONFIG_DEFAULT_DEVICE_TREE (DT control for bootloader)
+ *
+ * @board_name: match to search with (max of TI_BOARD_NAME_MAX chars)
+ * @fdt_map: NULL terminated array of device tree file name matches.
+ */
+void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map);
+
+#endif /* __FDT_OPS_H */
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index b77cffc..9dc3ed6 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -16,6 +16,7 @@
#include <dm.h>
#include "../common/board_detect.h"
+#include "../common/fdt_ops.h"
#define board_is_j721e_som() (board_ti_k3_is("J721EX-PM1-SOM") || \
board_ti_k3_is("J721EX-PM2-SOM"))
@@ -353,6 +354,12 @@
#endif
#ifdef CONFIG_BOARD_LATE_INIT
+static struct ti_fdt_map ti_j721e_evm_fdt_map[] = {
+ {"j721e", "k3-j721e-common-proc-board.dtb"},
+ {"j721e-sk", "k3-j721e-sk.dtb"},
+ {"j7200", "k3-j7200-common-proc-board.dtb"},
+ { /* Sentinel. */ }
+};
static void setup_board_eeprom_env(void)
{
char *name = "j721e";
@@ -372,6 +379,7 @@
invalid_eeprom:
set_board_info_env_am6(name);
+ ti_set_fdt_env(name, ti_j721e_evm_fdt_map);
}
static void setup_serial(void)
diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index cb27bf5..38bfd7d 100644
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -7,16 +7,6 @@
#include <env/ti/k3_rproc.env>
#endif
-default_device_tree=ti/k3-j721e-common-proc-board.dtb
-findfdt=
- setenv name_fdt ${default_device_tree};
- if test $board_name = j721e; then
- setenv name_fdt ti/k3-j721e-common-proc-board.dtb; fi;
- if test $board_name = j7200; then
- setenv name_fdt ti/k3-j7200-common-proc-board.dtb; fi;
- if test $board_name = j721e-eaik || test $board_name = j721e-sk; then
- setenv name_fdt ti/k3-j721e-sk.dtb; fi;
- setenv fdtfile ${name_fdt}
name_kern=Image
console=ttyS2,115200n8
args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 1220cd8..5a0281d 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -23,6 +23,7 @@
#include <dm/root.h>
#include "../common/board_detect.h"
+#include "../common/fdt_ops.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -114,6 +115,12 @@
return 0;
}
+static struct ti_fdt_map ti_j721s2_evm_fdt_map[] = {
+ {"j721s2", "k3-j721s2-common-proc-board.dtb"},
+ {"am68-sk", "k3-am68-sk-base-board.dtb"},
+ { /* Sentinel. */ }
+};
+
static void setup_board_eeprom_env(void)
{
char *name = "j721s2";
@@ -131,6 +138,7 @@
invalid_eeprom:
set_board_info_env_am6(name);
+ ti_set_fdt_env(name, ti_j721s2_evm_fdt_map);
}
static void setup_serial(void)
diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env
index 64e3d9d..9a03b9f 100644
--- a/board/ti/j721s2/j721s2.env
+++ b/board/ti/j721s2/j721s2.env
@@ -7,14 +7,6 @@
#include <env/ti/k3_rproc.env>
#endif
-default_device_tree=ti/k3-j721s2-common-proc-board.dtb
-findfdt=
- setenv name_fdt ${default_device_tree};
- if test $board_name = j721s2; then \
- setenv name_fdt ti/k3-j721s2-common-proc-board.dtb; fi;
- if test $board_name = am68-sk; then
- setenv name_fdt ti/k3-am68-sk-base-board.dtb; fi;
- setenv fdtfile ${name_fdt}
name_kern=Image
console=ttyS2,115200n8
args_all=setenv optargs earlycon=ns16550a,mmio32,0x02880000
diff --git a/board/ti/omap3evm/Kconfig b/board/ti/omap3evm/Kconfig
index 08a8aa2..cd71fe0 100644
--- a/board/ti/omap3evm/Kconfig
+++ b/board/ti/omap3evm/Kconfig
@@ -9,4 +9,6 @@
config SYS_CONFIG_NAME
default "omap3_evm"
+source "board/ti/common/Kconfig"
+
endif
diff --git a/board/ti/panda/Kconfig b/board/ti/panda/Kconfig
index 8f277b6..5912f69 100644
--- a/board/ti/panda/Kconfig
+++ b/board/ti/panda/Kconfig
@@ -9,4 +9,6 @@
config SYS_CONFIG_NAME
default "omap4_panda"
+source "board/ti/common/Kconfig"
+
endif
diff --git a/board/ti/sdp4430/Kconfig b/board/ti/sdp4430/Kconfig
index 36f1852..65e9107 100644
--- a/board/ti/sdp4430/Kconfig
+++ b/board/ti/sdp4430/Kconfig
@@ -12,4 +12,6 @@
config CMD_BAT
bool "Enable board-specific battery command"
+source "board/ti/common/Kconfig"
+
endif
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 9f50090..ba49eb7 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -18,6 +18,7 @@
#include <ahci.h>
#include <scsi.h>
#include <soc.h>
+#include <spl.h>
#include <malloc.h>
#include <memalign.h>
#include <wdt.h>
diff --git a/cmd/avb.c b/cmd/avb.c
index 783f51b..8fbd48e 100644
--- a/cmd/avb.c
+++ b/cmd/avb.c
@@ -1,8 +1,6 @@
-
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018, Linaro Limited
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <avb_verify.h>
@@ -13,6 +11,7 @@
#include <mmc.h>
#define AVB_BOOTARGS "avb_bootargs"
+
static struct AvbOps *avb_ops;
int do_avb_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
@@ -30,8 +29,10 @@
avb_ops = avb_ops_alloc(mmc_dev);
if (avb_ops)
return CMD_RET_SUCCESS;
+ else
+ printf("Can't allocate AvbOps");
- printf("Failed to initialize avb2\n");
+ printf("Failed to initialize AVB\n");
return CMD_RET_FAILURE;
}
@@ -43,10 +44,11 @@
s64 offset;
size_t bytes, bytes_read = 0;
void *buffer;
+ int ret;
if (!avb_ops) {
- printf("AVB 2.0 is not initialized, please run 'avb init'\n");
- return CMD_RET_USAGE;
+ printf("AVB is not initialized, please run 'avb init <id>'\n");
+ return CMD_RET_FAILURE;
}
if (argc != 5)
@@ -57,14 +59,15 @@
bytes = hextoul(argv[3], NULL);
buffer = (void *)hextoul(argv[4], NULL);
- if (avb_ops->read_from_partition(avb_ops, part, offset, bytes,
- buffer, &bytes_read) ==
- AVB_IO_RESULT_OK) {
+ ret = avb_ops->read_from_partition(avb_ops, part, offset,
+ bytes, buffer, &bytes_read);
+ if (ret == AVB_IO_RESULT_OK) {
printf("Read %zu bytes\n", bytes_read);
return CMD_RET_SUCCESS;
}
- printf("Failed to read from partition\n");
+ printf("Failed to read from partition '%s', err = %d\n",
+ part, ret);
return CMD_RET_FAILURE;
}
@@ -76,10 +79,11 @@
s64 offset;
size_t bytes, bytes_read = 0;
char *buffer;
+ int ret;
if (!avb_ops) {
- printf("AVB 2.0 is not initialized, please run 'avb init'\n");
- return CMD_RET_USAGE;
+ printf("AVB is not initialized, please run 'avb init <id>'\n");
+ return CMD_RET_FAILURE;
}
if (argc != 4)
@@ -96,8 +100,9 @@
}
memset(buffer, 0, bytes);
- if (avb_ops->read_from_partition(avb_ops, part, offset, bytes, buffer,
- &bytes_read) == AVB_IO_RESULT_OK) {
+ ret = avb_ops->read_from_partition(avb_ops, part, offset,
+ bytes, buffer, &bytes_read);
+ if (ret == AVB_IO_RESULT_OK) {
printf("Requested %zu, read %zu bytes\n", bytes, bytes_read);
printf("Data: ");
for (int i = 0; i < bytes_read; i++)
@@ -109,7 +114,8 @@
return CMD_RET_SUCCESS;
}
- printf("Failed to read from partition\n");
+ printf("Failed to read from partition '%s', err = %d\n",
+ part, ret);
free(buffer);
return CMD_RET_FAILURE;
@@ -122,9 +128,10 @@
s64 offset;
size_t bytes;
void *buffer;
+ int ret;
if (!avb_ops) {
- printf("AVB 2.0 is not initialized, run 'avb init' first\n");
+ printf("AVB is not initialized, please run 'avb init <id>'\n");
return CMD_RET_FAILURE;
}
@@ -136,13 +143,15 @@
bytes = hextoul(argv[3], NULL);
buffer = (void *)hextoul(argv[4], NULL);
- if (avb_ops->write_to_partition(avb_ops, part, offset, bytes, buffer) ==
- AVB_IO_RESULT_OK) {
+ ret = avb_ops->write_to_partition(avb_ops, part, offset,
+ bytes, buffer);
+ if (ret == AVB_IO_RESULT_OK) {
printf("Wrote %zu bytes\n", bytes);
return CMD_RET_SUCCESS;
}
- printf("Failed to write in partition\n");
+ printf("Failed to write in partition '%s', err = %d\n",
+ part, ret);
return CMD_RET_FAILURE;
}
@@ -152,9 +161,10 @@
{
size_t index;
u64 rb_idx;
+ int ret;
if (!avb_ops) {
- printf("AVB 2.0 is not initialized, run 'avb init' first\n");
+ printf("AVB is not initialized, please run 'avb init <id>'\n");
return CMD_RET_FAILURE;
}
@@ -163,13 +173,14 @@
index = (size_t)hextoul(argv[1], NULL);
- if (avb_ops->read_rollback_index(avb_ops, index, &rb_idx) ==
- AVB_IO_RESULT_OK) {
+ ret = avb_ops->read_rollback_index(avb_ops, index, &rb_idx);
+ if (ret == AVB_IO_RESULT_OK) {
printf("Rollback index: %llx\n", rb_idx);
return CMD_RET_SUCCESS;
}
- printf("Failed to read rollback index\n");
+ printf("Failed to read rollback index id = %zu, err = %d\n",
+ index, ret);
return CMD_RET_FAILURE;
}
@@ -179,9 +190,10 @@
{
size_t index;
u64 rb_idx;
+ int ret;
if (!avb_ops) {
- printf("AVB 2.0 is not initialized, run 'avb init' first\n");
+ printf("AVB is not initialized, please run 'avb init <id>'\n");
return CMD_RET_FAILURE;
}
@@ -191,11 +203,12 @@
index = (size_t)hextoul(argv[1], NULL);
rb_idx = hextoul(argv[2], NULL);
- if (avb_ops->write_rollback_index(avb_ops, index, rb_idx) ==
- AVB_IO_RESULT_OK)
+ ret = avb_ops->write_rollback_index(avb_ops, index, rb_idx);
+ if (ret == AVB_IO_RESULT_OK)
return CMD_RET_SUCCESS;
- printf("Failed to write rollback index\n");
+ printf("Failed to write rollback index id = %zu, err = %d\n",
+ index, ret);
return CMD_RET_FAILURE;
}
@@ -205,9 +218,10 @@
{
const char *part;
char buffer[UUID_STR_LEN + 1];
+ int ret;
if (!avb_ops) {
- printf("AVB 2.0 is not initialized, run 'avb init' first\n");
+ printf("AVB is not initialized, please run 'avb init <id>'\n");
return CMD_RET_FAILURE;
}
@@ -216,14 +230,16 @@
part = argv[1];
- if (avb_ops->get_unique_guid_for_partition(avb_ops, part, buffer,
- UUID_STR_LEN + 1) ==
- AVB_IO_RESULT_OK) {
+ ret = avb_ops->get_unique_guid_for_partition(avb_ops, part,
+ buffer,
+ UUID_STR_LEN + 1);
+ if (ret == AVB_IO_RESULT_OK) {
printf("'%s' UUID: %s\n", part, buffer);
return CMD_RET_SUCCESS;
}
- printf("Failed to read UUID\n");
+ printf("Failed to read partition '%s' UUID, err = %d\n",
+ part, ret);
return CMD_RET_FAILURE;
}
@@ -234,15 +250,17 @@
const char * const requested_partitions[] = {"boot", NULL};
AvbSlotVerifyResult slot_result;
AvbSlotVerifyData *out_data;
+ enum avb_boot_state boot_state;
char *cmdline;
char *extra_args;
char *slot_suffix = "";
+ int ret;
bool unlocked = false;
int res = CMD_RET_FAILURE;
if (!avb_ops) {
- printf("AVB 2.0 is not initialized, run 'avb init' first\n");
+ printf("AVB is not initialized, please run 'avb init <id>'\n");
return CMD_RET_FAILURE;
}
@@ -255,9 +273,10 @@
printf("## Android Verified Boot 2.0 version %s\n",
avb_version_string());
- if (avb_ops->read_is_device_unlocked(avb_ops, &unlocked) !=
- AVB_IO_RESULT_OK) {
- printf("Can't determine device lock state.\n");
+ ret = avb_ops->read_is_device_unlocked(avb_ops, &unlocked);
+ if (ret != AVB_IO_RESULT_OK) {
+ printf("Can't determine device lock state, err = %d\n",
+ ret);
return CMD_RET_FAILURE;
}
@@ -269,18 +288,23 @@
AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE,
&out_data);
- switch (slot_result) {
- case AVB_SLOT_VERIFY_RESULT_OK:
- /* Until we don't have support of changing unlock states, we
- * assume that we are by default in locked state.
- * So in this case we can boot only when verification is
- * successful; we also supply in cmdline GREEN boot state
- */
+ /*
+ * LOCKED devices with custom root of trust setup is not supported (YELLOW)
+ */
+ if (slot_result == AVB_SLOT_VERIFY_RESULT_OK) {
printf("Verification passed successfully\n");
- /* export additional bootargs to AVB_BOOTARGS env var */
+ /*
+ * ORANGE state indicates that device may be freely modified.
+ * Device integrity is left to the user to verify out-of-band.
+ */
+ if (unlocked)
+ boot_state = AVB_ORANGE;
+ else
+ boot_state = AVB_GREEN;
- extra_args = avb_set_state(avb_ops, AVB_GREEN);
+ /* export boot state to AVB_BOOTARGS env var */
+ extra_args = avb_set_state(avb_ops, boot_state);
if (extra_args)
cmdline = append_cmd_line(out_data->cmdline,
extra_args);
@@ -290,30 +314,8 @@
env_set(AVB_BOOTARGS, cmdline);
res = CMD_RET_SUCCESS;
- break;
- case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION:
- printf("Verification failed\n");
- break;
- case AVB_SLOT_VERIFY_RESULT_ERROR_IO:
- printf("I/O error occurred during verification\n");
- break;
- case AVB_SLOT_VERIFY_RESULT_ERROR_OOM:
- printf("OOM error occurred during verification\n");
- break;
- case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA:
- printf("Corrupted dm-verity metadata detected\n");
- break;
- case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION:
- printf("Unsupported version avbtool was used\n");
- break;
- case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX:
- printf("Checking rollback index failed\n");
- break;
- case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED:
- printf("Public key was rejected\n");
- break;
- default:
- printf("Unknown error occurred\n");
+ } else {
+ printf("Verification failed, reason: %s\n", str_avb_slot_error(slot_result));
}
if (out_data)
@@ -326,9 +328,10 @@
int argc, char *const argv[])
{
bool unlock;
+ int ret;
if (!avb_ops) {
- printf("AVB not initialized, run 'avb init' first\n");
+ printf("AVB is not initialized, please run 'avb init <id>'\n");
return CMD_RET_FAILURE;
}
@@ -337,13 +340,14 @@
return CMD_RET_USAGE;
}
- if (avb_ops->read_is_device_unlocked(avb_ops, &unlock) ==
- AVB_IO_RESULT_OK) {
+ ret = avb_ops->read_is_device_unlocked(avb_ops, &unlock);
+ if (ret == AVB_IO_RESULT_OK) {
printf("Unlocked = %d\n", unlock);
return CMD_RET_SUCCESS;
}
- printf("Can't determine device lock state.\n");
+ printf("Can't determine device lock state, err = %d\n",
+ ret);
return CMD_RET_FAILURE;
}
@@ -356,9 +360,10 @@
size_t bytes_read;
void *buffer;
char *endp;
+ int ret;
if (!avb_ops) {
- printf("AVB 2.0 is not initialized, run 'avb init' first\n");
+ printf("AVB is not initialized, please run 'avb init <id>'\n");
return CMD_RET_FAILURE;
}
@@ -374,15 +379,16 @@
if (!buffer)
return CMD_RET_FAILURE;
- if (avb_ops->read_persistent_value(avb_ops, name, bytes, buffer,
- &bytes_read) == AVB_IO_RESULT_OK) {
+ ret = avb_ops->read_persistent_value(avb_ops, name, bytes,
+ buffer, &bytes_read);
+ if (ret == AVB_IO_RESULT_OK) {
printf("Read %zu bytes, value = %s\n", bytes_read,
(char *)buffer);
free(buffer);
return CMD_RET_SUCCESS;
}
- printf("Failed to read persistent value\n");
+ printf("Failed to read persistent value, err = %d\n", ret);
free(buffer);
@@ -394,9 +400,10 @@
{
const char *name;
const char *value;
+ int ret;
if (!avb_ops) {
- printf("AVB 2.0 is not initialized, run 'avb init' first\n");
+ printf("AVB is not initialized, please run 'avb init <id>'\n");
return CMD_RET_FAILURE;
}
@@ -406,14 +413,16 @@
name = argv[1];
value = argv[2];
- if (avb_ops->write_persistent_value(avb_ops, name, strlen(value) + 1,
- (const uint8_t *)value) ==
- AVB_IO_RESULT_OK) {
+ ret = avb_ops->write_persistent_value(avb_ops, name,
+ strlen(value) + 1,
+ (const uint8_t *)value);
+ if (ret == AVB_IO_RESULT_OK) {
printf("Wrote %zu bytes\n", strlen(value) + 1);
return CMD_RET_SUCCESS;
}
- printf("Failed to write persistent value\n");
+ printf("Failed to write persistent value `%s` = `%s`, err = %d\n",
+ name, value, ret);
return CMD_RET_FAILURE;
}
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 48ba8db..cff9117 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018, Linaro Limited
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <avb_verify.h>
@@ -120,6 +119,55 @@
0xd8, 0x7e,
};
+const char *str_avb_io_error(AvbIOResult res)
+{
+ switch (res) {
+ case AVB_IO_RESULT_OK:
+ return "Requested operation was successful";
+ case AVB_IO_RESULT_ERROR_IO:
+ return "Underlying hardware encountered an I/O error";
+ case AVB_IO_RESULT_ERROR_OOM:
+ return "Unable to allocate memory";
+ case AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION:
+ return "Requested partition does not exist";
+ case AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION:
+ return "Bytes requested is outside the range of partition";
+ case AVB_IO_RESULT_ERROR_NO_SUCH_VALUE:
+ return "Named persistent value does not exist";
+ case AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE:
+ return "Named persistent value size is not supported";
+ case AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE:
+ return "Buffer is too small for the requested operation";
+ default:
+ return "Unknown AVB error";
+ }
+}
+
+const char *str_avb_slot_error(AvbSlotVerifyResult res)
+{
+ switch (res) {
+ case AVB_SLOT_VERIFY_RESULT_OK:
+ return "Verification passed successfully";
+ case AVB_SLOT_VERIFY_RESULT_ERROR_OOM:
+ return "Allocation of memory failed";
+ case AVB_SLOT_VERIFY_RESULT_ERROR_IO:
+ return "I/O error occurred while trying to load data";
+ case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION:
+ return "Digest didn't match or signature checks failed";
+ case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX:
+ return "Rollback index is less than its stored value";
+ case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED:
+ return "Public keys are not accepted";
+ case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA:
+ return "Metadata is invalid or inconsistent";
+ case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION:
+ return "Metadata requires a newer version of libavb";
+ case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT:
+ return "Invalid arguments are used";
+ default:
+ return "Unknown AVB slot verification error";
+ }
+}
/**
* ============================================================================
* Boot states support (GREEN, YELLOW, ORANGE, RED) and dm_verity
@@ -280,9 +328,9 @@
* Reading fails on unaligned buffers, so we have to
* use aligned temporary buffer and then copy to destination
*/
-
if (unaligned) {
- printf("Handling unaligned read buffer..\n");
+ debug("%s: handling unaligned read buffer, addr = 0x%p\n",
+ __func__, buffer);
tmp_buf = get_sector_buf();
buf_size = get_sector_buf_size();
if (sectors > buf_size / part->info.blksz)
@@ -321,7 +369,8 @@
if (unaligned) {
tmp_buf = get_sector_buf();
buf_size = get_sector_buf_size();
- printf("Handling unaligned wrire buffer..\n");
+ debug("%s: handling unaligned read buffer, addr = 0x%p\n",
+ __func__, buffer);
if (sectors > buf_size / part->info.blksz)
sectors = buf_size / part->info.blksz;
@@ -349,28 +398,35 @@
dev_num = get_boot_device(ops);
part->mmc = find_mmc_device(dev_num);
if (!part->mmc) {
- printf("No MMC device at slot %x\n", dev_num);
+ printf("%s: no MMC device at slot %x\n", __func__, dev_num);
goto err;
}
- if (mmc_init(part->mmc)) {
- printf("MMC initialization failed\n");
+ ret = mmc_init(part->mmc);
+ if (ret) {
+ printf("%s: MMC initialization failed, err = %d\n",
+ __func__, ret);
goto err;
}
- ret = mmc_switch_part(part->mmc, part_num);
- if (ret)
- goto err;
+ if (IS_MMC(part->mmc)) {
+ ret = mmc_switch_part(part->mmc, part_num);
+ if (ret) {
+ printf("%s: MMC part switch failed, err = %d\n",
+ __func__, ret);
+ goto err;
+ }
+ }
mmc_blk = mmc_get_blk_desc(part->mmc);
if (!mmc_blk) {
- printf("Error - failed to obtain block descriptor\n");
+ printf("%s: failed to obtain block descriptor\n", __func__);
goto err;
}
ret = part_get_info_by_name(mmc_blk, partition, &part->info);
if (ret < 0) {
- printf("Can't find partition '%s'\n", partition);
+ printf("%s: can't find partition '%s'\n", __func__, partition);
goto err;
}
@@ -683,7 +739,7 @@
{
#ifndef CONFIG_OPTEE_TA_AVB
/* For now we always return 0 as the stored rollback index. */
- printf("%s not supported yet\n", __func__);
+ debug("%s: rollback protection is not implemented\n", __func__);
if (out_rollback_index)
*out_rollback_index = 0;
@@ -729,7 +785,7 @@
{
#ifndef CONFIG_OPTEE_TA_AVB
/* For now this is a no-op. */
- printf("%s not supported yet\n", __func__);
+ debug("%s: rollback protection is not implemented\n", __func__);
return AVB_IO_RESULT_OK;
#else
@@ -765,8 +821,7 @@
{
#ifndef CONFIG_OPTEE_TA_AVB
/* For now we always return that the device is unlocked. */
-
- printf("%s not supported yet\n", __func__);
+ debug("%s: device locking is not implemented\n", __func__);
*out_is_unlocked = true;
diff --git a/common/usb_hub.c b/common/usb_hub.c
index 3fb7e14..2e054eb 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -174,8 +174,10 @@
debug("enabling power on all ports\n");
for (i = 0; i < dev->maxchild; i++) {
- usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_RESET);
- debug("Reset : port %d returns %lX\n", i + 1, dev->status);
+ if (usb_hub_is_superspeed(dev)) {
+ usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_RESET);
+ debug("Reset : port %d returns %lX\n", i + 1, dev->status);
+ }
usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
debug("PowerOn : port %d returns %lX\n", i + 1, dev->status);
}
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index 31f38bd..35707a6 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -68,6 +68,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
+CONFIG_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -106,3 +107,4 @@
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 3808358..e5fcd8c 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -24,6 +24,7 @@
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig
index 0be2004..1f43891 100644
--- a/configs/am62x_beagleplay_a53_defconfig
+++ b/configs/am62x_beagleplay_a53_defconfig
@@ -33,7 +33,8 @@
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load"
+CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb;run set_led_state_fail_load"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80c80000
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index 457931f..a39b82d 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -32,6 +32,7 @@
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80c80000
diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
index 59e9b3a..f328af8 100644
--- a/configs/blanche_defconfig
+++ b/configs/blanche_defconfig
@@ -44,6 +44,7 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
@@ -82,3 +83,4 @@
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig
new file mode 100644
index 0000000..bb41635
--- /dev/null
+++ b/configs/e850-96_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TEXT_BASE=0xf8800000
+CONFIG_SYS_MALLOC_LEN=0x81f000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ARCH_EXYNOS9=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000
+CONFIG_DEFAULT_DEVICE_TREE="exynos850-e850-96"
+CONFIG_SYS_LOAD_ADDR=0x80000000
+# CONFIG_AUTOBOOT is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_NET is not set
+CONFIG_CLK_EXYNOS850=y
+# CONFIG_MMC is not set
+CONFIG_SOC_SAMSUNG=y
+CONFIG_EXYNOS_PMU=y
+CONFIG_EXYNOS_USI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_SYSCON=y
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 4220b93..92bb591 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -68,6 +68,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
+CONFIG_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -104,3 +105,4 @@
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/imx6dl_sielaff_defconfig b/configs/imx6dl_sielaff_defconfig
new file mode 100644
index 0000000..41574a4
--- /dev/null
+++ b/configs/imx6dl_sielaff_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="imx6dl-sielaff"
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xF0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6S=y
+CONFIG_TARGET_MX6S_SIELAFF=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sielaff"
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_LTO=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT_PRINT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_SPI_BOOT=y
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8A
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand0:-@0x0(rootfs)"
+CONFIG_CMD_UBI=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_CONS_INDEX=2
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig
index 0db3ff8..a416ebc 100644
--- a/configs/imx8mm-phygate-tauri-l_defconfig
+++ b/configs/imx8mm-phygate-tauri-l_defconfig
@@ -112,4 +112,5 @@
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig
index 14922f2..036f44d 100644
--- a/configs/imx93_var_som_defconfig
+++ b/configs/imx93_var_som_defconfig
@@ -69,6 +69,7 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_READ=y
+CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_SNTP=y
@@ -95,6 +96,12 @@
CONFIG_CLK_IMX93=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_GPIO_HOG=y
CONFIG_IMX_RGPIO2P=y
CONFIG_DM_PCA953X=y
@@ -131,6 +138,14 @@
CONFIG_FSL_LPUART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_PORT_AUTO=y
CONFIG_ULP_WATCHDOG=y
CONFIG_WDT=y
CONFIG_LZO=y
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index 8b5ce4e..086fc47 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -10,21 +10,22 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20280000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000
CONFIG_ENV_OFFSET=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
-CONFIG_SPL_TEXT_BASE=0x20209000
+CONFIG_SPL_TEXT_BASE=0x20002000
CONFIG_TARGET_IMXRT1050_EVK=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SIZE_LIMIT=0x20000
CONFIG_SPL=y
-CONFIG_SYS_LOAD_ADDR=0x20209000
+CONFIG_SYS_LOAD_ADDR=0x20002000
CONFIG_HAVE_SYS_UBOOT_START=y
CONFIG_SYS_UBOOT_START=0x800023FD
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
+CONFIG_SPI_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
@@ -36,6 +37,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
+CONFIG_SPL_NOR_SUPPORT=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig
new file mode 100644
index 0000000..4b252cf
--- /dev/null
+++ b/configs/imxrt1050-evk_fspi_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
+# CONFIG_SPL_SYS_DCACHE_OFF is not set
+CONFIG_ARCH_IMXRT=y
+CONFIG_TEXT_BASE=0x80002000
+CONFIG_SYS_MALLOC_LEN=0x40000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000
+CONFIG_ENV_OFFSET=0x80000
+CONFIG_IMX_CONFIG="board/freescale/imxrt1050-evk/imximage-nor.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
+CONFIG_SPL_TEXT_BASE=0x20002000
+CONFIG_TARGET_IMXRT1050_EVK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x20002000
+CONFIG_HAVE_SYS_UBOOT_START=y
+CONFIG_SYS_UBOOT_START=0x800023FD
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SD_BOOT=y
+CONFIG_SPI_BOOT=y
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_NO_BSS_LIMIT=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
+CONFIG_SPL_NOR_SUPPORT=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_MII is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_TFTP_BLOCKSIZE=512
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_OF_TRANSLATE is not set
+CONFIG_SPL_CLK_IMXRT1050=y
+CONFIG_CLK_IMXRT1050=y
+# CONFIG_SPL_DM_GPIO is not set
+CONFIG_MXC_GPIO=y
+# CONFIG_INPUT is not set
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMXRT=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_IMXRT_SDRAM=y
+CONFIG_FSL_LPUART=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_IMX_GPT_TIMER=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_HEXDUMP=y
+CONFIG_FSPI_CONF_HEADER=y
+CONFIG_FSPI_CONF_FILE="fspi_header.bin"
+CONFIG_READ_CLK_SOURCE=0x03
+CONFIG_DEVICE_TYPE=0x00
+CONFIG_FLASH_PAD_TYPE=0x08
+CONFIG_SERIAL_CLK_FREQUENCY=0x07
+CONFIG_FSPI_COL_ADDR_W=0x03
+CONFIG_FSPI_CONTROLLER_MISC=0x00000059
+CONFIG_FSPI_FLASH_A1_SIZE=0x04000000
+CONFIG_LUT_SEQUENCE="0xa0, 0x87, 0x18, 0x8b, 0x10, 0x8f, 0x06, 0xb3, 0x04, 0xa7"
diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig
index 4b019fa..3f06138 100644
--- a/configs/j721e_beagleboneai64_a72_defconfig
+++ b/configs/j721e_beagleboneai64_a72_defconfig
@@ -34,7 +34,8 @@
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load"
+CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb;run set_led_state_fail_load"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig
index b41c266..ee62fe3 100644
--- a/configs/khadas-vim3_android_ab_defconfig
+++ b/configs/khadas-vim3_android_ab_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_CONFIG_NAME="khadas-vim3_android"
CONFIG_ARCH_MESON=y
CONFIG_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x08000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig
index 88197f5..cecbe50 100644
--- a/configs/khadas-vim3_android_defconfig
+++ b/configs/khadas-vim3_android_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_CONFIG_NAME="khadas-vim3_android"
CONFIG_ARCH_MESON=y
CONFIG_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x08000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig
index 3381d2e..ec4e0dc 100644
--- a/configs/khadas-vim3l_android_ab_defconfig
+++ b/configs/khadas-vim3l_android_ab_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_CONFIG_NAME="khadas-vim3l_android"
CONFIG_ARCH_MESON=y
CONFIG_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x08000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig
index 3fa587e..206f8de 100644
--- a/configs/khadas-vim3l_android_defconfig
+++ b/configs/khadas-vim3l_android_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_CONFIG_NAME="khadas-vim3l_android"
CONFIG_ARCH_MESON=y
CONFIG_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x08000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index d39533c..8d9c3b9 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -68,6 +68,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
+CONFIG_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -104,3 +105,4 @@
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index da2ba58..d00314c 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -68,6 +68,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
+CONFIG_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -106,3 +107,4 @@
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig
index bf1052d..5688c7a 100644
--- a/configs/msc_sm2s_imx8mp_defconfig
+++ b/configs/msc_sm2s_imx8mp_defconfig
@@ -5,7 +5,8 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x200000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s"
CONFIG_SPL_TEXT_BASE=0x920000
@@ -16,6 +17,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x960000
CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x204000
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SYS_BOOT_GET_CMDLINE=y
@@ -26,7 +28,7 @@
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb"
+CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s-ep1.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_SPL_MAX_SIZE=0x26000
@@ -62,6 +64,8 @@
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
@@ -72,6 +76,7 @@
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
@@ -97,6 +102,7 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index d4de8df..e2d3bc0 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -60,6 +60,8 @@
CONFIG_POWER_I2C=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
@@ -67,3 +69,4 @@
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index ac4170d..e1884df 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -102,6 +102,8 @@
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
@@ -123,4 +125,5 @@
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
+CONFIG_IMX_WATCHDOG=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index bcc38d5..3a81ea7 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -128,4 +128,5 @@
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 0f37286..c955542 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -138,6 +138,7 @@
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 0a805de..a343c8e 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -68,6 +68,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
+CONFIG_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -104,3 +105,4 @@
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 7c6b5b5..5f08ae0 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -68,6 +68,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
+CONFIG_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -106,3 +107,4 @@
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index 8fad272..0375630 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -68,6 +68,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)"
+CONFIG_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -105,3 +106,4 @@
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index 72a123d..7a11035 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -16,6 +16,7 @@
CONFIG_VERSAL_NO_DDR=y
# CONFIG_PSCI_RESET is not set
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_LTO=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_AUTOBOOT is not set
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index d9fbac9..58945a1 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -14,6 +14,7 @@
CONFIG_VERSAL_NO_DDR=y
# CONFIG_PSCI_RESET is not set
CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_LTO=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_AUTOBOOT is not set
diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig
index 5f42243..d78c9f8 100644
--- a/configs/xilinx_versal_net_mini_ospi_defconfig
+++ b/configs/xilinx_versal_net_mini_ospi_defconfig
@@ -15,6 +15,7 @@
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
CONFIG_SYS_LOAD_ADDR=0xBBF80000
+CONFIG_LTO=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_AUTOBOOT is not set
diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig
index 4fa83fa..b0567f8 100644
--- a/configs/xilinx_versal_net_mini_qspi_defconfig
+++ b/configs/xilinx_versal_net_mini_qspi_defconfig
@@ -13,6 +13,7 @@
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
CONFIG_SYS_LOAD_ADDR=0xBBF80000
+CONFIG_LTO=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
# CONFIG_AUTOBOOT is not set
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 371d14e..0f1d990 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -146,3 +146,4 @@
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_BLK=y
CONFIG_TPM=y
+CONFIG_EFI_HTTP_BOOT=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 5f76a30..3c55dd8 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -153,3 +153,4 @@
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_BLK=y
CONFIG_TPM=y
+CONFIG_EFI_HTTP_BOOT=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index 0dc6c5b..28b28f6 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -224,3 +224,4 @@
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_HTTP_BOOT=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 2742e38..1fcae45 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -242,3 +242,4 @@
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_HTTP_BOOT=y
diff --git a/doc/android/avb2.rst b/doc/android/avb2.rst
index a072119..4aca7a5 100644
--- a/doc/android/avb2.rst
+++ b/doc/android/avb2.rst
@@ -38,16 +38,22 @@
Provides CLI interface to invoke AVB 2.0 verification + misc. commands for
different testing purposes::
- avb init <dev> - initialize avb 2.0 for <dev>
- avb verify - run verification process using hash data from vbmeta structure
+ avb init <dev> - initialize avb 2 for <dev>
avb read_rb <num> - read rollback index at location <num>
avb write_rb <num> <rb> - write rollback index <rb> to <num>
avb is_unlocked - returns unlock status of the device
- avb get_uuid <partname> - read and print uuid of partition <partname>
+ avb get_uuid <partname> - read and print uuid of partition <part>
avb read_part <partname> <offset> <num> <addr> - read <num> bytes from
- partition <partname> to buffer <addr>
+ partition <partname> to buffer <addr>
+ avb read_part_hex <partname> <offset> <num> - read <num> bytes from
+ partition <partname> and print to stdout
avb write_part <partname> <offset> <num> <addr> - write <num> bytes to
- <partname> by <offset> using data from <addr>
+ <partname> by <offset> using data from <addr>
+ avb read_pvalue <name> <bytes> - read a persistent value <name>
+ avb write_pvalue <name> <value> - write a persistent value <name>
+ avb verify [slot_suffix] - run verification process using hash data
+ from vbmeta structure
+ [slot_suffix] - _a, _b, etc (if vbmeta partition is slotted)
Partitions tampering (example)
------------------------------
diff --git a/doc/board/index.rst b/doc/board/index.rst
index d0f9f35..62357c9 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -42,6 +42,7 @@
renesas/index
rockchip/index
samsung/index
+ sielaff/index
siemens/index
sifive/index
sipeed/index
diff --git a/doc/board/nxp/imxrt1050-evk.rst b/doc/board/nxp/imxrt1050-evk.rst
index c1fb48f..e0cafe1 100644
--- a/doc/board/nxp/imxrt1050-evk.rst
+++ b/doc/board/nxp/imxrt1050-evk.rst
@@ -39,3 +39,33 @@
The USB console connector is the one close the ethernet connector
- Insert the micro SD card in the board, power it up and U-Boot messages should come up.
+
+
+How to use U-Boot with SPI flash on NXP i.MXRT1050 EVK
+------------------------------------------------------
+
+- Build U-Boot for i.MXRT1050 EVK:
+
+.. code-block:: bash
+
+ $ make mrproper
+ $ make imxrt1050-evk_fspi_defconfig
+ $ make
+
+This will generate SPL, uboot.img, fspi_header.bin, and the final image (flash.bin).
+
+To boot from SPI flash on other boards, you may need to change the flash header config,
+which is specific to your flash chip, in Kconfig.
+The flash config is 4K in size and is documented on page 217 of the imxrt1050 RM.
+The default flash chip on the i.MXRT1050 EVK is the S26KS512SDPBHI02 HYPERFLASH.
+
+- Jumper settings::
+
+ SW7: 0 1 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+
+- Use either JTAG or SWD to write `flash.bin` to the NOR. I used Mcuexpresso IDE's GUI flash tool.
diff --git a/doc/board/samsung/e850-96.rst b/doc/board/samsung/e850-96.rst
new file mode 100644
index 0000000..0cb9547
--- /dev/null
+++ b/doc/board/samsung/e850-96.rst
@@ -0,0 +1,87 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Sam Protsenko <semen.protsenko@linaro.org>
+
+WinLink E850-96 board
+=====================
+
+Overview
+--------
+
+WinLink's E850-96 board [1]_ is based on Samsung Exynos850 SoC and follows
+96Boards Consumer Edition specification [2]_. That makes it possible to use
+96Boards mezzanine boards [3]_ along with it. It's an open-hardware board and
+the hardware design files [4]_ were published, along with the supported
+software [5]_ and related documentation.
+
+U-Boot can be used on E850-96 instead of the original Samsung LittleKernel based
+bootloader [6]_. Because FWBL1 [7]_ doesn't verify bootloader's signature, there
+is no need to sign a U-Boot binary. That means U-Boot binary can be flashed into
+``bootloader`` partition (instead of LittleKernel bootloader) and it will just
+work.
+
+Because BL2 bootloader already sets up DRAM and runs the final bootloader
+(U-Boot) from DRAM, there is no need in U-Boot SPL. It's enough to have only
+U-Boot proper (``u-boot.bin``).
+
+Boot Flow
+---------
+
+The boot path for Exynos850 is shown on the figure below.
+
+.. image:: img/exynos850-boot-architecture.svg
+ :alt: Exynos850 SoC boot flow
+
+Legend:
+
+* ``BL0``: Boot ROM code
+* ``BL1``: Software part of Boot ROM
+* ``EPBL``: Exynos Primary Boot Loader
+* ``BL2``: Initializes CMU and DRAM and runs the final bootloader
+* ``Bootloader``: Final bootloader (e.g. U-Boot); also called BL33 in terms of
+ ARM boot flow
+* ``EL3_MON``: EL3 monitor (trusted firmware, handles SMC calls); also called
+ BL31 in terms of ARM boot flow
+* ``LDFW``: Loadable Firmware
+
+Build Procedure
+---------------
+
+.. warning::
+ At the moment both eMMC and USB features are not enabled in U-Boot. Flashing
+ U-Boot binary **WILL** effectively brick your board. The ``dltool`` [8]_ can
+ be used then to perform USB boot and flash LittleKernel bootloader binary [7]_
+ to unbrick and revive the board. Flashing U-Boot binary might be helpful for
+ developers or anybody who want to check current state of U-Boot enablement on
+ E850-96 (which is mostly serial console and related blocks).
+
+Build U-Boot binary from source code (using AArch64 baremetal GCC toolchain):
+
+.. prompt:: bash $
+
+ export PATH=<toolchain path>/bin:$PATH
+ export CROSS_COMPILE=<toolchain prefix>
+ make e850-96_defconfig
+ make
+
+Boot E850-96 board into fastboot mode as described in board software doc [9]_,
+and flash U-Boot binary into ``bootloader`` eMMC partition:
+
+.. prompt:: bash $
+
+ fastboot flash bootloader u-boot.bin
+ fastboot reboot
+
+U-Boot will boot up to the shell.
+
+References
+----------
+
+.. [1] https://www.96boards.org/product/e850-96b/
+.. [2] https://www.96boards.org/products/ce/
+.. [3] https://www.96boards.org/products/mezzanine/
+.. [4] https://www.96boards.org/documentation/consumer/e850-96b/hardware-docs/
+.. [5] https://gitlab.com/Linaro/96boards/e850-96/
+.. [6] https://gitlab.com/Linaro/96boards/e850-96/lk
+.. [7] https://gitlab.com/Linaro/96boards/e850-96/images
+.. [8] https://gitlab.com/Linaro/96boards/e850-96/tools/dltool
+.. [9] https://gitlab.com/Linaro/96boards/e850-96/doc
diff --git a/doc/board/samsung/img/exynos850-boot-architecture.svg b/doc/board/samsung/img/exynos850-boot-architecture.svg
new file mode 100644
index 0000000..c6e8504
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diff --git a/doc/board/samsung/index.rst b/doc/board/samsung/index.rst
index 971805e..a1c9636 100644
--- a/doc/board/samsung/index.rst
+++ b/doc/board/samsung/index.rst
@@ -7,3 +7,4 @@
:maxdepth: 2
axy17lte
+ e850-96
diff --git a/doc/board/sielaff/imx6dl-sielaff.rst b/doc/board/sielaff/imx6dl-sielaff.rst
new file mode 100644
index 0000000..699079b
--- /dev/null
+++ b/doc/board/sielaff/imx6dl-sielaff.rst
@@ -0,0 +1,29 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sielaff i.MX6 Solo Board
+========================
+
+The Sielaff i.MX6 Solo board is a control and Human Machine Interface (HMI)
+board for vending machines.
+
+Quick Start
+-----------
+
+Build U-Boot
+^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ make imx6dl_sielaff_defconfig
+ make CROSS_COMPILE=arm-linux-gnueabi-
+
+Copy the flash.bin file to an SD card at an offset of 1 KiB:
+
+.. code-block:: bash
+
+ dd if=flash.bin of=/dev/sd[x] bs=1K seek=1
+
+Boot
+^^^^
+
+Put the SD card in the slot on the board and apply power.
diff --git a/doc/board/sielaff/index.rst b/doc/board/sielaff/index.rst
new file mode 100644
index 0000000..a837648
--- /dev/null
+++ b/doc/board/sielaff/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sielaff
+=======
+
+.. toctree::
+ :maxdepth: 2
+
+ imx6dl-sielaff
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 4f18623..1b2e1a2 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -66,9 +66,9 @@
* U-Boot v2024.01-rc1 was released on Mon 29 January 2024.
-.. * U-Boot v2024.01-rc2 was released on Mon 12 February 2024.
+* U-Boot v2024.01-rc2 was released on Tue 13 February 2024.
-.. * U-Boot v2024.01-rc3 was released on Mon 26 February 2024.
+* U-Boot v2024.01-rc3 was released on Mon 26 February 2024.
.. * U-Boot v2024.01-rc4 was released on Mon 11 March 2024.
diff --git a/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
new file mode 100644
index 0000000..a0906ef
--- /dev/null
+++ b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
@@ -0,0 +1,307 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos850 SoC clock controller
+
+maintainers:
+ - Sam Protsenko <semen.protsenko@linaro.org>
+
+description: |
+ Exynos850 clock controller is comprised of several CMU units, generating
+ clocks for different domains. Those CMU units are modeled as separate device
+ tree nodes, and might depend on each other. Root clocks in that clock tree are
+ two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
+ clocks must be defined as fixed-rate clocks in dts.
+
+ CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+ dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All clocks available for usage
+ in clock consumer nodes are defined as preprocessor macros in
+ 'dt-bindings/clock/exynos850.h' header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos850-cmu-top
+ - samsung,exynos850-cmu-apm
+ - samsung,exynos850-cmu-aud
+ - samsung,exynos850-cmu-cmgp
+ - samsung,exynos850-cmu-core
+ - samsung,exynos850-cmu-dpu
+ - samsung,exynos850-cmu-g3d
+ - samsung,exynos850-cmu-hsi
+ - samsung,exynos850-cmu-is
+ - samsung,exynos850-cmu-mfcmscl
+ - samsung,exynos850-cmu-peri
+
+ clocks:
+ minItems: 1
+ maxItems: 5
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-top
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+
+ clock-names:
+ items:
+ - const: oscclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-apm
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_APM bus clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_clkcmu_apm_bus
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-aud
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: AUD clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_aud
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-cmgp
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_CMGP bus clock (from CMU_APM)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: gout_clkcmu_cmgp_bus
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-core
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_CORE bus clock (from CMU_TOP)
+ - description: CCI clock (from CMU_TOP)
+ - description: eMMC clock (from CMU_TOP)
+ - description: SSS clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_core_bus
+ - const: dout_core_cci
+ - const: dout_core_mmc_embd
+ - const: dout_core_sss
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-dpu
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: DPU clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_dpu
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-g3d
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: G3D clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_g3d_switch
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-hsi
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: External RTC clock (32768 Hz)
+ - description: CMU_HSI bus clock (from CMU_TOP)
+ - description: SD card clock (from CMU_TOP)
+ - description: USB 2.0 DRD clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: rtcclk
+ - const: dout_hsi_bus
+ - const: dout_hsi_mmc_card
+ - const: dout_hsi_usb20drd
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-is
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_IS bus clock (from CMU_TOP)
+ - description: Image Texture Processing core clock (from CMU_TOP)
+ - description: Visual Recognition Accelerator clock (from CMU_TOP)
+ - description: Geometric Distortion Correction clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_is_bus
+ - const: dout_is_itp
+ - const: dout_is_vra
+ - const: dout_is_gdc
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-mfcmscl
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: Multi-Format Codec clock (from CMU_TOP)
+ - description: Memory to Memory Scaler clock (from CMU_TOP)
+ - description: Multi-Channel Scaler clock (from CMU_TOP)
+ - description: JPEG codec clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_mfcmscl_mfc
+ - const: dout_mfcmscl_m2m
+ - const: dout_mfcmscl_mcsc
+ - const: dout_mfcmscl_jpeg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-peri
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_PERI bus clock (from CMU_TOP)
+ - description: UART clock (from CMU_TOP)
+ - description: Parent clock for HSI2C and SPI (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_peri_bus
+ - const: dout_peri_uart
+ - const: dout_peri_ip
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_PERI
+ - |
+ #include <dt-bindings/clock/exynos850.h>
+
+ cmu_peri: clock-controller@10030000 {
+ compatible = "samsung,exynos850-cmu-peri";
+ reg = <0x10030000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
+ <&cmu_top CLK_DOUT_PERI_UART>,
+ <&cmu_top CLK_DOUT_PERI_IP>;
+ clock-names = "oscclk", "dout_peri_bus",
+ "dout_peri_uart", "dout_peri_ip";
+ };
+
+...
diff --git a/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml b/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
new file mode 100644
index 0000000..c3e95c3
--- /dev/null
+++ b/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC series Power Management Unit (PMU)
+
+maintainers:
+ - Sam Protsenko <semen.protsenko@linaro.org>
+
+description: |+
+ PMU block controls the power and operation states of Exynos SoC. It contains
+ registers for changing the state of next features::
+
+ - Local power control. Exynos SoCs have various power domains, and it's
+ possible to turn them on and off independently, using corresponding
+ registers in PMU block
+ - System-level power control. That allows putting the system into power-down
+ modes (sleep) by turning off the power for most of the domains
+ - Miscellaneous PMU related features
+
+# Custom select to avoid matching all nodes with 'syscon'
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos850-pmu
+ required:
+ - compatible
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - samsung,exynos850-pmu
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ samsung,uart-debug-1:
+ type: boolean
+ description:
+ Enable this property if AP UART lines (Application Processor UART) must be
+ connected to UART_DEBUG_1 path in PMU block. That's usually needed when
+ the serial console is provided by uart1_pins. If this property is not
+ specified, the default behavior will be used (AP UART lines connected to
+ UART_DEBUG_0 path, which usually means uart0_pins are used for the serial
+ console).
+
+ syscon-poweroff:
+ $ref: /schemas/power/reset/syscon-poweroff.yaml#
+ type: object
+ description:
+ Node for power off method
+
+ syscon-reboot:
+ $ref: /schemas/power/reset/syscon-reboot.yaml#
+ type: object
+ description:
+ Node for reboot method
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ pmu_system_controller: system-controller@11860000 {
+ compatible = "samsung,exynos850-pmu", "syscon";
+ reg = <0x11860000 0x10000>;
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmu_system_controller>;
+ offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
+ mask = <0x2>; /* SWRESET_SYSTEM */
+ value = <0x2>; /* reset value */
+ };
+ };
diff --git a/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
new file mode 100644
index 0000000..8e6423f
--- /dev/null
+++ b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung's Exynos USI (Universal Serial Interface)
+
+maintainers:
+ - Sam Protsenko <semen.protsenko@linaro.org>
+
+description: |
+ USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
+ USI shares almost all internal circuits within each protocol, so only one
+ protocol can be chosen at a time. USI is modeled as a node with zero or more
+ child nodes, each representing a serial sub-node device. The mode setting
+ selects which particular function will be used.
+
+properties:
+ $nodename:
+ pattern: "^usi@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - samsung,exynos850-usi
+
+ reg: true
+
+ clocks: true
+
+ clock-names: true
+
+ ranges: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ samsung,sysreg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Register syscon node
+ - description: offset of SW_CONF register for this USI controller
+ description:
+ Should be phandle/offset pair. The phandle to System Register syscon node
+ (for the same domain where this USI controller resides) and the offset
+ of SW_CONF register for this USI controller.
+
+ samsung,mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Selects USI function (which serial protocol to use). Refer to
+ <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
+
+ samsung,clkreq-on:
+ type: boolean
+ description:
+ Enable this property if underlying protocol requires the clock to be
+ continuously provided without automatic gating. As suggested by SoC
+ manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
+ multi-master mode. Usually this property is needed if USI mode is set
+ to "UART".
+
+ This property is optional.
+
+patternProperties:
+ "^i2c@[0-9a-f]+$":
+ $ref: /schemas/i2c/i2c-exynos5.yaml
+ description: Child node describing underlying I2C
+
+ "^serial@[0-9a-f]+$":
+ $ref: /schemas/serial/samsung_uart.yaml
+ description: Child node describing underlying UART/serial
+
+ "^spi@[0-9a-f]+$":
+ $ref: /schemas/spi/samsung,spi.yaml
+ description: Child node describing underlying SPI
+
+required:
+ - compatible
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+ - samsung,sysreg
+ - samsung,mode
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos850-usi
+
+then:
+ properties:
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Bus (APB) clock
+ - description: Operating clock for UART/SPI/I2C protocol
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: ipclk
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+
+else:
+ properties:
+ reg: false
+ clocks: false
+ clock-names: false
+ samsung,clkreq-on: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/soc/samsung,exynos-usi.h>
+
+ usi0: usi@138200c0 {
+ compatible = "samsung,exynos850-usi";
+ reg = <0x138200c0 0x20>;
+ samsung,sysreg = <&sysreg_peri 0x1010>;
+ samsung,mode = <USI_V2_UART>;
+ samsung,clkreq-on; /* needed for UART mode */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&cmu_peri 32>, <&cmu_peri 31>;
+ clock-names = "pclk", "ipclk";
+
+ serial_0: serial@13820000 {
+ compatible = "samsung,exynos850-uart";
+ reg = <0x13820000 0xc0>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_peri 32>, <&cmu_peri 31>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ hsi2c_0: i2c@13820000 {
+ compatible = "samsung,exynosautov9-hsi2c";
+ reg = <0x13820000 0xc0>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_peri 31>, <&cmu_peri 32>;
+ clock-names = "hsi2c", "hsi2c_pclk";
+ status = "disabled";
+ };
+ };
diff --git a/drivers/button/button-qcom-pmic.c b/drivers/button/button-qcom-pmic.c
index 34a976d..bad445e 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -86,7 +86,7 @@
}
ret = pmic_reg_read(priv->pmic, priv->base + REG_SUBTYPE);
- if ((ret & 0x7) == 0) {
+ if (ret < 0 || (ret & 0x7) == 0) {
printf("%s: unexpected PMCI function subtype %d\n", dev->name, ret);
return -ENXIO;
}
@@ -133,7 +133,7 @@
} else if (NODE_IS_RESIN(node)) {
uc_plat->label = "vol_down";
} else {
- printf("Unknown button node '%s' should be 'pwrkey' or 'resin'\n",
+ debug("Unknown button node '%s' should be 'pwrkey' or 'resin'\n",
ofnode_get_name(node));
device_unbind(dev);
}
diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig
index eb0efa9..85ce9d6 100644
--- a/drivers/clk/exynos/Kconfig
+++ b/drivers/clk/exynos/Kconfig
@@ -15,4 +15,11 @@
This enables common clock driver support for platforms based
on Samsung Exynos7420 SoC.
+config CLK_EXYNOS850
+ bool "Clock driver for Samsung's Exynos850 SoC"
+ select CLK_CCF
+ help
+ This enables common clock driver support for platforms based
+ on Samsung Exynos850 SoC.
+
endmenu
diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
index c9f29c8..734100e 100644
--- a/drivers/clk/exynos/Makefile
+++ b/drivers/clk/exynos/Makefile
@@ -1,7 +1,12 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2016 Samsung Electronics
-# Thomas Abraham <thomas.ab@samsung.com>
+# Copyright (C) 2023 Linaro Ltd.
+#
+# Authors:
+# Thomas Abraham <thomas.ab@samsung.com>
+# Sam Protsenko <semen.protsenko@linaro.org>
-obj-y += clk-pll.o
-obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o
+obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
+obj-$(CONFIG_CLK_EXYNOS850) += clk-exynos850.o
diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
index 7d869eb..9caa932 100644
--- a/drivers/clk/exynos/clk-exynos7420.c
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -10,8 +10,15 @@
#include <errno.h>
#include <clk-uclass.h>
#include <asm/io.h>
+#include <div64.h>
#include <dt-bindings/clock/exynos7420-clk.h>
-#include "clk-pll.h"
+
+#define PLL145X_MDIV_SHIFT 16
+#define PLL145X_MDIV_MASK 0x3ff
+#define PLL145X_PDIV_SHIFT 8
+#define PLL145X_PDIV_MASK 0x3f
+#define PLL145X_SDIV_SHIFT 0
+#define PLL145X_SDIV_MASK 0x7
#define DIVIDER(reg, shift, mask) \
(((readl(reg) >> shift) & mask) + 1)
@@ -64,6 +71,22 @@
unsigned long sclk_uart2;
};
+static unsigned long pll145x_get_rate(unsigned int *con1,
+ unsigned long fin_freq)
+{
+ unsigned long pll_con1 = readl(con1);
+ unsigned long mdiv, sdiv, pdiv;
+ u64 fvco = fin_freq;
+
+ mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
+ pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
+ sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+ return (unsigned long)fvco;
+}
+
static ulong exynos7420_topc_get_rate(struct clk *clk)
{
struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev);
diff --git a/drivers/clk/exynos/clk-exynos850.c b/drivers/clk/exynos/clk-exynos850.c
new file mode 100644
index 0000000..cf94a3e
--- /dev/null
+++ b/drivers/clk/exynos/clk-exynos850.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung Exynos850 clock driver.
+ * Copyright (c) 2023 Linaro Ltd.
+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
+ */
+
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/exynos850.h>
+#include "clk.h"
+
+/* ---- CMU_TOP ------------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_TOP (0x120e0000) */
+#define PLL_CON0_PLL_MMC 0x0100
+#define PLL_CON3_PLL_MMC 0x010c
+#define PLL_CON0_PLL_SHARED0 0x0140
+#define PLL_CON3_PLL_SHARED0 0x014c
+#define PLL_CON0_PLL_SHARED1 0x0180
+#define PLL_CON3_PLL_SHARED1 0x018c
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
+#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
+#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
+#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
+#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c
+#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890
+#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894
+#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
+#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
+#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
+
+static const struct samsung_pll_clock top_pure_pll_clks[] = {
+ PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk",
+ PLL_CON3_PLL_SHARED0),
+ PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk",
+ PLL_CON3_PLL_SHARED1),
+ PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk",
+ PLL_CON3_PLL_MMC),
+};
+
+/* List of parent clocks for Muxes in CMU_TOP */
+PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" };
+PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" };
+PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
+PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
+PNAME(mout_peri_uart_p) = { "clock-oscclk", "dout_shared0_div4",
+ "dout_shared1_div4", "clock-oscclk" };
+PNAME(mout_peri_ip_p) = { "clock-oscclk", "dout_shared0_div4",
+ "dout_shared1_div4", "clock-oscclk" };
+
+static const struct samsung_mux_clock top_pure_mux_clks[] = {
+ MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
+ PLL_CON0_PLL_SHARED0, 4, 1),
+ MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
+ PLL_CON0_PLL_SHARED1, 4, 1),
+ MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
+ PLL_CON0_PLL_MMC, 4, 1),
+};
+
+static const struct samsung_mux_clock top_peri_mux_clks[] = {
+ MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
+ MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
+ MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
+};
+
+static const struct samsung_div_clock top_pure_div_clks[] = {
+ DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
+ DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
+ DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
+ CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
+ DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
+ CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
+ DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
+ CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
+ DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
+ CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
+};
+
+static const struct samsung_div_clock top_peri_div_clks[] = {
+ DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
+ CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
+ DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
+ CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
+ DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
+ CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
+};
+
+static const struct samsung_gate_clock top_peri_gate_clks[] = {
+ GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
+ CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart",
+ CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
+ GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip",
+ CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
+};
+
+static const struct samsung_clk_group top_cmu_clks[] = {
+ /* CMU_TOP_PURECLKCOMP */
+ { S_CLK_PLL, top_pure_pll_clks, ARRAY_SIZE(top_pure_pll_clks) },
+ { S_CLK_MUX, top_pure_mux_clks, ARRAY_SIZE(top_pure_mux_clks) },
+ { S_CLK_DIV, top_pure_div_clks, ARRAY_SIZE(top_pure_div_clks) },
+
+ /* CMU_TOP clocks for CMU_PERI */
+ { S_CLK_MUX, top_peri_mux_clks, ARRAY_SIZE(top_peri_mux_clks) },
+ { S_CLK_GATE, top_peri_gate_clks, ARRAY_SIZE(top_peri_gate_clks) },
+ { S_CLK_DIV, top_peri_div_clks, ARRAY_SIZE(top_peri_div_clks) },
+};
+
+static int exynos850_cmu_top_probe(struct udevice *dev)
+{
+ return samsung_cmu_register_one(dev, top_cmu_clks,
+ ARRAY_SIZE(top_cmu_clks));
+}
+
+static const struct udevice_id exynos850_cmu_top_ids[] = {
+ { .compatible = "samsung,exynos850-cmu-top" },
+ { }
+};
+
+U_BOOT_DRIVER(exynos850_cmu_top) = {
+ .name = "exynos850-cmu-top",
+ .id = UCLASS_CLK,
+ .of_match = exynos850_cmu_top_ids,
+ .ops = &ccf_clk_ops,
+ .probe = exynos850_cmu_top_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* ---- CMU_PERI ------------------------------------------------------------ */
+
+/* Register Offset definitions for CMU_PERI (0x10030000) */
+#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630
+#define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8
+#define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac
+
+/* List of parent clocks for Muxes in CMU_PERI */
+PNAME(mout_peri_bus_user_p) = { "clock-oscclk", "dout_peri_bus" };
+PNAME(mout_peri_uart_user_p) = { "clock-oscclk", "dout_peri_uart" };
+
+static const struct samsung_mux_clock peri_mux_clks[] = {
+ MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
+ PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user",
+ mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1),
+};
+
+static const struct samsung_gate_clock peri_gate_clks[] = {
+ GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user",
+ CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0),
+ GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0),
+};
+
+static const struct samsung_clk_group peri_cmu_clks[] = {
+ { S_CLK_MUX, peri_mux_clks, ARRAY_SIZE(peri_mux_clks) },
+ { S_CLK_GATE, peri_gate_clks, ARRAY_SIZE(peri_gate_clks) },
+};
+
+static int exynos850_cmu_peri_probe(struct udevice *dev)
+{
+ return samsung_register_cmu(dev, peri_cmu_clks, exynos850_cmu_top);
+}
+
+static const struct udevice_id exynos850_cmu_peri_ids[] = {
+ { .compatible = "samsung,exynos850-cmu-peri" },
+ { }
+};
+
+U_BOOT_DRIVER(exynos850_cmu_peri) = {
+ .name = "exynos850-cmu-peri",
+ .id = UCLASS_CLK,
+ .of_match = exynos850_cmu_peri_ids,
+ .ops = &ccf_clk_ops,
+ .probe = exynos850_cmu_peri_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
index 407fc71..4aacbc2 100644
--- a/drivers/clk/exynos/clk-pll.c
+++ b/drivers/clk/exynos/clk-pll.c
@@ -1,32 +1,167 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Exynos PLL helper functions for clock drivers.
* Copyright (C) 2016 Samsung Electronics
- * Thomas Abraham <thomas.ab@samsung.com>
+ * Copyright (C) 2023 Linaro Ltd.
+ *
+ * Authors:
+ * Thomas Abraham <thomas.ab@samsung.com>
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * This file contains the utility functions to register the pll clocks.
*/
-#include <common.h>
#include <asm/io.h>
#include <div64.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <clk.h>
+#include "clk.h"
-#define PLL145X_MDIV_SHIFT 16
-#define PLL145X_MDIV_MASK 0x3ff
-#define PLL145X_PDIV_SHIFT 8
-#define PLL145X_PDIV_MASK 0x3f
-#define PLL145X_SDIV_SHIFT 0
-#define PLL145X_SDIV_MASK 0x7
+#define UBOOT_DM_CLK_SAMSUNG_PLL0822X "samsung_clk_pll0822x"
+#define UBOOT_DM_CLK_SAMSUNG_PLL0831X "samsung_clk_pll0831x"
-unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
+struct samsung_clk_pll {
+ struct clk clk;
+ void __iomem *con_reg;
+ enum samsung_pll_type type;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct samsung_clk_pll, clk)
+
+/*
+ * PLL0822x Clock Type
+ */
+
+#define PLL0822X_MDIV_MASK 0x3ff
+#define PLL0822X_PDIV_MASK 0x3f
+#define PLL0822X_SDIV_MASK 0x7
+#define PLL0822X_MDIV_SHIFT 16
+#define PLL0822X_PDIV_SHIFT 8
+#define PLL0822X_SDIV_SHIFT 0
+
+static unsigned long samsung_pll0822x_recalc_rate(struct clk *clk)
{
- unsigned long pll_con1 = readl(con1);
- unsigned long mdiv, sdiv, pdiv;
- uint64_t fvco = fin_freq;
+ struct samsung_clk_pll *pll = to_clk_pll(clk);
+ u32 mdiv, pdiv, sdiv, pll_con3;
+ u64 fvco = clk_get_parent_rate(clk);
- mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
- pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
- sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
+ pll_con3 = readl_relaxed(pll->con_reg);
+ mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
+ pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
+ sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
+
+static const struct clk_ops samsung_pll0822x_clk_min_ops = {
+ .get_rate = samsung_pll0822x_recalc_rate,
+};
+
+/*
+ * PLL0831x Clock Type
+ */
+
+#define PLL0831X_KDIV_MASK 0xffff
+#define PLL0831X_MDIV_MASK 0x1ff
+#define PLL0831X_PDIV_MASK 0x3f
+#define PLL0831X_SDIV_MASK 0x7
+#define PLL0831X_MDIV_SHIFT 16
+#define PLL0831X_PDIV_SHIFT 8
+#define PLL0831X_SDIV_SHIFT 0
+#define PLL0831X_KDIV_SHIFT 0
+
+static unsigned long samsung_pll0831x_recalc_rate(struct clk *clk)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(clk);
+ u32 mdiv, pdiv, sdiv, pll_con3, pll_con5;
+ s16 kdiv;
+ u64 fvco = clk_get_parent_rate(clk);
+
+ pll_con3 = readl_relaxed(pll->con_reg);
+ pll_con5 = readl_relaxed(pll->con_reg + 8);
+ mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK;
+ pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK;
+ sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK;
+ kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK);
+
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll0831x_clk_min_ops = {
+ .get_rate = samsung_pll0831x_recalc_rate,
+};
+
+static struct clk *_samsung_clk_register_pll(void __iomem *base,
+ const struct samsung_pll_clock *pll_clk)
+{
+ struct samsung_clk_pll *pll;
+ struct clk *clk;
+ const char *drv_name;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->con_reg = base + pll_clk->con_offset;
+ pll->type = pll_clk->type;
+ clk = &pll->clk;
+ clk->flags = pll_clk->flags;
+
+ switch (pll_clk->type) {
+ case pll_0822x:
+ drv_name = UBOOT_DM_CLK_SAMSUNG_PLL0822X;
+ break;
+ case pll_0831x:
+ drv_name = UBOOT_DM_CLK_SAMSUNG_PLL0831X;
+ break;
+ default:
+ kfree(pll);
+ return ERR_PTR(-ENODEV);
+ }
+
+ ret = clk_register(clk, drv_name, pll_clk->name, pll_clk->parent_name);
+ if (ret) {
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+void samsung_clk_register_pll(void __iomem *base,
+ const struct samsung_pll_clock *clk_list,
+ unsigned int nr_clk)
+{
+ unsigned int cnt;
+
+ for (cnt = 0; cnt < nr_clk; cnt++) {
+ struct clk *clk;
+ const struct samsung_pll_clock *pll_clk;
+
+ pll_clk = &clk_list[cnt];
+ clk = _samsung_clk_register_pll(base, pll_clk);
+ clk_dm(pll_clk->id, clk);
+ }
+}
+
+U_BOOT_DRIVER(samsung_pll0822x_clk) = {
+ .name = UBOOT_DM_CLK_SAMSUNG_PLL0822X,
+ .id = UCLASS_CLK,
+ .ops = &samsung_pll0822x_clk_min_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(samsung_pll0831x_clk) = {
+ .name = UBOOT_DM_CLK_SAMSUNG_PLL0831X,
+ .id = UCLASS_CLK,
+ .ops = &samsung_pll0831x_clk_min_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
index 7b7af5e..bd79309 100644
--- a/drivers/clk/exynos/clk-pll.h
+++ b/drivers/clk/exynos/clk-pll.h
@@ -1,13 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Exynos PLL helper functions for clock drivers.
* Copyright (C) 2016 Samsung Electronics
- * Thomas Abraham <thomas.ab@samsung.com>
+ * Copyright (C) 2023 Linaro Ltd.
+ *
+ * Authors:
+ * Thomas Abraham <thomas.ab@samsung.com>
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Common Clock Framework support for all PLL's in Samsung platforms.
*/
#ifndef __EXYNOS_CLK_PLL_H
#define __EXYNOS_CLK_PLL_H
-unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
+#include <linux/clk-provider.h>
+
+enum samsung_pll_type {
+ pll_0822x,
+ pll_0831x,
+};
#endif /* __EXYNOS_CLK_PLL_H */
diff --git a/drivers/clk/exynos/clk.c b/drivers/clk/exynos/clk.c
new file mode 100644
index 0000000..430767f
--- /dev/null
+++ b/drivers/clk/exynos/clk.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * This file includes utility functions to register clocks to common
+ * clock framework for Samsung platforms.
+ */
+
+#include <dm.h>
+#include "clk.h"
+
+void samsung_clk_register_mux(void __iomem *base,
+ const struct samsung_mux_clock *clk_list,
+ unsigned int nr_clk)
+{
+ unsigned int cnt;
+
+ for (cnt = 0; cnt < nr_clk; cnt++) {
+ struct clk *clk;
+ const struct samsung_mux_clock *m;
+
+ m = &clk_list[cnt];
+ clk = clk_register_mux(NULL, m->name, m->parent_names,
+ m->num_parents, m->flags, base + m->offset, m->shift,
+ m->width, m->mux_flags);
+ clk_dm(m->id, clk);
+ }
+}
+
+void samsung_clk_register_div(void __iomem *base,
+ const struct samsung_div_clock *clk_list,
+ unsigned int nr_clk)
+{
+ unsigned int cnt;
+
+ for (cnt = 0; cnt < nr_clk; cnt++) {
+ struct clk *clk;
+ const struct samsung_div_clock *d;
+
+ d = &clk_list[cnt];
+ clk = clk_register_divider(NULL, d->name, d->parent_name,
+ d->flags, base + d->offset, d->shift,
+ d->width, d->div_flags);
+ clk_dm(d->id, clk);
+ }
+}
+
+void samsung_clk_register_gate(void __iomem *base,
+ const struct samsung_gate_clock *clk_list,
+ unsigned int nr_clk)
+{
+ unsigned int cnt;
+
+ for (cnt = 0; cnt < nr_clk; cnt++) {
+ struct clk *clk;
+ const struct samsung_gate_clock *g;
+
+ g = &clk_list[cnt];
+ clk = clk_register_gate(NULL, g->name, g->parent_name,
+ g->flags, base + g->offset, g->bit_idx,
+ g->gate_flags, NULL);
+ clk_dm(g->id, clk);
+ }
+}
+
+typedef void (*samsung_clk_register_fn)(void __iomem *base,
+ const void *clk_list,
+ unsigned int nr_clk);
+
+static const samsung_clk_register_fn samsung_clk_register_fns[] = {
+ [S_CLK_MUX] = (samsung_clk_register_fn)samsung_clk_register_mux,
+ [S_CLK_DIV] = (samsung_clk_register_fn)samsung_clk_register_div,
+ [S_CLK_GATE] = (samsung_clk_register_fn)samsung_clk_register_gate,
+ [S_CLK_PLL] = (samsung_clk_register_fn)samsung_clk_register_pll,
+};
+
+/**
+ * samsung_cmu_register_clocks() - Register provided clock groups
+ * @base: Base address of CMU registers
+ * @clk_groups: list of clock groups
+ * @nr_groups: count of clock groups in @clk_groups
+ *
+ * Having the array of clock groups @clk_groups makes it possible to keep a
+ * correct clocks registration order.
+ */
+void samsung_cmu_register_clocks(void __iomem *base,
+ const struct samsung_clk_group *clk_groups,
+ unsigned int nr_groups)
+{
+ unsigned int i;
+
+ for (i = 0; i < nr_groups; i++) {
+ const struct samsung_clk_group *g = &clk_groups[i];
+
+ samsung_clk_register_fns[g->type](base, g->clk_list, g->nr_clk);
+ }
+}
+
+/**
+ * samsung_cmu_register_one - Register all CMU clocks
+ * @dev: CMU device
+ * @clk_groups: list of CMU clock groups
+ * @nr_groups: count of CMU clock groups in @clk_groups
+ *
+ * Return: 0 on success or negative value on error.
+ */
+int samsung_cmu_register_one(struct udevice *dev,
+ const struct samsung_clk_group *clk_groups,
+ unsigned int nr_groups)
+{
+ void __iomem *base;
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -EINVAL;
+
+ samsung_cmu_register_clocks(base, clk_groups, nr_groups);
+
+ return 0;
+}
diff --git a/drivers/clk/exynos/clk.h b/drivers/clk/exynos/clk.h
new file mode 100644
index 0000000..91a51b8
--- /dev/null
+++ b/drivers/clk/exynos/clk.h
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Common Clock Framework support for all Samsung platforms.
+ */
+
+#ifndef __EXYNOS_CLK_H
+#define __EXYNOS_CLK_H
+
+#include <errno.h>
+#include <linux/clk-provider.h>
+#include "clk-pll.h"
+
+/**
+ * struct samsung_mux_clock - information about mux clock
+ * @id: platform specific id of the clock
+ * @name: name of this mux clock
+ * @parent_names: array of pointer to parent clock names
+ * @num_parents: number of parents listed in @parent_names
+ * @flags: optional flags for basic clock
+ * @offset: offset of the register for configuring the mux
+ * @shift: starting bit location of the mux control bit-field in @reg
+ * @width: width of the mux control bit-field in @reg
+ * @mux_flags: flags for mux-type clock
+ */
+struct samsung_mux_clock {
+ unsigned int id;
+ const char *name;
+ const char * const *parent_names;
+ u8 num_parents;
+ unsigned long flags;
+ unsigned long offset;
+ u8 shift;
+ u8 width;
+ u8 mux_flags;
+};
+
+#define PNAME(x) static const char * const x[]
+
+#define __MUX(_id, cname, pnames, o, s, w, f, mf) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_names = pnames, \
+ .num_parents = ARRAY_SIZE(pnames), \
+ .flags = (f) | CLK_SET_RATE_NO_REPARENT, \
+ .offset = o, \
+ .shift = s, \
+ .width = w, \
+ .mux_flags = mf, \
+ }
+
+#define MUX(_id, cname, pnames, o, s, w) \
+ __MUX(_id, cname, pnames, o, s, w, 0, 0)
+
+#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
+ __MUX(_id, cname, pnames, o, s, w, f, mf)
+
+/**
+ * struct samsung_div_clock - information about div clock
+ * @id: platform specific id of the clock
+ * @name: name of this div clock
+ * @parent_name: name of the parent clock
+ * @flags: optional flags for basic clock
+ * @offset: offset of the register for configuring the div
+ * @shift: starting bit location of the div control bit-field in @reg
+ * @width: width of the bitfield
+ * @div_flags: flags for div-type clock
+ */
+struct samsung_div_clock {
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+ unsigned long offset;
+ u8 shift;
+ u8 width;
+ u8 div_flags;
+};
+
+#define __DIV(_id, cname, pname, o, s, w, f, df) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .flags = f, \
+ .offset = o, \
+ .shift = s, \
+ .width = w, \
+ .div_flags = df, \
+ }
+
+#define DIV(_id, cname, pname, o, s, w) \
+ __DIV(_id, cname, pname, o, s, w, 0, 0)
+
+#define DIV_F(_id, cname, pname, o, s, w, f, df) \
+ __DIV(_id, cname, pname, o, s, w, f, df)
+
+/**
+ * struct samsung_gate_clock - information about gate clock
+ * @id: platform specific id of the clock
+ * @name: name of this gate clock
+ * @parent_name: name of the parent clock
+ * @flags: optional flags for basic clock
+ * @offset: offset of the register for configuring the gate
+ * @bit_idx: bit index of the gate control bit-field in @reg
+ * @gate_flags: flags for gate-type clock
+ */
+struct samsung_gate_clock {
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+ unsigned long offset;
+ u8 bit_idx;
+ u8 gate_flags;
+};
+
+#define __GATE(_id, cname, pname, o, b, f, gf) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .flags = f, \
+ .offset = o, \
+ .bit_idx = b, \
+ .gate_flags = gf, \
+ }
+
+#define GATE(_id, cname, pname, o, b, f, gf) \
+ __GATE(_id, cname, pname, o, b, f, gf)
+
+/**
+ * struct samsung_pll_clock - information about pll clock
+ * @id: platform specific id of the clock
+ * @name: name of this pll clock
+ * @parent_name: name of the parent clock
+ * @flags: optional flags for basic clock
+ * @con_offset: offset of the register for configuring the PLL
+ * @type: type of PLL to be registered
+ */
+struct samsung_pll_clock {
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+ int con_offset;
+ enum samsung_pll_type type;
+};
+
+#define PLL(_typ, _id, _name, _pname, _con) \
+ { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .flags = CLK_GET_RATE_NOCACHE, \
+ .con_offset = _con, \
+ .type = _typ, \
+ }
+
+enum samsung_clock_type {
+ S_CLK_MUX,
+ S_CLK_DIV,
+ S_CLK_GATE,
+ S_CLK_PLL,
+};
+
+/**
+ * struct samsung_clock_group - contains a list of clocks of one type
+ * @type: type of clocks this structure contains
+ * @clk_list: list of clocks
+ * @nr_clk: count of clocks in @clk_list
+ */
+struct samsung_clk_group {
+ enum samsung_clock_type type;
+ const void *clk_list;
+ unsigned int nr_clk;
+};
+
+void samsung_clk_register_mux(void __iomem *base,
+ const struct samsung_mux_clock *clk_list,
+ unsigned int nr_clk);
+void samsung_clk_register_div(void __iomem *base,
+ const struct samsung_div_clock *clk_list,
+ unsigned int nr_clk);
+void samsung_clk_register_gate(void __iomem *base,
+ const struct samsung_gate_clock *clk_list,
+ unsigned int nr_clk);
+void samsung_clk_register_pll(void __iomem *base,
+ const struct samsung_pll_clock *clk_list,
+ unsigned int nr_clk);
+
+void samsung_cmu_register_clocks(void __iomem *base,
+ const struct samsung_clk_group *clk_groups,
+ unsigned int nr_groups);
+int samsung_cmu_register_one(struct udevice *dev,
+ const struct samsung_clk_group *clk_groups,
+ unsigned int nr_groups);
+
+/**
+ * samsung_register_cmu - Register CMU clocks ensuring parent CMU is present
+ * @dev: CMU device
+ * @clk_groups: list of CMU clock groups
+ * @parent_drv: name of parent CMU driver
+ *
+ * Register provided CMU clocks, but make sure CMU_TOP driver is instantiated
+ * first.
+ *
+ * Return: 0 on success or negative value on error.
+ */
+#define samsung_register_cmu(dev, clk_groups, parent_drv) \
+({ \
+ struct udevice *__parent; \
+ int __ret; \
+ \
+ __ret = uclass_get_device_by_driver(UCLASS_CLK, \
+ DM_DRIVER_GET(parent_drv), &__parent); \
+ if (__ret || !__parent) \
+ __ret = -ENOENT; \
+ else \
+ __ret = samsung_cmu_register_one(dev, clk_groups, \
+ ARRAY_SIZE(clk_groups)); \
+ __ret; \
+})
+
+#endif /* __EXYNOS_CLK_H */
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index 66ffef9..89f2d96 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -298,6 +298,15 @@
if (!priv->cpg_pll_config->extal_div)
return -EINVAL;
+ if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
+ priv->info->status_regs = mstpsr;
+ priv->info->control_regs = smstpcr;
+ priv->info->reset_regs = srcr;
+ priv->info->reset_clear_regs = srstclr;
+ } else {
+ return -EINVAL;
+ }
+
ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
if (ret < 0)
return ret;
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 38a2874..4e83b8c 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -80,6 +80,7 @@
#endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */
/* EON -- en25xxx */
+ { INFO("en25q80b", 0x1c3014, 0, 64 * 1024, 16, SECT_4K) },
{ INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
{ INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
diff --git a/drivers/pinctrl/exynos/Kconfig b/drivers/pinctrl/exynos/Kconfig
index a60f498..1b7fb62 100644
--- a/drivers/pinctrl/exynos/Kconfig
+++ b/drivers/pinctrl/exynos/Kconfig
@@ -16,3 +16,11 @@
help
Support pin multiplexing and pin configuration control on
Samsung's Exynos78x0 SoC.
+
+config PINCTRL_EXYNOS850
+ bool "Samsung Exynos850 pinctrl driver"
+ depends on ARCH_EXYNOS && PINCTRL_FULL
+ select PINCTRL_EXYNOS
+ help
+ Support pin multiplexing and pin configuration control on
+ Samsung's Exynos850 SoC.
diff --git a/drivers/pinctrl/exynos/Makefile b/drivers/pinctrl/exynos/Makefile
index 07db970..3abe122 100644
--- a/drivers/pinctrl/exynos/Makefile
+++ b/drivers/pinctrl/exynos/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o
obj-$(CONFIG_PINCTRL_EXYNOS78x0) += pinctrl-exynos78x0.o
+obj-$(CONFIG_PINCTRL_EXYNOS850) += pinctrl-exynos850.o
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos850.c b/drivers/pinctrl/exynos/pinctrl-exynos850.c
new file mode 100644
index 0000000..3ec2636
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos850.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Linaro Ltd.
+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Exynos850 pinctrl driver.
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include "pinctrl-exynos.h"
+
+#define EXYNOS850_PIN_BANK(pins, reg, id) \
+ { \
+ .type = &exynos850_bank_type, \
+ .offset = reg, \
+ .nr_pins = pins, \
+ .name = id \
+ }
+
+/* CON, DAT, PUD, DRV */
+static const struct samsung_pin_bank_type exynos850_bank_type = {
+ .fld_width = { 4, 1, 4, 4, },
+ .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
+static const struct pinctrl_ops exynos850_pinctrl_ops = {
+ .set_state = exynos_pinctrl_set_state
+};
+
+/* pin banks of exynos850 pin-controller 0 (ALIVE) */
+static const struct samsung_pin_bank_data exynos850_pin_banks0[] = {
+ EXYNOS850_PIN_BANK(8, 0x000, "gpa0"),
+ EXYNOS850_PIN_BANK(8, 0x020, "gpa1"),
+ EXYNOS850_PIN_BANK(8, 0x040, "gpa2"),
+ EXYNOS850_PIN_BANK(8, 0x060, "gpa3"),
+ EXYNOS850_PIN_BANK(4, 0x080, "gpa4"),
+ EXYNOS850_PIN_BANK(3, 0x0a0, "gpq0"),
+};
+
+/* pin banks of exynos850 pin-controller 1 (CMGP) */
+static const struct samsung_pin_bank_data exynos850_pin_banks1[] = {
+ EXYNOS850_PIN_BANK(1, 0x000, "gpm0"),
+ EXYNOS850_PIN_BANK(1, 0x020, "gpm1"),
+ EXYNOS850_PIN_BANK(1, 0x040, "gpm2"),
+ EXYNOS850_PIN_BANK(1, 0x060, "gpm3"),
+ EXYNOS850_PIN_BANK(1, 0x080, "gpm4"),
+ EXYNOS850_PIN_BANK(1, 0x0a0, "gpm5"),
+ EXYNOS850_PIN_BANK(1, 0x0c0, "gpm6"),
+ EXYNOS850_PIN_BANK(1, 0x0e0, "gpm7"),
+};
+
+/* pin banks of exynos850 pin-controller 2 (AUD) */
+static const struct samsung_pin_bank_data exynos850_pin_banks2[] = {
+ EXYNOS850_PIN_BANK(5, 0x000, "gpb0"),
+ EXYNOS850_PIN_BANK(5, 0x020, "gpb1"),
+};
+
+/* pin banks of exynos850 pin-controller 3 (HSI) */
+static const struct samsung_pin_bank_data exynos850_pin_banks3[] = {
+ EXYNOS850_PIN_BANK(6, 0x000, "gpf2"),
+};
+
+/* pin banks of exynos850 pin-controller 4 (CORE) */
+static const struct samsung_pin_bank_data exynos850_pin_banks4[] = {
+ EXYNOS850_PIN_BANK(4, 0x000, "gpf0"),
+ EXYNOS850_PIN_BANK(8, 0x020, "gpf1"),
+};
+
+/* pin banks of exynos850 pin-controller 5 (PERI) */
+static const struct samsung_pin_bank_data exynos850_pin_banks5[] = {
+ EXYNOS850_PIN_BANK(2, 0x000, "gpg0"),
+ EXYNOS850_PIN_BANK(6, 0x020, "gpp0"),
+ EXYNOS850_PIN_BANK(4, 0x040, "gpp1"),
+ EXYNOS850_PIN_BANK(4, 0x060, "gpp2"),
+ EXYNOS850_PIN_BANK(8, 0x080, "gpg1"),
+ EXYNOS850_PIN_BANK(8, 0x0a0, "gpg2"),
+ EXYNOS850_PIN_BANK(1, 0x0c0, "gpg3"),
+ EXYNOS850_PIN_BANK(3, 0x0e0, "gpc0"),
+ EXYNOS850_PIN_BANK(6, 0x100, "gpc1"),
+};
+
+static const struct samsung_pin_ctrl exynos850_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 ALIVE data */
+ .pin_banks = exynos850_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos850_pin_banks0),
+ }, {
+ /* pin-controller instance 1 CMGP data */
+ .pin_banks = exynos850_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos850_pin_banks1),
+ }, {
+ /* pin-controller instance 2 AUD data */
+ .pin_banks = exynos850_pin_banks2,
+ .nr_banks = ARRAY_SIZE(exynos850_pin_banks2),
+ }, {
+ /* pin-controller instance 3 HSI data */
+ .pin_banks = exynos850_pin_banks3,
+ .nr_banks = ARRAY_SIZE(exynos850_pin_banks3),
+ }, {
+ /* pin-controller instance 4 CORE data */
+ .pin_banks = exynos850_pin_banks4,
+ .nr_banks = ARRAY_SIZE(exynos850_pin_banks4),
+ }, {
+ /* pin-controller instance 5 PERI data */
+ .pin_banks = exynos850_pin_banks5,
+ .nr_banks = ARRAY_SIZE(exynos850_pin_banks5),
+ },
+ {/* list terminator */}
+};
+
+static const struct udevice_id exynos850_pinctrl_ids[] = {
+ { .compatible = "samsung,exynos850-pinctrl",
+ .data = (ulong)exynos850_pin_ctrl },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_exynos850) = {
+ .name = "pinctrl_exynos850",
+ .id = UCLASS_PINCTRL,
+ .of_match = exynos850_pinctrl_ids,
+ .priv_auto = sizeof(struct exynos_pinctrl_priv),
+ .ops = &exynos850_pinctrl_ops,
+ .probe = exynos_pinctrl_probe,
+};
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 7d04dcf..801b764 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -257,6 +257,7 @@
static const struct udevice_id s5p_serial_ids[] = {
{ .compatible = "samsung,exynos4210-uart", .data = PORT_S5P },
+ { .compatible = "samsung,exynos850-uart", .data = PORT_S5P },
{ .compatible = "apple,s5l-uart", .data = PORT_S5L },
{ }
};
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 85dac9d..03433bc0 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -40,6 +40,7 @@
This allows other drivers to verify the SoC familiy & revision using
matching SoC attributes.
+source "drivers/soc/samsung/Kconfig"
source "drivers/soc/ti/Kconfig"
endmenu
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 8438565..610bf81 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
#
# Makefile for the U-Boot SOC specific device drivers.
+obj-$(CONFIG_SOC_SAMSUNG) += samsung/
obj-$(CONFIG_SOC_TI) += ti/
obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o
obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o
diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
new file mode 100644
index 0000000..737b7ca
--- /dev/null
+++ b/drivers/soc/samsung/Kconfig
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+menuconfig SOC_SAMSUNG
+ bool "Samsung SoC drivers support"
+
+if SOC_SAMSUNG
+
+config EXYNOS_PMU
+ bool "Exynos PMU controller driver"
+ depends on ARCH_EXYNOS
+ select REGMAP
+ select SYSCON
+ help
+ Enable support for system controller configuration driver. It allows
+ one to configure system controller registers (e.g. some register in
+ PMU syscon) by providing register's offset, mask and value.
+
+config EXYNOS_USI
+ bool "Exynos USI (Universal Serial Interface) driver"
+ depends on ARCH_EXYNOS
+ select MISC
+ select REGMAP
+ select SYSCON
+ help
+ Enable support for USI block. USI (Universal Serial Interface) is an
+ IP-core found in modern Samsung Exynos SoCs, like Exynos850 and
+ ExynosAutoV9. USI block can be configured to provide one of the
+ following serial protocols: UART, SPI or High Speed I2C.
+
+ This driver allows one to configure USI for desired protocol, which
+ is usually done in USI node in Device Tree.
+
+endif
diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
new file mode 100644
index 0000000..0eb3ed8
--- /dev/null
+++ b/drivers/soc/samsung/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o
+obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o
diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
new file mode 100644
index 0000000..233ad4a
--- /dev/null
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Linaro Ltd.
+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Exynos PMU (Power Management Unit) driver.
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#define EXYNOS850_UART_IO_SHARE_CTRL 0x0760
+#define SEL_RXD_AP_UART_SHIFT 16
+#define SEL_RXD_AP_UART_MASK GENMASK(17, 16)
+#define SEL_TXD_GPIO_1_SHIFT 20
+#define SEL_TXD_GPIO_1_MASK GENMASK(21, 20)
+#define RXD_GPIO_1 0x3
+#define TXD_AP_UART 0x0
+
+struct exynos_pmu {
+ struct udevice *dev;
+ const struct exynos_pmu_data *pmu_data;
+ struct regmap *regmap;
+};
+
+struct exynos_pmu_data {
+ int (*pmu_init)(struct exynos_pmu *priv);
+};
+
+static int exynos850_pmu_init(struct exynos_pmu *priv)
+{
+ ofnode node;
+ bool uart_debug_1;
+ unsigned int offset, mask, value;
+
+ node = dev_ofnode(priv->dev);
+ uart_debug_1 = ofnode_read_bool(node, "samsung,uart-debug-1");
+ if (!uart_debug_1)
+ return 0;
+
+ /*
+ * If uart1_pins are used for serial, AP UART lines have to be muxed
+ * in PMU block to UART_DEBUG_1 path (GPIO_1). By default (reset value)
+ * UART_DEBUG_0 path (uart0_pins) is connected to AP UART lines.
+ */
+ offset = EXYNOS850_UART_IO_SHARE_CTRL;
+ mask = SEL_RXD_AP_UART_MASK | SEL_TXD_GPIO_1_MASK;
+ value = RXD_GPIO_1 << SEL_RXD_AP_UART_SHIFT |
+ TXD_AP_UART << SEL_TXD_GPIO_1_SHIFT;
+ return regmap_update_bits(priv->regmap, offset, mask, value);
+}
+
+static const struct exynos_pmu_data exynos850_pmu_data = {
+ .pmu_init = exynos850_pmu_init,
+};
+
+static int exynos_pmu_bind(struct udevice *dev)
+{
+ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+ return 0;
+}
+
+static int exynos_pmu_probe(struct udevice *dev)
+{
+ ofnode node;
+ struct exynos_pmu *priv;
+
+ priv = dev_get_priv(dev);
+ priv->dev = dev;
+
+ node = dev_ofnode(dev);
+ priv->regmap = syscon_node_to_regmap(node);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->pmu_data = (struct exynos_pmu_data *)dev_get_driver_data(dev);
+ if (priv->pmu_data && priv->pmu_data->pmu_init)
+ return priv->pmu_data->pmu_init(priv);
+
+ return 0;
+}
+
+static const struct udevice_id exynos_pmu_ids[] = {
+ {
+ .compatible = "samsung,exynos850-pmu",
+ .data = (ulong)&exynos850_pmu_data
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(exynos_pmu) = {
+ .name = "exynos-pmu",
+ .id = UCLASS_NOP,
+ .of_match = exynos_pmu_ids,
+ .bind = exynos_pmu_bind,
+ .probe = exynos_pmu_probe,
+ .priv_auto = sizeof(struct exynos_pmu),
+};
diff --git a/drivers/soc/samsung/exynos-usi.c b/drivers/soc/samsung/exynos-usi.c
new file mode 100644
index 0000000..b746a78
--- /dev/null
+++ b/drivers/soc/samsung/exynos-usi.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Linaro Ltd.
+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Samsung Exynos USI driver (Universal Serial Interface).
+ */
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <errno.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <dt-bindings/soc/samsung,exynos-usi.h>
+
+/* USIv2: System Register: SW_CONF register bits */
+#define USI_V2_SW_CONF_NONE 0x0
+#define USI_V2_SW_CONF_UART BIT(0)
+#define USI_V2_SW_CONF_SPI BIT(1)
+#define USI_V2_SW_CONF_I2C BIT(2)
+#define USI_V2_SW_CONF_MASK (USI_V2_SW_CONF_UART | USI_V2_SW_CONF_SPI | \
+ USI_V2_SW_CONF_I2C)
+
+/* USIv2: USI register offsets */
+#define USI_CON 0x04
+#define USI_OPTION 0x08
+
+/* USIv2: USI register bits */
+#define USI_CON_RESET BIT(0)
+#define USI_OPTION_CLKREQ_ON BIT(1)
+#define USI_OPTION_CLKSTOP_ON BIT(2)
+
+enum exynos_usi_ver {
+ USI_VER2 = 2,
+};
+
+struct exynos_usi_variant {
+ enum exynos_usi_ver ver; /* USI IP-core version */
+ unsigned int sw_conf_mask; /* SW_CONF mask for all protocols */
+ size_t min_mode; /* first index in exynos_usi_modes[] */
+ size_t max_mode; /* last index in exynos_usi_modes[] */
+};
+
+struct exynos_usi {
+ void __iomem *regs; /* USI register map */
+
+ size_t mode; /* current USI SW_CONF mode index */
+ bool clkreq_on; /* always provide clock to IP */
+
+ /* System Register */
+ struct regmap *sysreg; /* System Register map */
+ unsigned int sw_conf; /* SW_CONF register offset in sysreg */
+
+ const struct exynos_usi_variant *data;
+};
+
+struct exynos_usi_mode {
+ const char *name; /* mode name */
+ unsigned int val; /* mode register value */
+};
+
+static const struct exynos_usi_mode exynos_usi_modes[] = {
+ [USI_V2_NONE] = { .name = "none", .val = USI_V2_SW_CONF_NONE },
+ [USI_V2_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART },
+ [USI_V2_SPI] = { .name = "spi", .val = USI_V2_SW_CONF_SPI },
+ [USI_V2_I2C] = { .name = "i2c", .val = USI_V2_SW_CONF_I2C },
+};
+
+static const struct exynos_usi_variant exynos850_usi_data = {
+ .ver = USI_VER2,
+ .sw_conf_mask = USI_V2_SW_CONF_MASK,
+ .min_mode = USI_V2_NONE,
+ .max_mode = USI_V2_I2C,
+};
+
+static const struct udevice_id exynos_usi_ids[] = {
+ {
+ .compatible = "samsung,exynos850-usi",
+ .data = (ulong)&exynos850_usi_data,
+ },
+ { } /* sentinel */
+};
+
+/**
+ * exynos_usi_set_sw_conf - Set USI block configuration mode
+ * @dev: Driver object
+ *
+ * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core as specified
+ * in @usi.mode.
+ *
+ * Return: 0 on success, or negative error code on failure.
+ */
+static int exynos_usi_set_sw_conf(struct udevice *dev)
+{
+ struct exynos_usi *usi = dev_get_priv(dev);
+ size_t mode = usi->mode;
+ unsigned int val;
+ int ret;
+
+ if (mode < usi->data->min_mode || mode > usi->data->max_mode)
+ return -EINVAL;
+
+ val = exynos_usi_modes[mode].val;
+ ret = regmap_update_bits(usi->sysreg, usi->sw_conf,
+ usi->data->sw_conf_mask, val);
+ if (ret)
+ return ret;
+
+ dev_dbg(dev, "protocol: %s\n", exynos_usi_modes[mode].name);
+
+ return 0;
+}
+
+/**
+ * exynos_usi_enable - Initialize USI block
+ * @usi: USI driver object
+ *
+ * USI IP-core start state is "reset" (on startup and after CPU resume). This
+ * routine enables the USI block by clearing the reset flag. It also configures
+ * HWACG behavior (needed e.g. for UART Rx). It should be performed before
+ * underlying protocol becomes functional.
+ */
+static void exynos_usi_enable(const struct exynos_usi *usi)
+{
+ u32 val;
+
+ /* Enable USI block */
+ val = readl(usi->regs + USI_CON);
+ val &= ~USI_CON_RESET;
+ writel(val, usi->regs + USI_CON);
+ udelay(1);
+
+ /* Continuously provide the clock to USI IP w/o gating */
+ if (usi->clkreq_on) {
+ val = readl(usi->regs + USI_OPTION);
+ val &= ~USI_OPTION_CLKSTOP_ON;
+ val |= USI_OPTION_CLKREQ_ON;
+ writel(val, usi->regs + USI_OPTION);
+ }
+}
+
+static int exynos_usi_configure(struct udevice *dev)
+{
+ struct exynos_usi *usi = dev_get_priv(dev);
+ int ret;
+
+ ret = exynos_usi_set_sw_conf(dev);
+ if (ret)
+ return ret;
+
+ if (usi->data->ver == USI_VER2)
+ exynos_usi_enable(usi);
+
+ return 0;
+}
+
+static int exynos_usi_of_to_plat(struct udevice *dev)
+{
+ struct exynos_usi *usi = dev_get_priv(dev);
+ ofnode node = dev_ofnode(dev);
+ int ret;
+ u32 mode;
+
+ usi->data = (struct exynos_usi_variant *)dev_get_driver_data(dev);
+ if (usi->data->ver == USI_VER2) {
+ usi->regs = dev_read_addr_ptr(dev);
+ if (!usi->regs)
+ return -ENODEV;
+ }
+
+ ret = ofnode_read_u32(node, "samsung,mode", &mode);
+ if (ret)
+ return ret;
+ if (mode < usi->data->min_mode || mode > usi->data->max_mode)
+ return -EINVAL;
+ usi->mode = mode;
+
+ usi->sysreg = syscon_regmap_lookup_by_phandle(dev, "samsung,sysreg");
+ if (IS_ERR(usi->sysreg))
+ return PTR_ERR(usi->sysreg);
+
+ ret = ofnode_read_u32_index(node, "samsung,sysreg", 1, &usi->sw_conf);
+ if (ret)
+ return ret;
+
+ usi->clkreq_on = ofnode_read_bool(node, "samsung,clkreq-on");
+
+ return 0;
+}
+
+static int exynos_usi_probe(struct udevice *dev)
+{
+ return exynos_usi_configure(dev);
+}
+
+U_BOOT_DRIVER(exynos_usi) = {
+ .name = "exynos-usi",
+ .id = UCLASS_MISC,
+ .of_match = exynos_usi_ids,
+ .of_to_plat = exynos_usi_of_to_plat,
+ .probe = exynos_usi_probe,
+ .priv_auto = sizeof(struct exynos_usi),
+};
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index d9a5944..786825d 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -35,13 +35,15 @@
#define IDCODE2_PL_INIT_SHIFT 9
#define IDCODE2_PL_INIT_MASK BIT(IDCODE2_PL_INIT_SHIFT)
-#define ZYNQMP_VERSION_SIZE 7
+#define ZYNQMP_VERSION_SIZE 10
enum {
ZYNQMP_VARIANT_EG = BIT(0),
ZYNQMP_VARIANT_EV = BIT(1),
ZYNQMP_VARIANT_CG = BIT(2),
ZYNQMP_VARIANT_DR = BIT(3),
+ ZYNQMP_VARIANT_DR_SE = BIT(4),
+ ZYNQMP_VARIANT_EG_SE = BIT(5),
};
struct zynqmp_device {
@@ -106,6 +108,11 @@
.variants = ZYNQMP_VARIANT_EG,
},
{
+ .id = 0x04741093,
+ .device = 11,
+ .variants = ZYNQMP_VARIANT_EG_SE,
+ },
+ {
.id = 0x04750093,
.device = 15,
.variants = ZYNQMP_VARIANT_EG,
@@ -121,6 +128,11 @@
.variants = ZYNQMP_VARIANT_EG,
},
{
+ .id = 0x0475C093,
+ .device = 19,
+ .variants = ZYNQMP_VARIANT_EG_SE,
+ },
+ {
.id = 0x047E1093,
.device = 21,
.variants = ZYNQMP_VARIANT_DR,
@@ -171,6 +183,11 @@
.variants = ZYNQMP_VARIANT_DR,
},
{
+ .id = 0x047FA093,
+ .device = 47,
+ .variants = ZYNQMP_VARIANT_DR_SE,
+ },
+ {
.id = 0x047FB093,
.device = 48,
.variants = ZYNQMP_VARIANT_DR,
@@ -186,6 +203,11 @@
.variants = ZYNQMP_VARIANT_DR,
},
{
+ .id = 0x046d7093,
+ .device = 67,
+ .variants = ZYNQMP_VARIANT_DR_SE,
+ },
+ {
.id = 0x04712093,
.device = 24,
.variants = 0,
@@ -271,8 +293,12 @@
"cg" : "eg", sizeof(priv->machine));
} else if (device->variants & ZYNQMP_VARIANT_EG) {
strlcat(priv->machine, "eg", sizeof(priv->machine));
+ } else if (device->variants & ZYNQMP_VARIANT_EG_SE) {
+ strlcat(priv->machine, "eg_SE", sizeof(priv->machine));
} else if (device->variants & ZYNQMP_VARIANT_DR) {
strlcat(priv->machine, "dr", sizeof(priv->machine));
+ } else if (device->variants & ZYNQMP_VARIANT_DR_SE) {
+ strlcat(priv->machine, "dr_SE", sizeof(priv->machine));
}
return 0;
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 0dd5736..f96027d 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -210,10 +210,10 @@
config USB_EHCI_MX7
bool "Support for i.MX7 on-chip EHCI USB controller"
- depends on ARCH_MX7 || IMX8M
+ depends on ARCH_MX7 || IMX8M || IMX93
select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7
- select PHY if IMX8M
- select NOP_PHY if IMX8M
+ select PHY if IMX8M || IMX93
+ select NOP_PHY if IMX8M || IMX93
default y
---help---
Enables support for the on-chip EHCI controller on i.MX7 SoCs.
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index a9ed5e7..a35fcca 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -538,7 +538,7 @@
plat->init_type = USB_INIT_DEVICE;
else
plat->init_type = USB_INIT_HOST;
- } else if (is_mx7() || is_imx8mm() || is_imx8mn()) {
+ } else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx93()) {
phy_status = (void __iomem *)(addr +
USBNC_PHY_STATUS_OFFSET);
val = readl(phy_status);
diff --git a/include/avb_verify.h b/include/avb_verify.h
index 1e787ba..5d998b5 100644
--- a/include/avb_verify.h
+++ b/include/avb_verify.h
@@ -1,8 +1,6 @@
-
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2018, Linaro Limited
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _AVB_VERIFY_H
@@ -54,7 +52,8 @@
char *avb_set_ignore_corruption(const char *cmdline);
char *append_cmd_line(char *cmdline_orig, char *cmdline_new);
-
+const char *str_avb_io_error(AvbIOResult res);
+const char *str_avb_slot_error(AvbSlotVerifyResult res);
/**
* ============================================================================
* I/O helper inline functions
diff --git a/include/configs/e850-96.h b/include/configs/e850-96.h
new file mode 100644
index 0000000..4607b30
--- /dev/null
+++ b/include/configs/e850-96.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020, Linaro Limited
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Configuration for E850-96 board.
+ */
+
+#ifndef __E850_96_H
+#define __E850_96_H
+
+#endif /* __E850_96_H */
diff --git a/include/configs/imx6dl-sielaff.h b/include/configs/imx6dl-sielaff.h
new file mode 100644
index 0000000..df07413
--- /dev/null
+++ b/include/configs/imx6dl-sielaff.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+#ifndef __MX6SSIELAFF_CONFIG_H
+#define __MX6SSIELAFF_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+#define CFG_MXC_UART_BASE UART2_BASE
+
+#define PHYS_SDRAM_SIZE SZ_512M
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CFG_SYS_FSL_USDHC_NUM 1
+
+#define CFG_SYS_NAND_BASE 0x40000000
+
+#endif /* __MX6SSIELAFF_CONFIG_H */
diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
index 2af2dde..b370e25 100644
--- a/include/configs/imxrt1050-evk.h
+++ b/include/configs/imxrt1050-evk.h
@@ -25,4 +25,10 @@
"stderr=serial,vidconsole\0"
#endif
+/*
+ * Address of U-Boot for SPI NOR boot
+ */
+
+#define CFG_SYS_UBOOT_BASE 0x60010000
+
#endif /* __IMXRT1050_EVK_H */
diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h
index c1c1fd5..3c7d96c 100644
--- a/include/configs/msc_sm2s_imx8mp.h
+++ b/include/configs/msc_sm2s_imx8mp.h
@@ -55,8 +55,6 @@
#define PHYS_SDRAM_2 0xc0000000
#define PHYS_SDRAM_2_SIZE 0x0
-#define CFG_MXC_UART_BASE UART2_BASE_ADDR
-
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_FSL_ESDHC_ADDR 0
diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h
index 2b441da..9cb6b2b 100644
--- a/include/configs/xilinx_versal_net.h
+++ b/include/configs/xilinx_versal_net.h
@@ -16,8 +16,8 @@
/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
/* Generic Interrupt Controller Definitions */
-#define GICD_BASE 0xF9000000
-#define GICR_BASE 0xF9060000
+#define GICD_BASE 0xe2000000
+#define GICR_BASE 0xe2060000
/* Serial setup */
#define CFG_SYS_BAUDRATE_TABLE \
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
new file mode 100644
index 0000000..3090e09
--- /dev/null
+++ b/include/dt-bindings/clock/exynos850.h
@@ -0,0 +1,337 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2021 Linaro Ltd.
+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Device Tree binding constants for Exynos850 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_850_H
+
+/* CMU_TOP */
+#define CLK_FOUT_SHARED0_PLL 1
+#define CLK_FOUT_SHARED1_PLL 2
+#define CLK_FOUT_MMC_PLL 3
+#define CLK_MOUT_SHARED0_PLL 4
+#define CLK_MOUT_SHARED1_PLL 5
+#define CLK_MOUT_MMC_PLL 6
+#define CLK_MOUT_CORE_BUS 7
+#define CLK_MOUT_CORE_CCI 8
+#define CLK_MOUT_CORE_MMC_EMBD 9
+#define CLK_MOUT_CORE_SSS 10
+#define CLK_MOUT_DPU 11
+#define CLK_MOUT_HSI_BUS 12
+#define CLK_MOUT_HSI_MMC_CARD 13
+#define CLK_MOUT_HSI_USB20DRD 14
+#define CLK_MOUT_PERI_BUS 15
+#define CLK_MOUT_PERI_UART 16
+#define CLK_MOUT_PERI_IP 17
+#define CLK_DOUT_SHARED0_DIV3 18
+#define CLK_DOUT_SHARED0_DIV2 19
+#define CLK_DOUT_SHARED1_DIV3 20
+#define CLK_DOUT_SHARED1_DIV2 21
+#define CLK_DOUT_SHARED0_DIV4 22
+#define CLK_DOUT_SHARED1_DIV4 23
+#define CLK_DOUT_CORE_BUS 24
+#define CLK_DOUT_CORE_CCI 25
+#define CLK_DOUT_CORE_MMC_EMBD 26
+#define CLK_DOUT_CORE_SSS 27
+#define CLK_DOUT_DPU 28
+#define CLK_DOUT_HSI_BUS 29
+#define CLK_DOUT_HSI_MMC_CARD 30
+#define CLK_DOUT_HSI_USB20DRD 31
+#define CLK_DOUT_PERI_BUS 32
+#define CLK_DOUT_PERI_UART 33
+#define CLK_DOUT_PERI_IP 34
+#define CLK_GOUT_CORE_BUS 35
+#define CLK_GOUT_CORE_CCI 36
+#define CLK_GOUT_CORE_MMC_EMBD 37
+#define CLK_GOUT_CORE_SSS 38
+#define CLK_GOUT_DPU 39
+#define CLK_GOUT_HSI_BUS 40
+#define CLK_GOUT_HSI_MMC_CARD 41
+#define CLK_GOUT_HSI_USB20DRD 42
+#define CLK_GOUT_PERI_BUS 43
+#define CLK_GOUT_PERI_UART 44
+#define CLK_GOUT_PERI_IP 45
+#define CLK_MOUT_CLKCMU_APM_BUS 46
+#define CLK_DOUT_CLKCMU_APM_BUS 47
+#define CLK_GOUT_CLKCMU_APM_BUS 48
+#define CLK_MOUT_AUD 49
+#define CLK_GOUT_AUD 50
+#define CLK_DOUT_AUD 51
+#define CLK_MOUT_IS_BUS 52
+#define CLK_MOUT_IS_ITP 53
+#define CLK_MOUT_IS_VRA 54
+#define CLK_MOUT_IS_GDC 55
+#define CLK_GOUT_IS_BUS 56
+#define CLK_GOUT_IS_ITP 57
+#define CLK_GOUT_IS_VRA 58
+#define CLK_GOUT_IS_GDC 59
+#define CLK_DOUT_IS_BUS 60
+#define CLK_DOUT_IS_ITP 61
+#define CLK_DOUT_IS_VRA 62
+#define CLK_DOUT_IS_GDC 63
+#define CLK_MOUT_MFCMSCL_MFC 64
+#define CLK_MOUT_MFCMSCL_M2M 65
+#define CLK_MOUT_MFCMSCL_MCSC 66
+#define CLK_MOUT_MFCMSCL_JPEG 67
+#define CLK_GOUT_MFCMSCL_MFC 68
+#define CLK_GOUT_MFCMSCL_M2M 69
+#define CLK_GOUT_MFCMSCL_MCSC 70
+#define CLK_GOUT_MFCMSCL_JPEG 71
+#define CLK_DOUT_MFCMSCL_MFC 72
+#define CLK_DOUT_MFCMSCL_M2M 73
+#define CLK_DOUT_MFCMSCL_MCSC 74
+#define CLK_DOUT_MFCMSCL_JPEG 75
+#define CLK_MOUT_G3D_SWITCH 76
+#define CLK_GOUT_G3D_SWITCH 77
+#define CLK_DOUT_G3D_SWITCH 78
+
+/* CMU_APM */
+#define CLK_RCO_I3C_PMIC 1
+#define OSCCLK_RCO_APM 2
+#define CLK_RCO_APM__ALV 3
+#define CLK_DLL_DCO 4
+#define CLK_MOUT_APM_BUS_USER 5
+#define CLK_MOUT_RCO_APM_I3C_USER 6
+#define CLK_MOUT_RCO_APM_USER 7
+#define CLK_MOUT_DLL_USER 8
+#define CLK_MOUT_CLKCMU_CHUB_BUS 9
+#define CLK_MOUT_APM_BUS 10
+#define CLK_MOUT_APM_I3C 11
+#define CLK_DOUT_CLKCMU_CHUB_BUS 12
+#define CLK_DOUT_APM_BUS 13
+#define CLK_DOUT_APM_I3C 14
+#define CLK_GOUT_CLKCMU_CMGP_BUS 15
+#define CLK_GOUT_CLKCMU_CHUB_BUS 16
+#define CLK_GOUT_RTC_PCLK 17
+#define CLK_GOUT_TOP_RTC_PCLK 18
+#define CLK_GOUT_I3C_PCLK 19
+#define CLK_GOUT_I3C_SCLK 20
+#define CLK_GOUT_SPEEDY_PCLK 21
+#define CLK_GOUT_GPIO_ALIVE_PCLK 22
+#define CLK_GOUT_PMU_ALIVE_PCLK 23
+#define CLK_GOUT_SYSREG_APM_PCLK 24
+
+/* CMU_AUD */
+#define CLK_DOUT_AUD_AUDIF 1
+#define CLK_DOUT_AUD_BUSD 2
+#define CLK_DOUT_AUD_BUSP 3
+#define CLK_DOUT_AUD_CNT 4
+#define CLK_DOUT_AUD_CPU 5
+#define CLK_DOUT_AUD_CPU_ACLK 6
+#define CLK_DOUT_AUD_CPU_PCLKDBG 7
+#define CLK_DOUT_AUD_FM 8
+#define CLK_DOUT_AUD_FM_SPDY 9
+#define CLK_DOUT_AUD_MCLK 10
+#define CLK_DOUT_AUD_UAIF0 11
+#define CLK_DOUT_AUD_UAIF1 12
+#define CLK_DOUT_AUD_UAIF2 13
+#define CLK_DOUT_AUD_UAIF3 14
+#define CLK_DOUT_AUD_UAIF4 15
+#define CLK_DOUT_AUD_UAIF5 16
+#define CLK_DOUT_AUD_UAIF6 17
+#define CLK_FOUT_AUD_PLL 18
+#define CLK_GOUT_AUD_ABOX_ACLK 19
+#define CLK_GOUT_AUD_ASB_CCLK 20
+#define CLK_GOUT_AUD_CA32_CCLK 21
+#define CLK_GOUT_AUD_CNT_BCLK 22
+#define CLK_GOUT_AUD_CODEC_MCLK 23
+#define CLK_GOUT_AUD_DAP_CCLK 24
+#define CLK_GOUT_AUD_GPIO_PCLK 25
+#define CLK_GOUT_AUD_PPMU_ACLK 26
+#define CLK_GOUT_AUD_PPMU_PCLK 27
+#define CLK_GOUT_AUD_SPDY_BCLK 28
+#define CLK_GOUT_AUD_SYSMMU_CLK 29
+#define CLK_GOUT_AUD_SYSREG_PCLK 30
+#define CLK_GOUT_AUD_TZPC_PCLK 31
+#define CLK_GOUT_AUD_UAIF0_BCLK 32
+#define CLK_GOUT_AUD_UAIF1_BCLK 33
+#define CLK_GOUT_AUD_UAIF2_BCLK 34
+#define CLK_GOUT_AUD_UAIF3_BCLK 35
+#define CLK_GOUT_AUD_UAIF4_BCLK 36
+#define CLK_GOUT_AUD_UAIF5_BCLK 37
+#define CLK_GOUT_AUD_UAIF6_BCLK 38
+#define CLK_GOUT_AUD_WDT_PCLK 39
+#define CLK_MOUT_AUD_CPU 40
+#define CLK_MOUT_AUD_CPU_HCH 41
+#define CLK_MOUT_AUD_CPU_USER 42
+#define CLK_MOUT_AUD_FM 43
+#define CLK_MOUT_AUD_PLL 44
+#define CLK_MOUT_AUD_TICK_USB_USER 45
+#define CLK_MOUT_AUD_UAIF0 46
+#define CLK_MOUT_AUD_UAIF1 47
+#define CLK_MOUT_AUD_UAIF2 48
+#define CLK_MOUT_AUD_UAIF3 49
+#define CLK_MOUT_AUD_UAIF4 50
+#define CLK_MOUT_AUD_UAIF5 51
+#define CLK_MOUT_AUD_UAIF6 52
+#define IOCLK_AUDIOCDCLK0 53
+#define IOCLK_AUDIOCDCLK1 54
+#define IOCLK_AUDIOCDCLK2 55
+#define IOCLK_AUDIOCDCLK3 56
+#define IOCLK_AUDIOCDCLK4 57
+#define IOCLK_AUDIOCDCLK5 58
+#define IOCLK_AUDIOCDCLK6 59
+#define TICK_USB 60
+#define CLK_GOUT_AUD_CMU_AUD_PCLK 61
+
+/* CMU_CMGP */
+#define CLK_RCO_CMGP 1
+#define CLK_MOUT_CMGP_ADC 2
+#define CLK_MOUT_CMGP_USI0 3
+#define CLK_MOUT_CMGP_USI1 4
+#define CLK_DOUT_CMGP_ADC 5
+#define CLK_DOUT_CMGP_USI0 6
+#define CLK_DOUT_CMGP_USI1 7
+#define CLK_GOUT_CMGP_ADC_S0_PCLK 8
+#define CLK_GOUT_CMGP_ADC_S1_PCLK 9
+#define CLK_GOUT_CMGP_GPIO_PCLK 10
+#define CLK_GOUT_CMGP_USI0_IPCLK 11
+#define CLK_GOUT_CMGP_USI0_PCLK 12
+#define CLK_GOUT_CMGP_USI1_IPCLK 13
+#define CLK_GOUT_CMGP_USI1_PCLK 14
+#define CLK_GOUT_SYSREG_CMGP_PCLK 15
+
+/* CMU_G3D */
+#define CLK_FOUT_G3D_PLL 1
+#define CLK_MOUT_G3D_PLL 2
+#define CLK_MOUT_G3D_SWITCH_USER 3
+#define CLK_MOUT_G3D_BUSD 4
+#define CLK_DOUT_G3D_BUSP 5
+#define CLK_GOUT_G3D_CMU_G3D_PCLK 6
+#define CLK_GOUT_G3D_GPU_CLK 7
+#define CLK_GOUT_G3D_TZPC_PCLK 8
+#define CLK_GOUT_G3D_GRAY2BIN_CLK 9
+#define CLK_GOUT_G3D_BUSD_CLK 10
+#define CLK_GOUT_G3D_BUSP_CLK 11
+#define CLK_GOUT_G3D_SYSREG_PCLK 12
+
+/* CMU_HSI */
+#define CLK_MOUT_HSI_BUS_USER 1
+#define CLK_MOUT_HSI_MMC_CARD_USER 2
+#define CLK_MOUT_HSI_USB20DRD_USER 3
+#define CLK_MOUT_HSI_RTC 4
+#define CLK_GOUT_USB_RTC_CLK 5
+#define CLK_GOUT_USB_REF_CLK 6
+#define CLK_GOUT_USB_PHY_REF_CLK 7
+#define CLK_GOUT_USB_PHY_ACLK 8
+#define CLK_GOUT_USB_BUS_EARLY_CLK 9
+#define CLK_GOUT_GPIO_HSI_PCLK 10
+#define CLK_GOUT_MMC_CARD_ACLK 11
+#define CLK_GOUT_MMC_CARD_SDCLKIN 12
+#define CLK_GOUT_SYSREG_HSI_PCLK 13
+#define CLK_GOUT_HSI_PPMU_ACLK 14
+#define CLK_GOUT_HSI_PPMU_PCLK 15
+#define CLK_GOUT_HSI_CMU_HSI_PCLK 16
+
+/* CMU_IS */
+#define CLK_MOUT_IS_BUS_USER 1
+#define CLK_MOUT_IS_ITP_USER 2
+#define CLK_MOUT_IS_VRA_USER 3
+#define CLK_MOUT_IS_GDC_USER 4
+#define CLK_DOUT_IS_BUSP 5
+#define CLK_GOUT_IS_CMU_IS_PCLK 6
+#define CLK_GOUT_IS_CSIS0_ACLK 7
+#define CLK_GOUT_IS_CSIS1_ACLK 8
+#define CLK_GOUT_IS_CSIS2_ACLK 9
+#define CLK_GOUT_IS_TZPC_PCLK 10
+#define CLK_GOUT_IS_CSIS_DMA_CLK 11
+#define CLK_GOUT_IS_GDC_CLK 12
+#define CLK_GOUT_IS_IPP_CLK 13
+#define CLK_GOUT_IS_ITP_CLK 14
+#define CLK_GOUT_IS_MCSC_CLK 15
+#define CLK_GOUT_IS_VRA_CLK 16
+#define CLK_GOUT_IS_PPMU_IS0_ACLK 17
+#define CLK_GOUT_IS_PPMU_IS0_PCLK 18
+#define CLK_GOUT_IS_PPMU_IS1_ACLK 19
+#define CLK_GOUT_IS_PPMU_IS1_PCLK 20
+#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
+#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
+#define CLK_GOUT_IS_SYSREG_PCLK 23
+
+/* CMU_MFCMSCL */
+#define CLK_MOUT_MFCMSCL_MFC_USER 1
+#define CLK_MOUT_MFCMSCL_M2M_USER 2
+#define CLK_MOUT_MFCMSCL_MCSC_USER 3
+#define CLK_MOUT_MFCMSCL_JPEG_USER 4
+#define CLK_DOUT_MFCMSCL_BUSP 5
+#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6
+#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7
+#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8
+#define CLK_GOUT_MFCMSCL_M2M_ACLK 9
+#define CLK_GOUT_MFCMSCL_MCSC_CLK 10
+#define CLK_GOUT_MFCMSCL_MFC_ACLK 11
+#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12
+#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13
+#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14
+#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15
+
+/* CMU_PERI */
+#define CLK_MOUT_PERI_BUS_USER 1
+#define CLK_MOUT_PERI_UART_USER 2
+#define CLK_MOUT_PERI_HSI2C_USER 3
+#define CLK_MOUT_PERI_SPI_USER 4
+#define CLK_DOUT_PERI_HSI2C0 5
+#define CLK_DOUT_PERI_HSI2C1 6
+#define CLK_DOUT_PERI_HSI2C2 7
+#define CLK_DOUT_PERI_SPI0 8
+#define CLK_GOUT_PERI_HSI2C0 9
+#define CLK_GOUT_PERI_HSI2C1 10
+#define CLK_GOUT_PERI_HSI2C2 11
+#define CLK_GOUT_GPIO_PERI_PCLK 12
+#define CLK_GOUT_HSI2C0_IPCLK 13
+#define CLK_GOUT_HSI2C0_PCLK 14
+#define CLK_GOUT_HSI2C1_IPCLK 15
+#define CLK_GOUT_HSI2C1_PCLK 16
+#define CLK_GOUT_HSI2C2_IPCLK 17
+#define CLK_GOUT_HSI2C2_PCLK 18
+#define CLK_GOUT_I2C0_PCLK 19
+#define CLK_GOUT_I2C1_PCLK 20
+#define CLK_GOUT_I2C2_PCLK 21
+#define CLK_GOUT_I2C3_PCLK 22
+#define CLK_GOUT_I2C4_PCLK 23
+#define CLK_GOUT_I2C5_PCLK 24
+#define CLK_GOUT_I2C6_PCLK 25
+#define CLK_GOUT_MCT_PCLK 26
+#define CLK_GOUT_PWM_MOTOR_PCLK 27
+#define CLK_GOUT_SPI0_IPCLK 28
+#define CLK_GOUT_SPI0_PCLK 29
+#define CLK_GOUT_SYSREG_PERI_PCLK 30
+#define CLK_GOUT_UART_IPCLK 31
+#define CLK_GOUT_UART_PCLK 32
+#define CLK_GOUT_WDT0_PCLK 33
+#define CLK_GOUT_WDT1_PCLK 34
+
+/* CMU_CORE */
+#define CLK_MOUT_CORE_BUS_USER 1
+#define CLK_MOUT_CORE_CCI_USER 2
+#define CLK_MOUT_CORE_MMC_EMBD_USER 3
+#define CLK_MOUT_CORE_SSS_USER 4
+#define CLK_MOUT_CORE_GIC 5
+#define CLK_DOUT_CORE_BUSP 6
+#define CLK_GOUT_CCI_ACLK 7
+#define CLK_GOUT_GIC_CLK 8
+#define CLK_GOUT_MMC_EMBD_ACLK 9
+#define CLK_GOUT_MMC_EMBD_SDCLKIN 10
+#define CLK_GOUT_SSS_ACLK 11
+#define CLK_GOUT_SSS_PCLK 12
+#define CLK_GOUT_GPIO_CORE_PCLK 13
+#define CLK_GOUT_SYSREG_CORE_PCLK 14
+
+/* CMU_DPU */
+#define CLK_MOUT_DPU_USER 1
+#define CLK_DOUT_DPU_BUSP 2
+#define CLK_GOUT_DPU_CMU_DPU_PCLK 3
+#define CLK_GOUT_DPU_DECON0_ACLK 4
+#define CLK_GOUT_DPU_DMA_ACLK 5
+#define CLK_GOUT_DPU_DPP_ACLK 6
+#define CLK_GOUT_DPU_PPMU_ACLK 7
+#define CLK_GOUT_DPU_PPMU_PCLK 8
+#define CLK_GOUT_DPU_SMMU_CLK 9
+#define CLK_GOUT_DPU_SYSREG_PCLK 10
+#define DPU_NR_CLK 11
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */
diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h
new file mode 100644
index 0000000..a01af16
--- /dev/null
+++ b/include/dt-bindings/soc/samsung,exynos-usi.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021 Linaro Ltd.
+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Device Tree bindings for Samsung Exynos USI (Universal Serial Interface).
+ */
+
+#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
+#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
+
+#define USI_V2_NONE 0
+#define USI_V2_UART 1
+#define USI_V2_SPI 2
+#define USI_V2_I2C 3
+
+#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */
diff --git a/include/env/ti/default_findfdt.env b/include/env/ti/default_findfdt.env
deleted file mode 100644
index a2b51dd..0000000
--- a/include/env/ti/default_findfdt.env
+++ /dev/null
@@ -1,12 +0,0 @@
-default_device_tree=CONFIG_DEFAULT_DEVICE_TREE
-default_device_tree_arch=ti
-#ifdef CONFIG_ARM64
-findfdt=
- setenv name_fdt ${default_device_tree_arch}/${default_device_tree}.dtb;
- setenv fdtfile ${name_fdt}
-#else
-default_device_tree_subarch=omap
-findfdt=
- setenv name_fdt ${default_device_tree_arch}/${default_device_tree_subarch}/${default_device_tree}.dtb;
- setenv fdtfile ${name_fdt}
-#endif
diff --git a/test/py/tests/test_android/test_avb.py b/test/py/tests/test_android/test_avb.py
index 238b48c..865efbc 100644
--- a/test/py/tests/test_android/test_avb.py
+++ b/test/py/tests/test_android/test_avb.py
@@ -1,6 +1,5 @@
-# Copyright (c) 2018, Linaro Limited
-#
# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018, Linaro Limited
#
# Android Verified Boot 2.0 Test
