commit adc983b4d676e4ca958067f86bec1bb02cb17950
author Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Tue Aug 27 10:13:48 2019 +0000
committer Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Wed Aug 28 13:47:44 2019 +0530
tree aee0aac131f187f6e07758aedd90ea1912a0ec4c
parent e4b8dd9b34021241cd05d5cc9d24b4ae34657830

dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdef

This can avoid build error:
The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only
defined on the platforms that select the CONFIG_FOO, while
it's not defined on platforms that do not select the
CONFIG_FOO.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

drivers/pci/pcie_fsl.c

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 4d61a46..1879d81 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -299,8 +299,9 @@
 	out_be32(&pi->piwbear, 0);
 #endif
 
-	if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434))
-		flag = 0;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+	flag = 0;
+#endif
 
 	flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
 	if (pf)
@@ -401,47 +402,47 @@
 
 	fsl_pcie_init_atmu(pcie);
 
-	if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) {
-		val_32 = 0;
-		fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
-		val_32 &= ~0x03;
-		fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
-		udelay(1);
-	}
+#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
+	val_32 = 0;
+	fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
+	val_32 &= ~0x03;
+	fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
+	udelay(1);
+#endif
 
-	if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) {
-		u16 ltssm;
-		int i;
+#ifdef CONFIG_FSL_PCIE_RESET
+	u16 ltssm;
+	int i;
 
-		if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+		/* assert PCIe reset */
+		setbits_be32(&regs->pdb_stat, 0x08000000);
+		(void)in_be32(&regs->pdb_stat);
+		udelay(1000);
+		/* clear PCIe reset */
+		clrbits_be32(&regs->pdb_stat, 0x08000000);
+		asm("sync;isync");
+		for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
+			udelay(1000);
+	} else {
+		fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
+		if (ltssm == 1) {
 			/* assert PCIe reset */
 			setbits_be32(&regs->pdb_stat, 0x08000000);
 			(void)in_be32(&regs->pdb_stat);
-			udelay(1000);
+			udelay(100);
 			/* clear PCIe reset */
 			clrbits_be32(&regs->pdb_stat, 0x08000000);
 			asm("sync;isync");
-			for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
+			for (i = 0; i < 100 &&
+			     !fsl_pcie_link_up(pcie); i++)
 				udelay(1000);
-		} else {
-			fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
-			if (ltssm == 1) {
-				/* assert PCIe reset */
-				setbits_be32(&regs->pdb_stat, 0x08000000);
-				(void)in_be32(&regs->pdb_stat);
-				udelay(100);
-				/* clear PCIe reset */
-				clrbits_be32(&regs->pdb_stat, 0x08000000);
-				asm("sync;isync");
-				for (i = 0; i < 100 &&
-				     !fsl_pcie_link_up(pcie); i++)
-					udelay(1000);
-			}
 		}
 	}
+#endif
 
-	if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) &&
-	    !fsl_pcie_link_up(pcie)) {
+#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
+	if (!fsl_pcie_link_up(pcie)) {
 		serdes_corenet_t *srds_regs;
 
 		srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
@@ -460,13 +461,15 @@
 				udelay(1000);
 		}
 	}
+#endif
 
 	/*
 	 * The Read-Only Write Enable bit defaults to 1 instead of 0.
 	 * Set to 0 to protect the read-only registers.
 	 */
-	if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815))
-		clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
+#endif
 
 	/*
 	 * Enable All Error Interrupts except