arch/riscv: add semihosting support for RISC-V
We add RISC-V semihosting based serial console for JTAG based early
debugging.
The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/lib/Kconfig b/lib/Kconfig
index b8833e0..3c5a4ab 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -73,7 +73,7 @@
config SEMIHOSTING
bool "Support semihosting"
- depends on ARM
+ depends on ARM || RISCV
help
Semihosting is a method for a target to communicate with a host
debugger. It uses special instructions which the debugger will trap
@@ -86,7 +86,7 @@
config SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails"
- depends on SEMIHOSTING && ARM64
+ depends on SEMIHOSTING && (ARM64 || RISCV)
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is
@@ -96,7 +96,7 @@
config SPL_SEMIHOSTING
bool "Support semihosting in SPL"
- depends on SPL && ARM
+ depends on SPL && (ARM || RISCV)
help
Semihosting is a method for a target to communicate with a host
debugger. It uses special instructions which the debugger will trap
@@ -109,8 +109,8 @@
config SPL_SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails in SPL"
- depends on SPL_SEMIHOSTING && ARM64
- select ARMV8_SPL_EXCEPTION_VECTORS
+ depends on SPL_SEMIHOSTING && (ARM64 || RISCV)
+ select ARMV8_SPL_EXCEPTION_VECTORS if ARM64
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is