arch/arm/dts/rk3588-u-boot.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
 */

#include "rockchip-u-boot.dtsi"
#include "rk3588s-u-boot.dtsi"

/ {
	usbdrd3_1: usbdrd3_1 {
		compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
		clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
			 <&cru ACLK_USB3OTG1>;
		clock-names = "ref", "suspend", "bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		usbdrd_dwc3_1: usb@fc400000 {
			compatible = "snps,dwc3";
			reg = <0x0 0xfc400000 0x0 0x400000>;
			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
			power-domains = <&power RK3588_PD_USB>;
			resets = <&cru SRST_A_USB3OTG1>;
			reset-names = "usb3-otg";
			dr_mode = "host";
			phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
			phy-names = "usb2-phy", "usb3-phy";
			phy_type = "utmi_wide";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
		};
	};

	usbdpphy1_grf: syscon@fd5cc000 {
		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
		reg = <0x0 0xfd5cc000 0x0 0x4000>;
	};

	usb2phy1_grf: syscon@fd5d4000 {
		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
			     "simple-mfd";
		reg = <0x0 0xfd5d4000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;

		u2phy1: usb2-phy@4000 {
			compatible = "rockchip,rk3588-usb2phy";
			reg = <0x4000 0x10>;
			interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
			resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
			reset-names = "phy", "apb";
			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
			clock-names = "phyclk";
			clock-output-names = "usb480m_phy1";
			#clock-cells = <0>;
			rockchip,usbctrl-grf = <&usb_grf>;
			status = "disabled";

			u2phy1_otg: otg-port {
				#phy-cells = <0>;
				status = "disabled";
			};
		};
	};

	usbdp_phy1: phy@fed90000 {
		compatible = "rockchip,rk3588-usbdp-phy";
		reg = <0x0 0xfed90000 0x0 0x10000>;
		rockchip,u2phy-grf = <&usb2phy1_grf>;
		rockchip,usb-grf = <&usb_grf>;
		rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
		rockchip,vo-grf = <&vo0_grf>;
		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
			 <&cru CLK_USBDP_PHY1_IMMORTAL>,
			 <&cru PCLK_USBDPPHY1>,
			 <&u2phy1>;
		clock-names = "refclk", "immortal", "pclk", "utmi";
		resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
			 <&cru SRST_USBDP_COMBO_PHY1_CMN>,
			 <&cru SRST_USBDP_COMBO_PHY1_LANE>,
			 <&cru SRST_USBDP_COMBO_PHY1_PCS>,
			 <&cru SRST_P_USBDPPHY1>;
		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
		status = "disabled";

		usbdp_phy1_dp: dp-port {
			#phy-cells = <0>;
			status = "disabled";
		};

		usbdp_phy1_u3: usb3-port {
			#phy-cells = <0>;
			status = "disabled";
		};
	};
};