mips: octeon: Misc changes required because of the newly added headers
With the newly added headers and their restructuring (which macro is
defined where), some changes in the already existing Octeon files are
necessary. This patch makes the necessary changes.
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/drivers/ram/octeon/octeon3_lmc.c b/drivers/ram/octeon/octeon3_lmc.c
index 327cdc5..349abc1 100644
--- a/drivers/ram/octeon/octeon3_lmc.c
+++ b/drivers/ram/octeon/octeon3_lmc.c
@@ -17,14 +17,8 @@
/* Random number generator stuff */
-#define CVMX_RNM_CTL_STATUS 0x0001180040000000
#define CVMX_OCT_DID_RNG 8ULL
-static u64 cvmx_build_io_address(u64 major_did, u64 sub_did)
-{
- return ((0x1ull << 48) | (major_did << 43) | (sub_did << 40));
-}
-
static u64 cvmx_rng_get_random64(void)
{
return csr_rd(cvmx_build_io_address(CVMX_OCT_DID_RNG, 0));
@@ -285,10 +279,10 @@
int node = 0;
// Force full cacheline write-backs to boost traffic
- l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+ l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
saved_dissblkdty = l2c_ctl.cn78xx.dissblkdty;
l2c_ctl.cn78xx.dissblkdty = 1;
- l2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64);
+ l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64);
if (octeon_is_cpuid(OCTEON_CN73XX) || octeon_is_cpuid(OCTEON_CNF75XX))
kbitno = 18;
@@ -489,9 +483,9 @@
}
// Restore original setting that could enable partial cacheline writes
- l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+ l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
l2c_ctl.cn78xx.dissblkdty = saved_dissblkdty;
- l2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64);
+ l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64);
return errors;
}
@@ -6315,17 +6309,17 @@
lmc_rd(priv, CVMX_LMCX_INT(if_num));
for (tad = 0; tad < num_tads; tad++) {
- l2c_wr(priv, CVMX_L2C_TADX_INT(tad),
- l2c_rd(priv, CVMX_L2C_TADX_INT(tad)));
+ l2c_wr(priv, CVMX_L2C_TADX_INT_REL(tad),
+ l2c_rd(priv, CVMX_L2C_TADX_INT_REL(tad)));
debug("%-45s : (%d) 0x%08llx\n", "CVMX_L2C_TAD_INT", tad,
- l2c_rd(priv, CVMX_L2C_TADX_INT(tad)));
+ l2c_rd(priv, CVMX_L2C_TADX_INT_REL(tad)));
}
for (mci = 0; mci < num_mcis; mci++) {
- l2c_wr(priv, CVMX_L2C_MCIX_INT(mci),
- l2c_rd(priv, CVMX_L2C_MCIX_INT(mci)));
+ l2c_wr(priv, CVMX_L2C_MCIX_INT_REL(mci),
+ l2c_rd(priv, CVMX_L2C_MCIX_INT_REL(mci)));
debug("%-45s : (%d) 0x%08llx\n", "L2C_MCI_INT", mci,
- l2c_rd(priv, CVMX_L2C_MCIX_INT(mci)));
+ l2c_rd(priv, CVMX_L2C_MCIX_INT_REL(mci)));
}
debug("%-45s : 0x%08llx\n", "LMC_INT",
@@ -9827,7 +9821,7 @@
address -= ADDRESS_HOLE;
/* Determine the LMC controllers */
- l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+ l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
/* xbits depends on number of LMCs */
xbits = cvmx_dram_get_num_lmc(priv) >> 1; // 4->2, 2->1, 1->0
diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c
index 1f75dc1..e7b61d3 100644
--- a/drivers/ram/octeon/octeon_ddr.c
+++ b/drivers/ram/octeon/octeon_ddr.c
@@ -145,7 +145,7 @@
big_ctl.u64 = 0;
big_ctl.s.maxdram = bits - 9;
big_ctl.cn61xx.disable = mode;
- l2c_wr(priv, CVMX_L2C_BIG_CTL, big_ctl.u64);
+ l2c_wr(priv, CVMX_L2C_BIG_CTL_REL, big_ctl.u64);
}
}
@@ -2274,15 +2274,15 @@
printf("Disabling L2 ECC based on disable_l2_ecc environment variable\n");
union cvmx_l2c_ctl l2c_val;
- l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+ l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
l2c_val.s.disecc = 1;
- l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);
+ l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);
} else {
union cvmx_l2c_ctl l2c_val;
- l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+ l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
l2c_val.s.disecc = 0;
- l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);
+ l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);
}
/*
@@ -2295,17 +2295,17 @@
puts("L2 index aliasing disabled.\n");
- l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+ l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
l2c_val.s.disidxalias = 1;
- l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);
+ l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);
} else {
union cvmx_l2c_ctl l2c_val;
/* Enable L2C index aliasing */
- l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+ l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
l2c_val.s.disidxalias = 0;
- l2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);
+ l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);
}
if (OCTEON_IS_OCTEON3()) {
@@ -2321,7 +2321,7 @@
u64 rdf_cnt;
char *s;
- l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);
+ l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);
/*
* It is more convenient to compute the ratio using clock
@@ -2338,7 +2338,7 @@
debug("%-45s : %d, cpu_hertz:%d, ddr_hertz:%d\n",
"EARLY FILL COUNT ", l2c_ctl.cn78xx.rdf_cnt, cpu_hertz,
ddr_hertz);
- l2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64);
+ l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64);
}
/* Check for lower DIMM socket populated */