microblaze: cache: introduce flush_cache_all()
All flush_cache() calls in microblaze code are supposed to flush the
entire instruction and data caches, so introduce flush_cache_all()
helper to handle this.
Also, provide implementations for flush_dcache_all() and
invalidate_icache_all() so that icache and dcache u-boot commands can
work.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index d5c0afd..b99b8c1 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -24,6 +24,11 @@
}
}
+void invalidate_icache_all(void)
+{
+ __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE);
+}
+
static void __flush_dcache(ulong addr, ulong size)
{
if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
@@ -38,6 +43,11 @@
}
}
+void flush_dcache_all(void)
+{
+ __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
+}
+
int dcache_status(void)
{
int i = 0;
@@ -65,7 +75,7 @@
void icache_disable(void)
{
- __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE);
+ invalidate_icache_all();
MSRCLR(0x20);
}
@@ -77,7 +87,7 @@
void dcache_disable(void)
{
- __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
+ flush_dcache_all();
MSRCLR(0x80);
}
@@ -87,3 +97,9 @@
__invalidate_icache(addr, size);
__flush_dcache(addr, size);
}
+
+void flush_cache_all(void)
+{
+ invalidate_icache_all();
+ flush_dcache_all();
+}