| commit | ad3d6e88a1a4e6aacc55b39c2bad1528100784c0 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Thu Aug 20 11:52:14 2015 +0200 |
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | Thu Oct 15 14:46:43 2015 +0200 |
| tree | 0e6da861d32909eb34dce4f2c20d30d803d0f2ea | |
| parent | 55aa0bed9803b8a5bd3e462fd712741c2e1cff1b [diff] |
armv8/mmu: Set bits marked RES1 in TCR For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1. For EL1, only bit 23 is not reserved, so only write bit 31 as 1. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>