| commit | 1a87c24fe8f4c8afc735aa50b8fc9eaa2f230c0f | [log] [tgz] |
|---|---|---|
| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | Fri Aug 26 18:30:38 2016 +0800 |
| committer | York Sun <york.sun@nxp.com> | Wed Sep 14 14:05:20 2016 -0700 |
| tree | 3977d2c8cae7f96374254e30a4125409fcb256fd | |
| parent | 77b571da3b2c2fd46d6a80e4e045f3aae392d979 [diff] |
armv8: fsl-layerscape: Update ddr erratum a008336 DDR erratum A008336 only applies to DDR controller v5.2.0. DDR controller v5.2.1 already has default 0x43b30002 in EDDRTQCR1 register for optimal performance. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>