| commit | b42b5b7a243ab3923fd80ab03f950f036b6e1329 | [log] [tgz] |
|---|---|---|
| author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | Wed Jan 30 11:19:17 2013 +0000 |
| committer | Stefano Babic <sbabic@denx.de> | Tue Feb 12 13:52:31 2013 +0100 |
| tree | 2dec05cd0a9861dd8732da17cc05bc843c2c7765 | |
| parent | 1791b1f97f71bb4f110ca851ab10479640b7bc05 [diff] |
imx: mx6q DDR3 init: Fix MR0.PPD MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>