commit b42b5b7a243ab3923fd80ab03f950f036b6e1329
author Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Wed Jan 30 11:19:17 2013 +0000
committer Stefano Babic <sbabic@denx.de> Tue Feb 12 13:52:31 2013 +0100
tree 2dec05cd0a9861dd8732da17cc05bc843c2c7765
parent 1791b1f97f71bb4f110ca851ab10479640b7bc05

imx: mx6q DDR3 init: Fix MR0.PPD

MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which
is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg

diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 51f8c35..d50858d 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -126,8 +126,8 @@
 DATA 4 0x021b001c 0x0000803B
 DATA 4 0x021b001c 0x00428031
 DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x09408038
+DATA 4 0x021b001c 0x19408030
+DATA 4 0x021b001c 0x19408038
 
 DATA 4 0x021b001c 0x04008040
 DATA 4 0x021b001c 0x04008048