Merge branch 'master' of git://git.denx.de/u-boot-video
diff --git a/.checkpatch.conf b/.checkpatch.conf
index 35167e1..d1d32fa 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -21,3 +21,7 @@
# Ignore networking block comment style
--ignore NETWORKING_BLOCK_COMMENT_STYLE
+
+# Ignore "WARNING: Prefer ether_addr_copy() over memcpy() if the Ethernet
+# addresses are __aligned(2)".
+--ignore PREFER_ETHER_ADDR_COPY
diff --git a/Kconfig b/Kconfig
index ee4e060..3ce5ba1 100644
--- a/Kconfig
+++ b/Kconfig
@@ -225,6 +225,8 @@
source "common/Kconfig"
+source "cmd/Kconfig"
+
source "dts/Kconfig"
source "net/Kconfig"
diff --git a/Makefile b/Makefile
index c9c2cbe..06996d4 100644
--- a/Makefile
+++ b/Makefile
@@ -661,6 +661,7 @@
libs-y += drivers/usb/musb-new/
libs-y += drivers/usb/phy/
libs-y += drivers/usb/ulpi/
+libs-y += cmd/
libs-y += common/
libs-$(CONFIG_API) += api/
libs-$(CONFIG_HAS_POST) += post/
diff --git a/README b/README
index ece4793..864c7cc 100644
--- a/README
+++ b/README
@@ -3712,12 +3712,6 @@
- RTS/CTS Flow control enable:
CONFIG_HWFLOW
-- Modem debug support:
- CONFIG_MODEM_SUPPORT_DEBUG
-
- Enables debugging stuff (char screen[1024], dbg())
- for modem support. Useful only with BDI2000.
-
- Interrupt support (PPC):
There are common interrupt_init() and timer_interrupt()
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 0550225..a3e14a8 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -40,7 +40,8 @@
archprepare: checkthumb
checkthumb:
- @if test "$(call cc-version)" -lt "0404"; then \
+ @if test "$(call cc-name)" = "gcc" -a \
+ "$(call cc-version)" -lt "0404"; then \
echo -n '*** Your GCC does not produce working '; \
echo 'binaries in THUMB mode.'; \
echo '*** Your board is configured for THUMB mode.'; \
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 64514b1..27a3f2f 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -18,6 +18,8 @@
PLL_BUS, /* System Bus PLL*/
PLL_USBOTG, /* OTG USB PLL */
PLL_ENET, /* ENET PLL */
+ PLL_AUDIO, /* AUDIO PLL */
+ PLL_VIDEO, /* AUDIO PLL */
};
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -204,7 +206,7 @@
}
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
- u32 div;
+ u32 div, test_div, pll_num, pll_denom;
switch (pll) {
case PLL_SYS:
@@ -227,6 +229,44 @@
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
return 25000000 * (div + (div >> 1) + 1);
+ case PLL_AUDIO:
+ div = __raw_readl(&imx_ccm->analog_pll_audio);
+ if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
+ return 0;
+ /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
+ if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
+ return MXC_HCLK;
+ pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
+ pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
+ test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
+ BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
+ div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
+ if (test_div == 3) {
+ debug("Error test_div\n");
+ return 0;
+ }
+ test_div = 1 << (2 - test_div);
+
+ return infreq * (div + pll_num / pll_denom) / test_div;
+ case PLL_VIDEO:
+ div = __raw_readl(&imx_ccm->analog_pll_video);
+ if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
+ return 0;
+ /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
+ if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
+ return MXC_HCLK;
+ pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
+ pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
+ test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
+ BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+ div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+ if (test_div == 3) {
+ debug("Error test_div\n");
+ return 0;
+ }
+ test_div = 1 << (2 - test_div);
+
+ return infreq * (div + pll_num / pll_denom) / test_div;
default:
return 0;
}
@@ -437,7 +477,7 @@
u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
- u32 freq, podf, per2_clk2_podf;
+ u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
is_cpu_type(MXC_CPU_MX6SL)) {
@@ -472,8 +512,21 @@
freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
- /* static / 2 divider */
- freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+ pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
+ switch (pmu_misc2_audio_div) {
+ case 0:
+ case 2:
+ pmu_misc2_audio_div = 1;
+ break;
+ case 1:
+ pmu_misc2_audio_div = 2;
+ break;
+ case 3:
+ pmu_misc2_audio_div = 4;
+ break;
+ }
+ freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
+ pmu_misc2_audio_div;
break;
}
}
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index c777922..1d8e470 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -130,6 +130,24 @@
writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
}
+static void imx_enet_mdio_fixup(void)
+{
+ struct iomuxc_gpr_base_regs *gpr_regs =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /*
+ * The management data input/output (MDIO) requires open-drain,
+ * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
+ * this feature. So to TO1.1, need to enable open drain by setting
+ * bits GPR0[8:7].
+ */
+
+ if (soc_rev() >= CHIP_REV_1_1) {
+ setbits_le32(&gpr_regs->gpr[0],
+ IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
+ }
+}
+
int arch_cpu_init(void)
{
init_aips();
@@ -138,6 +156,8 @@
/* Disable PDE bit of WMCR register */
imx_set_wdog_powerdown(false);
+ imx_enet_mdio_fixup();
+
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */
mxs_dma_init();
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 13e0a3d..22212c2 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -103,6 +103,97 @@
u32 analog_pfd_528_set;
u32 analog_pfd_528_clr;
u32 analog_pfd_528_tog;
+ /* PMU Memory Map/Register Definition */
+ u32 pmu_reg_1p1;
+ u32 pmu_reg_1p1_set;
+ u32 pmu_reg_1p1_clr;
+ u32 pmu_reg_1p1_tog;
+ u32 pmu_reg_3p0;
+ u32 pmu_reg_3p0_set;
+ u32 pmu_reg_3p0_clr;
+ u32 pmu_reg_3p0_tog;
+ u32 pmu_reg_2p5;
+ u32 pmu_reg_2p5_set;
+ u32 pmu_reg_2p5_clr;
+ u32 pmu_reg_2p5_tog;
+ u32 pmu_reg_core;
+ u32 pmu_reg_core_set;
+ u32 pmu_reg_core_clr;
+ u32 pmu_reg_core_tog;
+ u32 pmu_misc0;
+ u32 pmu_misc0_set;
+ u32 pmu_misc0_clr;
+ u32 pmu_misc0_tog;
+ u32 pmu_misc1;
+ u32 pmu_misc1_set;
+ u32 pmu_misc1_clr;
+ u32 pmu_misc1_tog;
+ u32 pmu_misc2;
+ u32 pmu_misc2_set;
+ u32 pmu_misc2_clr;
+ u32 pmu_misc2_tog;
+ /* TEMPMON Memory Map/Register Definition */
+ u32 tempsense0;
+ u32 tempsense0_set;
+ u32 tempsense0_clr;
+ u32 tempsense0_tog;
+ u32 tempsense1;
+ u32 tempsense1_set;
+ u32 tempsense1_clr;
+ u32 tempsense1_tog;
+ /* USB Analog Memory Map/Register Definition */
+ u32 usb1_vbus_detect;
+ u32 usb1_vbus_detect_set;
+ u32 usb1_vbus_detect_clr;
+ u32 usb1_vbus_detect_tog;
+ u32 usb1_chrg_detect;
+ u32 usb1_chrg_detect_set;
+ u32 usb1_chrg_detect_clr;
+ u32 usb1_chrg_detect_tog;
+ u32 usb1_vbus_det_stat;
+ u32 usb1_vbus_det_stat_set;
+ u32 usb1_vbus_det_stat_clr;
+ u32 usb1_vbus_det_stat_tog;
+ u32 usb1_chrg_det_stat;
+ u32 usb1_chrg_det_stat_set;
+ u32 usb1_chrg_det_stat_clr;
+ u32 usb1_chrg_det_stat_tog;
+ u32 usb1_loopback;
+ u32 usb1_loopback_set;
+ u32 usb1_loopback_clr;
+ u32 usb1_loopback_tog;
+ u32 usb1_misc;
+ u32 usb1_misc_set;
+ u32 usb1_misc_clr;
+ u32 usb1_misc_tog;
+ u32 usb2_vbus_detect;
+ u32 usb2_vbus_detect_set;
+ u32 usb2_vbus_detect_clr;
+ u32 usb2_vbus_detect_tog;
+ u32 usb2_chrg_detect;
+ u32 usb2_chrg_detect_set;
+ u32 usb2_chrg_detect_clr;
+ u32 usb2_chrg_detect_tog;
+ u32 usb2_vbus_det_stat;
+ u32 usb2_vbus_det_stat_set;
+ u32 usb2_vbus_det_stat_clr;
+ u32 usb2_vbus_det_stat_tog;
+ u32 usb2_chrg_det_stat;
+ u32 usb2_chrg_det_stat_set;
+ u32 usb2_chrg_det_stat_clr;
+ u32 usb2_chrg_det_stat_tog;
+ u32 usb2_loopback;
+ u32 usb2_loopback_set;
+ u32 usb2_loopback_clr;
+ u32 usb2_loopback_tog;
+ u32 usb2_misc;
+ u32 usb2_misc_set;
+ u32 usb2_misc_clr;
+ u32 usb2_misc_tog;
+ u32 digprog;
+ u32 reserved1[7];
+ /* For i.MX 6SoloLite */
+ u32 digprog_sololite;
};
#endif
@@ -1136,4 +1227,16 @@
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
+#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
+#define BP_PMU_MISC2_AUDIO_DIV_MSB 23
+
+#define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15)
+#define BP_PMU_MISC2_AUDIO_DIV_LSB 15
+
+#define PMU_MISC2_AUDIO_DIV(v) \
+ (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \
+ (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \
+ ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \
+ BP_PMU_MISC2_AUDIO_DIV_LSB))
+
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index e28a807..58a25c7 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -272,6 +272,8 @@
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6
+#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7)
+#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7
/* GPR1 Bit Fields */
#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u
#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0
diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h
index 7d421b3..1aec4f9 100644
--- a/arch/arm/include/asm/imx-common/dma.h
+++ b/arch/arm/include/asm/imx-common/dma.h
@@ -59,7 +59,7 @@
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
-#elif defined(CONFIG_MX6)
+#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
diff --git a/arch/arm/include/asm/imx-common/regs-apbh.h b/arch/arm/include/asm/imx-common/regs-apbh.h
index ca77436..391452c 100644
--- a/arch/arm/include/asm/imx-common/regs-apbh.h
+++ b/arch/arm/include/asm/imx-common/regs-apbh.h
@@ -96,7 +96,7 @@
mxs_reg_32(hw_apbh_version)
};
-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
@@ -275,7 +275,7 @@
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
-#elif defined(CONFIG_MX6)
+#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
@@ -391,7 +391,7 @@
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
-#if defined(CONFIG_MX6)
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#endif
diff --git a/arch/arm/include/asm/imx-common/regs-bch.h b/arch/arm/include/asm/imx-common/regs-bch.h
index 5c47783..adfbace 100644
--- a/arch/arm/include/asm/imx-common/regs-bch.h
+++ b/arch/arm/include/asm/imx-common/regs-bch.h
@@ -123,7 +123,7 @@
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
-#if defined(CONFIG_MX6)
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
#else
@@ -154,7 +154,7 @@
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
-#if defined(CONFIG_MX6)
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
#else
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c
index b4229f4..a4fa00c 100644
--- a/arch/arm/mach-tegra/ap.c
+++ b/arch/arm/mach-tegra/ap.c
@@ -8,6 +8,7 @@
/* Tegra AP (Application Processor) code */
#include <common.h>
+#include <linux/bug.h>
#include <asm/io.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/mc.h>
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index b8ac5a5..f71e342 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -10,6 +10,7 @@
#ifndef _ASM_IO_H
#define _ASM_IO_H
+#include <linux/bug.h>
#include <linux/compiler.h>
#include <linux/types.h>
diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c
index c26cc8f..b7fbd2f 100644
--- a/arch/openrisc/lib/board.c
+++ b/arch/openrisc/lib/board.c
@@ -13,6 +13,7 @@
*/
#include <common.h>
+#include <console.h>
#include <stdio_dev.h>
#include <watchdog.h>
#include <malloc.h>
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk
index 6b44a37..b0ed374 100644
--- a/arch/powerpc/config.mk
+++ b/arch/powerpc/config.mk
@@ -41,7 +41,8 @@
# that U-Boot wants.
# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
checkgcc4:
- @if test $(call cc-version) -lt 0400; then \
+ @if test "$(call cc-name)" = "gcc" -a \
+ $(call cc-version) -lt 0400; then \
echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
false; \
fi
diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c
index 4105a28..ac77ddc 100644
--- a/arch/powerpc/cpu/mpc512x/serial.c
+++ b/arch/powerpc/cpu/mpc512x/serial.c
@@ -203,18 +203,6 @@
out_8(&psc->tfdata_8, c);
}
-void serial_putc_raw_dev(unsigned int idx, const char c)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
-
- /* Wait for last character to go. */
- while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
- ;
-
- out_8(&psc->tfdata_8, c);
-}
-
void serial_puts_dev(unsigned int idx, const char *s)
{
while (*s)
diff --git a/arch/powerpc/cpu/mpc5xxx/serial.c b/arch/powerpc/cpu/mpc5xxx/serial.c
index cb5b0bf..bccdcf7 100644
--- a/arch/powerpc/cpu/mpc5xxx/serial.c
+++ b/arch/powerpc/cpu/mpc5xxx/serial.c
@@ -112,17 +112,6 @@
psc->psc_buffer_8 = c;
}
-void serial_putc_raw_dev(unsigned long dev_base, const char c)
-{
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
- /* Wait for last character to go. */
- while (!(psc->psc_status & PSC_SR_TXEMP))
- ;
-
- psc->psc_buffer_8 = c;
-}
-
-
void serial_puts_dev (unsigned long dev_base, const char *s)
{
while (*s) {
diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c
index 997aea4..5659ab8 100644
--- a/arch/powerpc/cpu/mpc83xx/law.c
+++ b/arch/powerpc/cpu/mpc83xx/law.c
@@ -19,7 +19,7 @@
if (start == 0)
start_align = 1ull << (LAW_SIZE_2G + 1);
else
- start_align = 1ull << (__ffs64(start) - 1);
+ start_align = 1ull << (__ffs64(start));
law_sz = min(start_align, sz);
law_sz_enc = __ilog2_u64(law_sz) - 1;
@@ -39,7 +39,7 @@
if (sz) {
start += law_sz;
- start_align = 1ull << (__ffs64(start) - 1);
+ start_align = 1ull << (__ffs64(start));
law_sz = min(start_align, sz);
law_sz_enc = __ilog2_u64(law_sz) - 1;
ecm = &immap->sysconf.ddrlaw[1];
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 13a7d0f..8c6b678 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -23,6 +23,10 @@
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_srio.h>
+#ifdef CONFIG_FSL_CORENET
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#endif
#include <fsl_usb.h>
#include <hwconfig.h>
#include <linux/compiler.h>
@@ -788,6 +792,13 @@
spin_table_compat = 1;
#endif
+#ifdef CONFIG_FSL_CORENET
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+#endif
+
l2cache_init();
#if defined(CONFIG_RAMBOOT_PBL)
disable_cpc_sram();
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 24baad4..bd79297 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -188,7 +188,7 @@
if (start == 0)
start_align = 1ull << (LAW_SIZE_32G + 1);
else
- start_align = 1ull << (__ffs64(start) - 1);
+ start_align = 1ull << (__ffs64(start));
law_sz = min(start_align, sz);
law_sz_enc = __ilog2_u64(law_sz) - 1;
@@ -203,7 +203,7 @@
if (sz) {
start += law_sz;
- start_align = 1ull << (__ffs64(start) - 1);
+ start_align = 1ull << (__ffs64(start));
law_sz = min(start_align, sz);
law_sz_enc = __ilog2_u64(law_sz) - 1;
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index 7299f2c..25382f9 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -50,7 +50,7 @@
mrccache_save();
#endif
- return pirq_init();
+ return 0;
}
int reserve_arch(void)
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 41e29a6..7f5087a 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -14,7 +14,8 @@
#include <pci.h>
static const struct udevice_id generic_pch_ids[] = {
- { .compatible = "intel,pch" },
+ { .compatible = "intel,pch7" },
+ { .compatible = "intel,pch9" },
{ }
};
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 381d835..6c3a748 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -688,7 +688,7 @@
}
#endif
-__weak int x86_init_cpus(void)
+static int x86_init_cpus(void)
{
#ifdef CONFIG_SMP
debug("Init additional CPUs\n");
@@ -709,8 +709,24 @@
int cpu_init_r(void)
{
- if (ll_boot_init())
- return x86_init_cpus();
+ struct udevice *dev;
+ int ret;
+
+ if (!ll_boot_init())
+ return 0;
+
+ ret = x86_init_cpus();
+ if (ret)
+ return ret;
+
+ /*
+ * Set up the northbridge, PCH and LPC if available. Note that these
+ * may have had some limited pre-relocation init if they were probed
+ * before relocation, but this is post relocation.
+ */
+ uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+ uclass_first_device(UCLASS_PCH, &dev);
+ uclass_first_device(UCLASS_LPC, &dev);
return 0;
}
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index b00ddc0..c40200b 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -12,6 +12,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <asm/cache.h>
#include <asm/control_regs.h>
#include <asm/interrupt.h>
@@ -244,6 +245,14 @@
int interrupt_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ /* Try to set up the interrupt router, but don't require one */
+ ret = uclass_first_device(UCLASS_IRQ, &dev);
+ if (ret && ret != -ENODEV)
+ return ret;
+
/*
* When running as an EFI application we are not in control of
* interrupts and should leave them alone.
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 35b29f6..0b36ace 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
@@ -82,12 +83,7 @@
slot->irq[pin - 1].bitmap = irq_router.irq_mask;
}
-__weak void cpu_irq_init(void)
-{
- return;
-}
-
-static int create_pirq_routing_table(void)
+static int create_pirq_routing_table(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
struct fdt_pci_addr addr;
@@ -97,16 +93,13 @@
struct irq_routing_table *rt;
struct irq_info *slot, *slot_base;
int irq_entries = 0;
+ int parent;
int i;
int ret;
- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IRQ_ROUTER);
- if (node < 0) {
- debug("%s: Cannot find irq router node\n", __func__);
- return -EINVAL;
- }
-
- ret = fdtdec_get_pci_addr(blob, node, FDT_PCI_SPACE_CONFIG,
+ node = dev->of_offset;
+ parent = dev->parent->of_offset;
+ ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
"reg", &addr);
if (ret)
return ret;
@@ -225,13 +218,11 @@
return 0;
}
-int pirq_init(void)
+int irq_router_common_init(struct udevice *dev)
{
int ret;
- cpu_irq_init();
-
- ret = create_pirq_routing_table();
+ ret = create_pirq_routing_table(dev);
if (ret) {
debug("Failed to create pirq routing table\n");
return ret;
@@ -243,6 +234,11 @@
return 0;
}
+int irq_router_probe(struct udevice *dev)
+{
+ return irq_router_common_init(dev);
+}
+
u32 write_pirq_routing_table(u32 addr)
{
if (!pirq_routing_table)
@@ -250,3 +246,20 @@
return copy_pirq_routing_table(addr, pirq_routing_table);
}
+
+static const struct udevice_id irq_router_ids[] = {
+ { .compatible = "intel,irq-router" },
+ { }
+};
+
+U_BOOT_DRIVER(irq_router_drv) = {
+ .name = "intel_irq",
+ .id = UCLASS_IRQ,
+ .of_match = irq_router_ids,
+ .probe = irq_router_probe,
+};
+
+UCLASS_DRIVER(irq) = {
+ .id = UCLASS_IRQ,
+ .name = "irq",
+};
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 0c7efae..45ef141 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -7,7 +7,6 @@
obj-y += bd82x6x.o
obj-y += car.o
obj-y += cpu.o
-obj-y += early_init.o
obj-y += early_me.o
obj-y += gma.o
obj-y += lpc.o
@@ -15,10 +14,6 @@
obj-y += model_206ax.o
obj-y += microcode_intel.o
obj-y += northbridge.o
-obj-y += pch.o
-obj-y += pci.o
obj-y += report_platform.o
obj-y += sata.o
obj-y += sdram.o
-obj-y += usb_ehci.o
-obj-y += usb_xhci.o
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 434dfd6..2b172d4 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -3,12 +3,15 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
+#include <pch.h>
+#include <syscon.h>
+#include <asm/cpu.h>
+#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/pci.h>
#include <asm/arch/bd82x6x.h>
@@ -16,106 +19,198 @@
#include <asm/arch/pch.h>
#include <asm/arch/sandybridge.h>
-void bd82x6x_pci_init(pci_dev_t dev)
+#define BIOS_CTRL 0xdc
+
+static int pch_revision_id = -1;
+static int pch_type = -1;
+
+/**
+ * pch_silicon_revision() - Read silicon revision ID from the PCH
+ *
+ * @dev: PCH device
+ * @return silicon revision ID
+ */
+static int pch_silicon_revision(struct udevice *dev)
{
- u16 reg16;
- u8 reg8;
+ u8 val;
- debug("bd82x6x PCI init.\n");
- /* Enable Bus Master */
- reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
- reg16 |= PCI_COMMAND_MASTER;
- x86_pci_write_config16(dev, PCI_COMMAND, reg16);
+ if (pch_revision_id < 0) {
+ dm_pci_read_config8(dev, PCI_REVISION_ID, &val);
+ pch_revision_id = val;
+ }
- /* This device has no interrupt */
- x86_pci_write_config8(dev, INTR, 0xff);
+ return pch_revision_id;
+}
- /* disable parity error response and SERR */
- reg16 = x86_pci_read_config16(dev, BCTRL);
- reg16 &= ~(1 << 0);
- reg16 &= ~(1 << 1);
- x86_pci_write_config16(dev, BCTRL, reg16);
+int pch_silicon_type(struct udevice *dev)
+{
+ u8 val;
- /* Master Latency Count must be set to 0x04! */
- reg8 = x86_pci_read_config8(dev, SMLT);
- reg8 &= 0x07;
- reg8 |= (0x04 << 3);
- x86_pci_write_config8(dev, SMLT, reg8);
+ if (pch_type < 0) {
+ dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val);
+ pch_type = val;
+ }
- /* Will this improve throughput of bus masters? */
- x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+ return pch_type;
+}
- /* Clear errors in status registers */
- reg16 = x86_pci_read_config16(dev, PSTS);
- /* reg16 |= 0xf900; */
- x86_pci_write_config16(dev, PSTS, reg16);
+/**
+ * pch_silicon_supported() - Check if a certain revision is supported
+ *
+ * @dev: PCH device
+ * @type: PCH type
+ * @rev: Minimum required resion
+ * @return 0 if not supported, 1 if supported
+ */
+static int pch_silicon_supported(struct udevice *dev, int type, int rev)
+{
+ int cur_type = pch_silicon_type(dev);
+ int cur_rev = pch_silicon_revision(dev);
- reg16 = x86_pci_read_config16(dev, SECSTS);
- /* reg16 |= 0xf900; */
- x86_pci_write_config16(dev, SECSTS, reg16);
+ switch (type) {
+ case PCH_TYPE_CPT:
+ /* CougarPoint minimum revision */
+ if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
+ return 1;
+ /* PantherPoint any revision */
+ if (cur_type == PCH_TYPE_PPT)
+ return 1;
+ break;
+
+ case PCH_TYPE_PPT:
+ /* PantherPoint minimum revision */
+ if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
+ return 1;
+ break;
+ }
+
+ return 0;
+}
+
+#define IOBP_RETRY 1000
+static inline int iobp_poll(void)
+{
+ unsigned try = IOBP_RETRY;
+ u32 data;
+
+ while (try--) {
+ data = readl(RCB_REG(IOBPS));
+ if ((data & 1) == 0)
+ return 1;
+ udelay(10);
+ }
+
+ printf("IOBP timeout\n");
+ return 0;
+}
+
+void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
+ u32 orvalue)
+{
+ u32 data;
+
+ /* Set the address */
+ writel(address, RCB_REG(IOBPIRI));
+
+ /* READ OPCODE */
+ if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
+ writel(IOBPS_RW_BX, RCB_REG(IOBPS));
+ else
+ writel(IOBPS_READ_AX, RCB_REG(IOBPS));
+ if (!iobp_poll())
+ return;
+
+ /* Read IOBP data */
+ data = readl(RCB_REG(IOBPD));
+ if (!iobp_poll())
+ return;
+
+ /* Check for successful transaction */
+ if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
+ printf("IOBP read 0x%08x failed\n", address);
+ return;
+ }
+
+ /* Update the data */
+ data &= andvalue;
+ data |= orvalue;
+
+ /* WRITE OPCODE */
+ if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
+ writel(IOBPS_RW_BX, RCB_REG(IOBPS));
+ else
+ writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
+ if (!iobp_poll())
+ return;
+
+ /* Write IOBP data */
+ writel(data, RCB_REG(IOBPD));
+ if (!iobp_poll())
+ return;
}
static int bd82x6x_probe(struct udevice *dev)
{
- const void *blob = gd->fdt_blob;
- struct pci_controller *hose;
- struct x86_cpu_priv *cpu;
- int sata_node, gma_node;
+ struct udevice *gma_dev;
int ret;
- hose = pci_bus_to_hose(0);
- lpc_enable(PCH_LPC_DEV);
- lpc_init(hose, PCH_LPC_DEV);
- sata_node = fdtdec_next_compatible(blob, 0,
- COMPAT_INTEL_PANTHERPOINT_AHCI);
- if (sata_node < 0) {
- debug("%s: Cannot find SATA node\n", __func__);
- return -EINVAL;
- }
- bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
- bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
- bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
+ if (!(gd->flags & GD_FLG_RELOC))
+ return 0;
- cpu = calloc(1, sizeof(*cpu));
- if (!cpu)
- return -ENOMEM;
- model_206ax_init(cpu);
+ /* Cause the SATA device to do its init */
+ uclass_first_device(UCLASS_DISK, &dev);
- gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
- if (gma_node < 0) {
- debug("%s: Cannot find GMA node\n", __func__);
- return -EINVAL;
- }
- ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev);
+ ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev);
if (ret)
return ret;
- ret = gma_func0_init(dev, blob, gma_node);
+ ret = gma_func0_init(gma_dev);
if (ret)
return ret;
return 0;
}
-int bd82x6x_init(void)
+static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
{
- const void *blob = gd->fdt_blob;
- int sata_node;
+ u32 rcba;
- sata_node = fdtdec_next_compatible(blob, 0,
- COMPAT_INTEL_PANTHERPOINT_AHCI);
- if (sata_node < 0) {
- debug("%s: Cannot find SATA node\n", __func__);
- return -EINVAL;
- }
-
- bd82x6x_pci_init(PCH_DEV);
- bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
- northbridge_enable(PCH_DEV);
- northbridge_init(PCH_DEV);
+ dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+ /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
+ rcba = rcba & 0xffffc000;
+ *sbasep = rcba + 0x3800;
return 0;
}
+static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
+{
+ return PCHV_9;
+}
+
+static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
+{
+ uint8_t bios_cntl;
+
+ /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
+ dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
+ if (protect) {
+ bios_cntl &= ~BIOS_CTRL_BIOSWE;
+ bios_cntl |= BIT(5);
+ } else {
+ bios_cntl |= BIOS_CTRL_BIOSWE;
+ bios_cntl &= ~BIT(5);
+ }
+ dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
+
+ return 0;
+}
+
+static const struct pch_ops bd82x6x_pch_ops = {
+ .get_sbase = bd82x6x_pch_get_sbase,
+ .get_version = bd82x6x_pch_get_version,
+ .set_spi_protect = bd82x6x_set_spi_protect,
+};
+
static const struct udevice_id bd82x6x_ids[] = {
{ .compatible = "intel,bd82x6x" },
{ }
@@ -126,4 +221,5 @@
.id = UCLASS_PCH,
.of_match = bd82x6x_ids,
.probe = bd82x6x_probe,
+ .ops = &bd82x6x_pch_ops,
};
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 343bfb4..948833c 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -15,6 +15,7 @@
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
+#include <pch.h>
#include <asm/cpu.h>
#include <asm/io.h>
#include <asm/lapic.h>
@@ -30,26 +31,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev)
-{
- /* Enable port 80 POST on LPC */
- pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
- clrbits_le32(RCB_REG(GCS), 4);
-}
-
-/*
- * Enable Prefetching and Caching.
- */
-static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev)
-{
- u8 reg8;
-
- pci_hose_read_config_byte(hose, dev, 0xdc, ®8);
- reg8 &= ~(3 << 2);
- reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
- pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
-}
-
static int set_flex_ratio_to_tdp_nominal(void)
{
msr_t flex_ratio, msr;
@@ -99,22 +80,6 @@
return -EINVAL;
}
-static void set_spi_speed(void)
-{
- u32 fdod;
-
- /* Observe SPI Descriptor Component Section 0 */
- writel(0x1000, RCB_REG(SPI_DESC_COMP0));
-
- /* Extract the1 Write/Erase SPI Frequency from descriptor */
- fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
- fdod >>= 24;
- fdod &= 7;
-
- /* Set Software Sequence frequency to match */
- clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
-}
-
int arch_cpu_init(void)
{
post_code(POST_CPU_INIT);
@@ -124,10 +89,8 @@
int arch_cpu_init_dm(void)
{
- const void *blob = gd->fdt_blob;
struct pci_controller *hose;
- struct udevice *bus;
- int node;
+ struct udevice *bus, *dev;
int ret;
post_code(0x70);
@@ -141,19 +104,9 @@
/* TODO(sjg@chromium.org): Get rid of gd->hose */
gd->hose = hose;
- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
- if (node < 0)
- return -ENOENT;
- ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
- if (ret)
- return ret;
-
- enable_spi_prefetch(hose, PCH_LPC_DEV);
-
- /* This is already done in start.S, but let's do it in C */
- enable_port80_on_lpc(hose, PCH_LPC_DEV);
-
- set_spi_speed();
+ ret = uclass_first_device(UCLASS_LPC, &dev);
+ if (!dev)
+ return -ENODEV;
/*
* We should do as little as possible before the serial console is
@@ -167,41 +120,6 @@
return 0;
}
-static int enable_smbus(void)
-{
- pci_dev_t dev;
- uint16_t value;
-
- /* Set the SMBus device statically. */
- dev = PCI_BDF(0x0, 0x1f, 0x3);
-
- /* Check to make sure we've got the right device. */
- value = x86_pci_read_config16(dev, 0x0);
- if (value != 0x8086) {
- printf("SMBus controller not found\n");
- return -ENOSYS;
- }
-
- /* Set SMBus I/O base. */
- x86_pci_write_config32(dev, SMB_BASE,
- SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
-
- /* Set SMBus enable. */
- x86_pci_write_config8(dev, HOSTC, HST_EN);
-
- /* Set SMBus I/O space enable. */
- x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
-
- /* Disable interrupt generation. */
- outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-
- /* Clear any lingering errors, so transactions can run. */
- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- debug("SMBus controller enabled\n");
-
- return 0;
-}
-
#define PCH_EHCI0_TEMP_BAR0 0xe8000000
#define PCH_EHCI1_TEMP_BAR0 0xe8000400
#define PCH_XHCI_TEMP_BAR0 0xe8001000
@@ -215,33 +133,33 @@
*
* This is used to speed up the resume path.
*/
-static void enable_usb_bar(void)
+static void enable_usb_bar(struct udevice *bus)
{
pci_dev_t usb0 = PCH_EHCI1_DEV;
pci_dev_t usb1 = PCH_EHCI2_DEV;
pci_dev_t usb3 = PCH_XHCI_DEV;
- u32 cmd;
+ ulong cmd;
/* USB Controller 1 */
- x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
- PCH_EHCI0_TEMP_BAR0);
- cmd = x86_pci_read_config32(usb0, PCI_COMMAND);
+ pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0,
+ PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32);
+ pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- x86_pci_write_config32(usb0, PCI_COMMAND, cmd);
+ pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32);
- /* USB Controller 1 */
- x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
- PCH_EHCI1_TEMP_BAR0);
- cmd = x86_pci_read_config32(usb1, PCI_COMMAND);
+ /* USB Controller 2 */
+ pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0,
+ PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32);
+ pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- x86_pci_write_config32(usb1, PCI_COMMAND, cmd);
+ pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32);
- /* USB3 Controller */
- x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
- PCH_XHCI_TEMP_BAR0);
- cmd = x86_pci_read_config32(usb3, PCI_COMMAND);
+ /* USB3 Controller 1 */
+ pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0,
+ PCH_XHCI_TEMP_BAR0, PCI_SIZE_32);
+ pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- x86_pci_write_config32(usb3, PCI_COMMAND, cmd);
+ pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
}
static int report_bist_failure(void)
@@ -259,6 +177,7 @@
{
enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
char processor_name[CPU_MAX_NAME_LEN];
+ struct udevice *dev, *lpc;
const char *name;
uint32_t pm1_cnt;
uint16_t pm1_sts;
@@ -289,7 +208,16 @@
}
/* Early chipset init required before RAM init can work */
- sandybridge_early_init(SANDYBRIDGE_MOBILE);
+ uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+
+ ret = uclass_first_device(UCLASS_LPC, &lpc);
+ if (ret)
+ return ret;
+ if (!dev)
+ return -ENODEV;
+
+ /* Cause the SATA device to do its early init */
+ uclass_first_device(UCLASS_DISK, &dev);
/* Check PM1_STS[15] to see if we are waking from Sx */
pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
@@ -308,20 +236,18 @@
post_code(POST_EARLY_INIT);
/* Enable SPD ROMs and DDR-III DRAM */
- ret = enable_smbus();
+ ret = uclass_first_device(UCLASS_I2C, &dev);
if (ret)
return ret;
+ if (!dev)
+ return -ENODEV;
/* Prepare USB controller early in S3 resume */
if (boot_mode == PEI_BOOT_RESUME)
- enable_usb_bar();
+ enable_usb_bar(pci_get_controller(lpc->parent));
gd->arch.pei_boot_mode = boot_mode;
- /* TODO: Move this to the board or driver */
- x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
- x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
/* Print processor name */
name = cpu_get_name(processor_name);
printf("CPU: %s\n", name);
diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c
deleted file mode 100644
index 9ca008e..0000000
--- a/arch/x86/cpu/ivybridge/early_init.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * From Coreboot
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2011 Google Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-#include <asm/arch/sandybridge.h>
-
-static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
-{
- /* Setting up Southbridge. In the northbridge code. */
- debug("Setting up static southbridge registers\n");
- x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
-
- x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
- x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
-
- debug("Disabling watchdog reboot\n");
- setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
- outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
-
- /* Set up all hardcoded northbridge BARs */
- debug("Setting up static registers\n");
- x86_pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
- x86_pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
- x86_pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
- x86_pci_write_config32(pch_dev, MCHBAR + 4,
- (0LL + DEFAULT_MCHBAR) >> 32);
- /* 64MB - busses 0-63 */
- x86_pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
- x86_pci_write_config32(pch_dev, PCIEXBAR + 4,
- (0LL + DEFAULT_PCIEXBAR) >> 32);
- x86_pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
- x86_pci_write_config32(pch_dev, DMIBAR + 4,
- (0LL + DEFAULT_DMIBAR) >> 32);
-
- /* Set C0000-FFFFF to access RAM on both reads and writes */
- x86_pci_write_config8(pch_dev, PAM0, 0x30);
- x86_pci_write_config8(pch_dev, PAM1, 0x33);
- x86_pci_write_config8(pch_dev, PAM2, 0x33);
- x86_pci_write_config8(pch_dev, PAM3, 0x33);
- x86_pci_write_config8(pch_dev, PAM4, 0x33);
- x86_pci_write_config8(pch_dev, PAM5, 0x33);
- x86_pci_write_config8(pch_dev, PAM6, 0x33);
-}
-
-static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
-{
- u32 reg32;
- u16 reg16;
- u8 reg8;
-
- reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID);
- switch (reg16) {
- case 0x0102: /* GT1 Desktop */
- case 0x0106: /* GT1 Mobile */
- case 0x010a: /* GT1 Server */
- case 0x0112: /* GT2 Desktop */
- case 0x0116: /* GT2 Mobile */
- case 0x0122: /* GT2 Desktop >=1.3GHz */
- case 0x0126: /* GT2 Mobile >=1.3GHz */
- case 0x0156: /* IvyBridge */
- case 0x0166: /* IvyBridge */
- break;
- default:
- debug("Graphics not supported by this CPU/chipset\n");
- return;
- }
-
- debug("Initialising Graphics\n");
-
- /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
- reg16 = x86_pci_read_config16(pch_dev, GGC);
- reg16 &= ~0x00f8;
- reg16 |= 1 << 3;
- /* Program GTT memory by setting GGC[9:8] = 2MB */
- reg16 &= ~0x0300;
- reg16 |= 2 << 8;
- /* Enable VGA decode */
- reg16 &= ~0x0002;
- x86_pci_write_config16(pch_dev, GGC, reg16);
-
- /* Enable 256MB aperture */
- reg8 = x86_pci_read_config8(video_dev, MSAC);
- reg8 &= ~0x06;
- reg8 |= 0x02;
- x86_pci_write_config8(video_dev, MSAC, reg8);
-
- /* Erratum workarounds */
- reg32 = readl(MCHBAR_REG(0x5f00));
- reg32 |= (1 << 9) | (1 << 10);
- writel(reg32, MCHBAR_REG(0x5f00));
-
- /* Enable SA Clock Gating */
- reg32 = readl(MCHBAR_REG(0x5f00));
- writel(reg32 | 1, MCHBAR_REG(0x5f00));
-
- /* GPU RC6 workaround for sighting 366252 */
- reg32 = readl(MCHBAR_REG(0x5d14));
- reg32 |= (1 << 31);
- writel(reg32, MCHBAR_REG(0x5d14));
-
- /* VLW */
- reg32 = readl(MCHBAR_REG(0x6120));
- reg32 &= ~(1 << 0);
- writel(reg32, MCHBAR_REG(0x6120));
-
- reg32 = readl(MCHBAR_REG(0x5418));
- reg32 |= (1 << 4) | (1 << 5);
- writel(reg32, MCHBAR_REG(0x5418));
-}
-
-void sandybridge_early_init(int chipset_type)
-{
- pci_dev_t pch_dev = PCH_DEV;
- pci_dev_t video_dev = PCH_VIDEO_DEV;
- pci_dev_t lpc_dev = PCH_LPC_DEV;
- u32 capid0_a;
- u8 reg8;
-
- /* Device ID Override Enable should be done very early */
- capid0_a = x86_pci_read_config32(pch_dev, 0xe4);
- if (capid0_a & (1 << 10)) {
- reg8 = x86_pci_read_config8(pch_dev, 0xf3);
- reg8 &= ~7; /* Clear 2:0 */
-
- if (chipset_type == SANDYBRIDGE_MOBILE)
- reg8 |= 1; /* Set bit 0 */
-
- x86_pci_write_config8(pch_dev, 0xf3, reg8);
- }
-
- /* Setup all BARs required for early PCIe and raminit */
- sandybridge_setup_bars(pch_dev, lpc_dev);
-
- /* Device Enable */
- x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
-
- sandybridge_setup_graphics(pch_dev, video_dev);
-}
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
index 711470f..b1df77d 100644
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -7,8 +7,10 @@
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <asm/pci.h>
+#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/arch/me.h>
#include <asm/arch/pch.h>
@@ -25,33 +27,36 @@
[ME_HFS_ACK_CONTINUE] = "Continue to boot"
};
-static inline void pci_read_dword_ptr(void *ptr, int offset)
+static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
+ int offset)
{
u32 dword;
- dword = x86_pci_read_config32(PCH_ME_DEV, offset);
+ dm_pci_read_config32(me_dev, offset, &dword);
memcpy(ptr, &dword, sizeof(dword));
}
-static inline void pci_write_dword_ptr(void *ptr, int offset)
+static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
+ int offset)
{
u32 dword = 0;
+
memcpy(&dword, ptr, sizeof(dword));
- x86_pci_write_config32(PCH_ME_DEV, offset, dword);
+ dm_pci_write_config32(me_dev, offset, dword);
}
-void intel_early_me_status(void)
+void intel_early_me_status(struct udevice *me_dev)
{
struct me_hfs hfs;
struct me_gmes gmes;
- pci_read_dword_ptr(&hfs, PCI_ME_HFS);
- pci_read_dword_ptr(&gmes, PCI_ME_GMES);
+ pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
+ pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
intel_me_status(&hfs, &gmes);
}
-int intel_early_me_init(void)
+int intel_early_me_init(struct udevice *me_dev)
{
int count;
struct me_uma uma;
@@ -61,7 +66,7 @@
/* Wait for ME UMA SIZE VALID bit to be set */
for (count = ME_RETRY; count > 0; --count) {
- pci_read_dword_ptr(&uma, PCI_ME_UMA);
+ pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
if (uma.valid)
break;
udelay(ME_DELAY);
@@ -72,7 +77,7 @@
}
/* Check for valid firmware */
- pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+ pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
if (hfs.fpt_bad) {
printf("WARNING: ME has bad firmware\n");
return -EBADF;
@@ -83,11 +88,11 @@
return 0;
}
-int intel_early_me_uma_size(void)
+int intel_early_me_uma_size(struct udevice *me_dev)
{
struct me_uma uma;
- pci_read_dword_ptr(&uma, PCI_ME_UMA);
+ pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
if (uma.valid) {
debug("ME: Requested %uMB UMA\n", uma.size);
return uma.size;
@@ -97,11 +102,11 @@
return -EINVAL;
}
-static inline void set_global_reset(int enable)
+static inline void set_global_reset(struct udevice *dev, int enable)
{
u32 etr3;
- etr3 = x86_pci_read_config32(PCH_LPC_DEV, ETR3);
+ dm_pci_read_config32(dev, ETR3, &etr3);
/* Clear CF9 Without Resume Well Reset Enable */
etr3 &= ~ETR3_CWORWRE;
@@ -112,10 +117,11 @@
else
etr3 &= ~ETR3_CF9GR;
- x86_pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+ dm_pci_write_config32(dev, ETR3, etr3);
}
-int intel_early_me_init_done(u8 status)
+int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
+ uint status)
{
int count;
u32 mebase_l, mebase_h;
@@ -126,8 +132,8 @@
};
/* MEBASE from MESEG_BASE[35:20] */
- mebase_l = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L);
- mebase_h = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H);
+ dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l);
+ dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h);
mebase_h &= 0xf;
did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
@@ -135,25 +141,25 @@
debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
status, did.uma_base);
- pci_write_dword_ptr(&did, PCI_ME_H_GS);
+ pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS);
/* Must wait for ME acknowledgement */
for (count = ME_RETRY; count > 0; --count) {
- pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+ pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
if (hfs.bios_msg_ack)
break;
udelay(ME_DELAY);
}
if (!count) {
printf("ERROR: ME failed to respond\n");
- return -1;
+ return -ETIMEDOUT;
}
/* Return the requested BIOS action */
debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
/* Check status after acknowledgement */
- intel_early_me_status();
+ intel_early_me_status(me_dev);
switch (hfs.ack_data) {
case ME_HFS_ACK_CONTINUE:
@@ -161,17 +167,17 @@
return 0;
case ME_HFS_ACK_RESET:
/* Non-power cycle reset */
- set_global_reset(0);
+ set_global_reset(dev, 0);
reset_cpu(0);
break;
case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */
- set_global_reset(0);
+ set_global_reset(dev, 0);
x86_full_reset();
break;
case ME_HFS_ACK_GBL_RESET:
/* Global reset */
- set_global_reset(1);
+ set_global_reset(dev, 1);
x86_full_reset();
break;
case ME_HFS_ACK_S3:
@@ -180,5 +186,17 @@
break;
}
- return -1;
+ return -EINVAL;
}
+
+static const struct udevice_id ivybridge_syscon_ids[] = {
+ { .compatible = "intel,me", .data = X86_SYSCON_ME },
+ { .compatible = "intel,gma", .data = X86_SYSCON_GMA },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_intel_me) = {
+ .name = "intel_me_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = ivybridge_syscon_ids,
+};
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 85a09c64..3b6291e 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <bios_emul.h>
+#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <pci_rom.h>
@@ -352,14 +353,13 @@
return 0;
}
-static int gma_pm_init_pre_vbios(void *gtt_bar)
+static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
{
u32 reg32;
- debug("GT Power Management Init, silicon = %#x\n",
- bridge_silicon_revision());
+ debug("GT Power Management Init, silicon = %#x\n", rev);
- if (bridge_silicon_revision() < IVB_STEP_C0) {
+ if (rev < IVB_STEP_C0) {
/* 1: Enable force wake */
gtt_write(gtt_bar, 0xa18c, 0x00000001);
gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
@@ -369,14 +369,14 @@
gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
}
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
reg32 = gtt_read(gtt_bar, 0x42004);
reg32 |= (1 << 14) | (1 << 15);
gtt_write(gtt_bar, 0x42004, reg32);
}
- if (bridge_silicon_revision() >= IVB_STEP_A0) {
+ if (rev >= IVB_STEP_A0) {
/* Display Reset Acknowledge Settings */
reg32 = gtt_read(gtt_bar, 0x45010);
reg32 |= (1 << 1) | (1 << 0);
@@ -385,7 +385,7 @@
/* 2: Get GT SKU from GTT+0x911c[13] */
reg32 = gtt_read(gtt_bar, 0x911c);
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
if (reg32 & (1 << 13)) {
debug("SNB GT1 Power Meter Weights\n");
gtt_write_powermeter(gtt_bar, snb_pm_gt1);
@@ -434,13 +434,13 @@
reg32 = gtt_read(gtt_bar, 0xa180);
reg32 |= (1 << 26) | (1 << 31);
/* (bit 20=1 for SNB step D1+ / IVB A0+) */
- if (bridge_silicon_revision() >= SNB_STEP_D1)
+ if (rev >= SNB_STEP_D1)
reg32 |= (1 << 20);
gtt_write(gtt_bar, 0xa180, reg32);
/* 6a: for SnB step D2+ only */
- if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
- (bridge_silicon_revision() >= SNB_STEP_D2)) {
+ if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
+ (rev >= SNB_STEP_D2)) {
reg32 = gtt_read(gtt_bar, 0x9400);
reg32 |= (1 << 7);
gtt_write(gtt_bar, 0x9400, reg32);
@@ -452,7 +452,7 @@
gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
}
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
reg32 = gtt_read(gtt_bar, 0x907c);
reg32 |= (1 << 16);
gtt_write(gtt_bar, 0x907c, reg32);
@@ -504,7 +504,7 @@
gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
/* 11a: Enable Render Standby (RC6) */
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
/*
* IvyBridge should also support DeepRenderStandby.
*
@@ -538,14 +538,16 @@
return 0;
}
-int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node)
+int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
{
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
u32 reg32, cycle_delay;
debug("GT Power Management Init (post VBIOS)\n");
/* 15: Deassert Force Wake */
- if (bridge_silicon_revision() < IVB_STEP_C0) {
+ if (rev < IVB_STEP_C0) {
gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
} else {
@@ -728,15 +730,93 @@
return res;
}
-int gma_func0_init(struct udevice *dev, const void *blob, int node)
+void sandybridge_setup_graphics(struct udevice *dev, struct udevice *video_dev)
+{
+ u32 reg32;
+ u16 reg16;
+ u8 reg8;
+
+ dm_pci_read_config16(video_dev, PCI_DEVICE_ID, ®16);
+ switch (reg16) {
+ case 0x0102: /* GT1 Desktop */
+ case 0x0106: /* GT1 Mobile */
+ case 0x010a: /* GT1 Server */
+ case 0x0112: /* GT2 Desktop */
+ case 0x0116: /* GT2 Mobile */
+ case 0x0122: /* GT2 Desktop >=1.3GHz */
+ case 0x0126: /* GT2 Mobile >=1.3GHz */
+ case 0x0156: /* IvyBridge */
+ case 0x0166: /* IvyBridge */
+ break;
+ default:
+ debug("Graphics not supported by this CPU/chipset\n");
+ return;
+ }
+
+ debug("Initialising Graphics\n");
+
+ /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
+ dm_pci_read_config16(dev, GGC, ®16);
+ reg16 &= ~0x00f8;
+ reg16 |= 1 << 3;
+ /* Program GTT memory by setting GGC[9:8] = 2MB */
+ reg16 &= ~0x0300;
+ reg16 |= 2 << 8;
+ /* Enable VGA decode */
+ reg16 &= ~0x0002;
+ dm_pci_write_config16(dev, GGC, reg16);
+
+ /* Enable 256MB aperture */
+ dm_pci_read_config8(video_dev, MSAC, ®8);
+ reg8 &= ~0x06;
+ reg8 |= 0x02;
+ dm_pci_write_config8(video_dev, MSAC, reg8);
+
+ /* Erratum workarounds */
+ reg32 = readl(MCHBAR_REG(0x5f00));
+ reg32 |= (1 << 9) | (1 << 10);
+ writel(reg32, MCHBAR_REG(0x5f00));
+
+ /* Enable SA Clock Gating */
+ reg32 = readl(MCHBAR_REG(0x5f00));
+ writel(reg32 | 1, MCHBAR_REG(0x5f00));
+
+ /* GPU RC6 workaround for sighting 366252 */
+ reg32 = readl(MCHBAR_REG(0x5d14));
+ reg32 |= (1 << 31);
+ writel(reg32, MCHBAR_REG(0x5d14));
+
+ /* VLW */
+ reg32 = readl(MCHBAR_REG(0x6120));
+ reg32 &= ~(1 << 0);
+ writel(reg32, MCHBAR_REG(0x6120));
+
+ reg32 = readl(MCHBAR_REG(0x5418));
+ reg32 |= (1 << 4) | (1 << 5);
+ writel(reg32, MCHBAR_REG(0x5418));
+}
+
+int gma_func0_init(struct udevice *dev)
{
#ifdef CONFIG_VIDEO
ulong start;
#endif
+ struct udevice *nbridge;
void *gtt_bar;
ulong base;
u32 reg32;
int ret;
+ int rev;
+
+ /* Enable PCH Display Port */
+ writew(0x0010, RCB_REG(DISPBDF));
+ setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
+
+ ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge);
+ if (!nbridge)
+ return -ENODEV;
+ rev = bridge_silicon_revision(nbridge);
+ sandybridge_setup_graphics(nbridge, dev);
/* IGD needs to be Bus Master */
dm_pci_read_config32(dev, PCI_COMMAND, ®32);
@@ -750,7 +830,7 @@
gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
debug("GT bar %p\n", gtt_bar);
- ret = gma_pm_init_pre_vbios(gtt_bar);
+ ret = gma_pm_init_pre_vbios(gtt_bar, rev);
if (ret)
return ret;
@@ -761,7 +841,7 @@
debug("BIOS ran in %lums\n", get_timer(start));
#endif
/* Post VBIOS init */
- ret = gma_pm_init_post_vbios(gtt_bar, blob, node);
+ ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
if (ret)
return ret;
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index af5d4a8..9ab5ed3 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -24,13 +24,13 @@
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
#define TEST_SMM_FLASH_LOCKDOWN 0
-static int pch_enable_apic(pci_dev_t dev)
+static int pch_enable_apic(struct udevice *pch)
{
u32 reg32;
int i;
/* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
- x86_pci_write_config8(dev, ACPI_CNTL, 0x80);
+ dm_pci_write_config8(pch, ACPI_CNTL, 0x80);
writel(0, IO_APIC_INDEX);
writel(1 << 25, IO_APIC_DATA);
@@ -66,36 +66,36 @@
return 0;
}
-static void pch_enable_serial_irqs(pci_dev_t dev)
+static void pch_enable_serial_irqs(struct udevice *pch)
{
u32 value;
/* Set packet length and toggle silent mode bit for one frame. */
value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
- x86_pci_write_config8(dev, SERIRQ_CNTL, value);
+ dm_pci_write_config8(pch, SERIRQ_CNTL, value);
#else
- x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
+ dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6));
#endif
}
-static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
+static int pch_pirq_init(struct udevice *pch)
{
uint8_t route[8], *ptr;
- if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route,
- sizeof(route)))
+ if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
+ "intel,pirq-routing", route, sizeof(route)))
return -EINVAL;
ptr = route;
- x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++);
- x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++);
- x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++);
- x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++);
+ dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++);
+ dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++);
+ dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++);
+ dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++);
- x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++);
- x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++);
- x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++);
- x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++);
+ dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++);
+ dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++);
+ dm_pci_write_config8(pch, PIRQG_ROUT, *ptr++);
+ dm_pci_write_config8(pch, PIRQH_ROUT, *ptr++);
/*
* TODO(sjg@chromium.org): U-Boot does not set up the interrupts
@@ -104,26 +104,28 @@
return 0;
}
-static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
+static int pch_gpi_routing(struct udevice *pch)
{
u8 route[16];
u32 reg;
int gpi;
- if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route,
- sizeof(route)))
+ if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
+ "intel,gpi-routing", route, sizeof(route)))
return -EINVAL;
for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
reg |= route[gpi] << (gpi * 2);
- x86_pci_write_config32(dev, 0xb8, reg);
+ dm_pci_write_config32(pch, 0xb8, reg);
return 0;
}
-static int pch_power_options(const void *blob, int node, pci_dev_t dev)
+static int pch_power_options(struct udevice *pch)
{
+ const void *blob = gd->fdt_blob;
+ int node = pch->of_offset;
u8 reg8;
u16 reg16, pmbase;
u32 reg32;
@@ -142,7 +144,7 @@
*/
pwr_on = MAINBOARD_POWER_ON;
- reg16 = x86_pci_read_config16(dev, GEN_PMCON_3);
+ dm_pci_read_config16(pch, GEN_PMCON_3, ®16);
reg16 &= 0xfffe;
switch (pwr_on) {
case MAINBOARD_POWER_OFF:
@@ -169,7 +171,7 @@
reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
- x86_pci_write_config16(dev, GEN_PMCON_3, reg16);
+ dm_pci_write_config16(pch, GEN_PMCON_3, reg16);
debug("Set power %s after power failure.\n", state);
/* Set up NMI on errors. */
@@ -193,21 +195,22 @@
outb(reg8, 0x70);
/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
- reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
+ dm_pci_read_config16(pch, GEN_PMCON_1, ®16);
reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
#if DEBUG_PERIODIC_SMIS
/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
reg16 |= (3 << 0); /* Periodic SMI every 8s */
#endif
- x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
+ dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
/* Set the board's GPI routing. */
- ret = pch_gpi_routing(blob, node, dev);
+ ret = pch_gpi_routing(pch);
if (ret)
return ret;
- pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe;
+ dm_pci_read_config16(pch, 0x40, &pmbase);
+ pmbase &= 0xfffe;
writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
"intel,gpe0-enable", 0));
@@ -227,16 +230,16 @@
return 0;
}
-static void pch_rtc_init(pci_dev_t dev)
+static void pch_rtc_init(struct udevice *pch)
{
int rtc_failed;
u8 reg8;
- reg8 = x86_pci_read_config8(dev, GEN_PMCON_3);
+ dm_pci_read_config8(pch, GEN_PMCON_3, ®8);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
- x86_pci_write_config8(dev, GEN_PMCON_3, reg8);
+ dm_pci_write_config8(pch, GEN_PMCON_3, reg8);
}
debug("rtc_failed = 0x%x\n", rtc_failed);
@@ -246,10 +249,10 @@
}
/* CougarPoint PCH Power Management init */
-static void cpt_pm_init(pci_dev_t dev)
+static void cpt_pm_init(struct udevice *pch)
{
debug("CougarPoint PM init\n");
- x86_pci_write_config8(dev, 0xa9, 0x47);
+ dm_pci_write_config8(pch, 0xa9, 0x47);
setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
setbits_le32(RCB_REG(0x228c), 1 << 0);
@@ -290,10 +293,10 @@
}
/* PantherPoint PCH Power Management init */
-static void ppt_pm_init(pci_dev_t dev)
+static void ppt_pm_init(struct udevice *pch)
{
debug("PantherPoint PM init\n");
- x86_pci_write_config8(dev, 0xa9, 0x47);
+ dm_pci_write_config8(pch, 0xa9, 0x47);
setbits_le32(RCB_REG(0x2238), 1 << 0);
setbits_le32(RCB_REG(0x228c), 1 << 0);
setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
@@ -340,21 +343,21 @@
clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
}
-static void enable_clock_gating(pci_dev_t dev)
+static void enable_clock_gating(struct udevice *pch)
{
u32 reg32;
u16 reg16;
setbits_le32(RCB_REG(0x2234), 0xf);
- reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
+ dm_pci_read_config16(pch, GEN_PMCON_1, ®16);
reg16 |= (1 << 2) | (1 << 11);
- x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
+ dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
- pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
- pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
- pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
- pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
+ pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31));
+ pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7));
+ pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31));
+ pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
reg32 = readl(RCB_REG(CG));
reg32 |= (1 << 31);
@@ -376,77 +379,24 @@
setbits_le32(RCB_REG(0x3564), 0x3);
}
-#if CONFIG_HAVE_SMI_HANDLER
-static void pch_lock_smm(pci_dev_t dev)
-{
-#if TEST_SMM_FLASH_LOCKDOWN
- u8 reg8;
-#endif
-
- if (acpi_slp_type != 3) {
-#if ENABLE_ACPI_MODE_IN_COREBOOT
- debug("Enabling ACPI via APMC:\n");
- outb(0xe1, 0xb2); /* Enable ACPI mode */
- debug("done.\n");
-#else
- debug("Disabling ACPI via APMC:\n");
- outb(0x1e, 0xb2); /* Disable ACPI mode */
- debug("done.\n");
-#endif
- }
-
- /* Don't allow evil boot loaders, kernels, or
- * userspace applications to deceive us:
- */
- smm_lock();
-
-#if TEST_SMM_FLASH_LOCKDOWN
- /* Now try this: */
- debug("Locking BIOS to RO... ");
- reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
- (reg8 & 1) ? "rw" : "ro");
- reg8 &= ~(1 << 0); /* clear BIOSWE */
- x86_pci_write_config8(dev, 0xdc, reg8);
- reg8 |= (1 << 1); /* set BLE */
- x86_pci_write_config8(dev, 0xdc, reg8);
- debug("ok.\n");
- reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
- (reg8 & 1) ? "rw" : "ro");
-
- debug("Writing:\n");
- writeb(0, 0xfff00000);
- debug("Testing:\n");
- reg8 |= (1 << 0); /* set BIOSWE */
- x86_pci_write_config8(dev, 0xdc, reg8);
-
- reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
- (reg8 & 1) ? "rw" : "ro");
- debug("Done.\n");
-#endif
-}
-#endif
-
-static void pch_disable_smm_only_flashing(pci_dev_t dev)
+static void pch_disable_smm_only_flashing(struct udevice *pch)
{
u8 reg8;
debug("Enabling BIOS updates outside of SMM... ");
- reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */
reg8 &= ~(1 << 5);
- x86_pci_write_config8(dev, 0xdc, reg8);
+ dm_pci_write_config8(pch, 0xdc, reg8);
}
-static void pch_fixups(pci_dev_t dev)
+static void pch_fixups(struct udevice *pch)
{
u8 gen_pmcon_2;
/* Indicate DRAM init done for MRC S3 to know it can resume */
- gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2);
+ dm_pci_read_config8(pch, GEN_PMCON_2, &gen_pmcon_2);
gen_pmcon_2 |= (1 << 7);
- x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
+ dm_pci_write_config8(pch, GEN_PMCON_2, gen_pmcon_2);
/* Enable DMI ASPM in the PCH */
clrbits_le32(RCB_REG(0x2304), 1 << 10);
@@ -454,7 +404,49 @@
setbits_le32(RCB_REG(0x21a8), 0x3);
}
-int lpc_early_init(const void *blob, int node, pci_dev_t dev)
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(struct udevice *pch)
+{
+ u8 reg8;
+
+ dm_pci_read_config8(pch, 0xdc, ®8);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ dm_pci_write_config8(pch, 0xdc, reg8);
+}
+
+static void enable_port80_on_lpc(struct udevice *pch)
+{
+ /* Enable port 80 POST on LPC */
+ dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+ clrbits_le32(RCB_REG(GCS), 4);
+}
+
+static void set_spi_speed(void)
+{
+ u32 fdod;
+
+ /* Observe SPI Descriptor Component Section 0 */
+ writel(0x1000, RCB_REG(SPI_DESC_COMP0));
+
+ /* Extract the1 Write/Erase SPI Frequency from descriptor */
+ fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
+ fdod >>= 24;
+ fdod &= 7;
+
+ /* Set Software Sequence frequency to match */
+ clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
+}
+
+/**
+ * lpc_early_init() - set up LPC serial ports and other early things
+ *
+ * @dev: LPC device
+ * @return 0 if OK, -ve on error
+ */
+static int lpc_early_init(struct udevice *dev)
{
struct reg_info {
u32 base;
@@ -463,17 +455,18 @@
int count;
int i;
- count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec",
- (u32 *)values, sizeof(values) / sizeof(u32));
+ count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
+ "intel,gen-dec", (u32 *)values,
+ sizeof(values) / sizeof(u32));
if (count < 0)
return -EINVAL;
/* Set COM1/COM2 decode range */
- x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010);
+ dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
- x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
- GAMEL_LPC_EN | COMA_LPC_EN);
+ dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+ GAMEL_LPC_EN | COMA_LPC_EN);
/* Write all registers but use 0 if we run out of data */
count = count * sizeof(u32) / sizeof(values[0]);
@@ -482,81 +475,114 @@
if (i < count)
reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
- x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg);
+ dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
}
+ enable_spi_prefetch(dev->parent);
+
+ /* This is already done in start.S, but let's do it in C */
+ enable_port80_on_lpc(dev->parent);
+
+ set_spi_speed();
+
return 0;
}
-int lpc_init(struct pci_controller *hose, pci_dev_t dev)
+static int lpc_init_extra(struct udevice *dev)
{
+ struct udevice *pch = dev->parent;
const void *blob = gd->fdt_blob;
int node;
debug("pch: lpc_init\n");
- pci_write_bar32(hose, dev, 0, 0);
- pci_write_bar32(hose, dev, 1, 0xff800000);
- pci_write_bar32(hose, dev, 2, 0xfec00000);
- pci_write_bar32(hose, dev, 3, 0x800);
- pci_write_bar32(hose, dev, 4, 0x900);
+ dm_pci_write_bar32(pch, 0, 0);
+ dm_pci_write_bar32(pch, 1, 0xff800000);
+ dm_pci_write_bar32(pch, 2, 0xfec00000);
+ dm_pci_write_bar32(pch, 3, 0x800);
+ dm_pci_write_bar32(pch, 4, 0x900);
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
if (node < 0)
return -ENOENT;
/* Set the value for PCI command register. */
- x86_pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */
- pch_enable_apic(dev);
+ pch_enable_apic(pch);
- pch_enable_serial_irqs(dev);
+ pch_enable_serial_irqs(pch);
/* Setup the PIRQ. */
- pch_pirq_init(blob, node, dev);
+ pch_pirq_init(pch);
/* Setup power options. */
- pch_power_options(blob, node, dev);
+ pch_power_options(pch);
/* Initialize power management */
- switch (pch_silicon_type()) {
+ switch (pch_silicon_type(pch)) {
case PCH_TYPE_CPT: /* CougarPoint */
- cpt_pm_init(dev);
+ cpt_pm_init(pch);
break;
case PCH_TYPE_PPT: /* PantherPoint */
- ppt_pm_init(dev);
+ ppt_pm_init(pch);
break;
default:
- printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev),
- PCI_FUNC(dev));
+ printf("Unknown Chipset: %s\n", pch->name);
return -ENOSYS;
}
/* Initialize the real time clock. */
- pch_rtc_init(dev);
+ pch_rtc_init(pch);
/* Initialize the High Precision Event Timers, if present. */
enable_hpet();
/* Initialize Clock Gating */
- enable_clock_gating(dev);
+ enable_clock_gating(pch);
- pch_disable_smm_only_flashing(dev);
+ pch_disable_smm_only_flashing(pch);
-#if CONFIG_HAVE_SMI_HANDLER
- pch_lock_smm(dev);
-#endif
-
- pch_fixups(dev);
+ pch_fixups(pch);
return 0;
}
-void lpc_enable(pci_dev_t dev)
+static int bd82x6x_lpc_early_init(struct udevice *dev)
{
- /* Enable PCH Display Port */
- writew(0x0010, RCB_REG(DISPBDF));
- setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
+ /* Setting up Southbridge. In the northbridge code. */
+ debug("Setting up static southbridge registers\n");
+ dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+ dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1);
+
+ /* Enable ACPI BAR */
+ dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80);
+
+ debug("Disabling watchdog reboot\n");
+ setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
+ outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
+
+ dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+ dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10);
+
+ return 0;
+}
+
+static int bd82x6x_lpc_probe(struct udevice *dev)
+{
+ int ret;
+
+ if (!(gd->flags & GD_FLG_RELOC)) {
+ ret = lpc_early_init(dev);
+ if (ret) {
+ debug("%s: lpc_early_init() failed\n", __func__);
+ return ret;
+ }
+
+ return bd82x6x_lpc_early_init(dev);
+ }
+
+ return lpc_init_extra(dev);
}
static const struct udevice_id bd82x6x_lpc_ids[] = {
@@ -568,4 +594,5 @@
.name = "lpc",
.id = UCLASS_LPC,
.of_match = bd82x6x_lpc_ids,
+ .probe = bd82x6x_lpc_probe,
};
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index fd7db97..9654600 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -8,10 +8,13 @@
*/
#include <common.h>
+#include <cpu.h>
+#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
#include <asm/acpi.h>
#include <asm/cpu.h>
+#include <asm/cpu_x86.h>
#include <asm/lapic.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
@@ -280,18 +283,13 @@
msr_write(MSR_PP1_CURRENT_CONFIG, msr);
}
-static int configure_thermal_target(void)
+static int configure_thermal_target(struct udevice *dev)
{
int tcc_offset;
msr_t msr;
- int node;
- /* Find pointer to CPU configuration */
- node = fdtdec_next_compatible(gd->fdt_blob, 0,
- COMPAT_INTEL_MODEL_206AX);
- if (node < 0)
- return -ENOENT;
- tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0);
+ tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "tcc-offset",
+ 0);
/* Set TCC activaiton offset if supported */
msr = msr_read(MSR_PLATFORM_INFO);
@@ -400,56 +398,7 @@
static unsigned ehci_debug_addr;
#endif
-/*
- * Initialize any extra cores/threads in this package.
- */
-static int intel_cores_init(struct x86_cpu_priv *cpu)
-{
- struct cpuid_result result;
- unsigned threads_per_package, threads_per_core, i;
-
- /* Logical processors (threads) per core */
- result = cpuid_ext(0xb, 0);
- threads_per_core = result.ebx & 0xffff;
-
- /* Logical processors (threads) per package */
- result = cpuid_ext(0xb, 1);
- threads_per_package = result.ebx & 0xffff;
-
- debug("CPU: %u has %u cores, %u threads per core\n",
- cpu->apic_id, threads_per_package / threads_per_core,
- threads_per_core);
-
- for (i = 1; i < threads_per_package; ++i) {
- struct x86_cpu_priv *new_cpu;
-
- new_cpu = calloc(1, sizeof(*new_cpu));
- if (!new_cpu)
- return -ENOMEM;
-
- new_cpu->apic_id = cpu->apic_id + i;
-
- /* Update APIC ID if no hyperthreading */
- if (threads_per_core == 1)
- new_cpu->apic_id <<= 1;
-
- debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id);
-
-#if 0 && CONFIG_SMP && CONFIG_MAX_CPUS > 1
- /* TODO(sjg@chromium.org): Start the new cpu */
- if (!start_cpu(new_cpu)) {
- /* Record the error in cpu? */
- printk(BIOS_ERR, "CPU %u would not start!\n",
- new_cpu->apic_id);
- new_cpu->start_err = 1;
- }
-#endif
- }
-
- return 0;
-}
-
-int model_206ax_init(struct x86_cpu_priv *cpu)
+static int model_206ax_init(struct udevice *dev)
{
int ret;
@@ -463,16 +412,6 @@
set_ehci_debug(0);
#endif
- /* Setup MTRRs based on physical address size */
-#if 0 /* TODO: Implement this */
- struct cpuid_result cpuid_regs;
-
- cpuid_regs = cpuid(0x80000008);
- x86_setup_fixed_mtrrs();
- x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
- x86_mtrr_check();
-#endif
-
#if CONFIG_USBDEBUG
set_ehci_debug(ehci_debug_addr);
#endif
@@ -491,9 +430,11 @@
configure_misc();
/* Thermal throttle activation offset */
- ret = configure_thermal_target();
- if (ret)
+ ret = configure_thermal_target(dev);
+ if (ret) {
+ debug("Cannot set thermal target\n");
return ret;
+ }
/* Enable Direct Cache Access */
configure_dca_cap();
@@ -507,8 +448,49 @@
/* Enable Turbo */
turbo_enable();
- /* Start up extra cores */
- intel_cores_init(cpu);
+ return 0;
+}
+
+static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ msr_t msr;
+
+ msr = msr_read(IA32_PERF_CTL);
+ info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;
+ info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
return 0;
}
+
+static int model_206ax_get_count(struct udevice *dev)
+{
+ return 4;
+}
+
+static int cpu_x86_model_206ax_probe(struct udevice *dev)
+{
+ if (dev->seq == 0)
+ model_206ax_init(dev);
+
+ return 0;
+}
+
+static const struct cpu_ops cpu_x86_model_206ax_ops = {
+ .get_desc = cpu_x86_get_desc,
+ .get_info = model_206ax_get_info,
+ .get_count = model_206ax_get_count,
+};
+
+static const struct udevice_id cpu_x86_model_206ax_ids[] = {
+ { .compatible = "intel,core-gen3" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = {
+ .name = "cpu_x86_model_206ax",
+ .id = UCLASS_CPU,
+ .of_match = cpu_x86_model_206ax_ids,
+ .bind = cpu_x86_bind,
+ .probe = cpu_x86_model_206ax_probe,
+ .ops = &cpu_x86_model_206ax_ops,
+};
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index e3d8c13..a066607 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <asm/msr.h>
#include <asm/acpi.h>
#include <asm/cpu.h>
@@ -18,23 +19,17 @@
#include <asm/arch/model_206ax.h>
#include <asm/arch/sandybridge.h>
-static int bridge_revision_id = -1;
-
-int bridge_silicon_revision(void)
+int bridge_silicon_revision(struct udevice *dev)
{
- if (bridge_revision_id < 0) {
- struct cpuid_result result;
- uint8_t stepping, bridge_id;
- pci_dev_t dev;
+ struct cpuid_result result;
+ u16 bridge_id;
+ u8 stepping;
- result = cpuid(1);
- stepping = result.eax & 0xf;
- dev = PCI_BDF(0, 0, 0);
- bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
- bridge_revision_id = bridge_id | stepping;
- }
-
- return bridge_revision_id;
+ result = cpuid(1);
+ stepping = result.eax & 0xf;
+ dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id);
+ bridge_id &= 0xf0;
+ return bridge_id | stepping;
}
/*
@@ -47,15 +42,14 @@
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
-static int get_pcie_bar(u32 *base, u32 *len)
+static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len)
{
- pci_dev_t dev = PCI_BDF(0, 0, 0);
u32 pciexbar_reg;
*base = 0;
*len = 0;
- pciexbar_reg = x86_pci_read_config32(dev, PCIEXBAR);
+ dm_pci_read_config32(dev, PCIEXBAR, &pciexbar_reg);
if (!(pciexbar_reg & (1 << 0)))
return 0;
@@ -81,55 +75,55 @@
return 0;
}
-static void add_fixed_resources(pci_dev_t dev, int index)
+static void add_fixed_resources(struct udevice *dev, int index)
{
u32 pcie_config_base, pcie_config_size;
- if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+ if (get_pcie_bar(dev, &pcie_config_base, &pcie_config_size)) {
debug("Adding PCIe config bar base=0x%08x size=0x%x\n",
pcie_config_base, pcie_config_size);
}
}
-static void northbridge_dmi_init(pci_dev_t dev)
+static void northbridge_dmi_init(struct udevice *dev, int rev)
{
/* Clear error status bits */
writel(0xffffffff, DMIBAR_REG(0x1c4));
writel(0xffffffff, DMIBAR_REG(0x1d0));
/* Steps prior to DMI ASPM */
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),
1 << 21);
}
setbits_le32(DMIBAR_REG(0x238), 1 << 29);
- if (bridge_silicon_revision() >= SNB_STEP_D0) {
+ if (rev >= SNB_STEP_D0) {
setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);
- } else if (bridge_silicon_revision() >= SNB_STEP_D1) {
+ } else if (rev >= SNB_STEP_D1) {
clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);
setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));
}
/* Enable ASPM on SNB link, should happen before PCH link */
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB)
+ if ((rev & BASE_REV_MASK) == BASE_REV_SNB)
setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
}
-void northbridge_init(pci_dev_t dev)
+static void northbridge_init(struct udevice *dev, int rev)
{
u32 bridge_type;
add_fixed_resources(dev, 6);
- northbridge_dmi_init(dev);
+ northbridge_dmi_init(dev, rev);
bridge_type = readl(MCHBAR_REG(0x5f10));
bridge_type &= ~0xff;
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
/* Enable Power Aware Interrupt Routing - fixed priority */
clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
@@ -167,6 +161,78 @@
writel(0x00100001, MCHBAR_REG(0x5500));
}
-void northbridge_enable(pci_dev_t dev)
+static void sandybridge_setup_northbridge_bars(struct udevice *dev)
{
+ /* Set up all hardcoded northbridge BARs */
+ debug("Setting up static registers\n");
+ dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
+ dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
+ dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1);
+ dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
+ /* 64MB - busses 0-63 */
+ dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
+ dm_pci_write_config32(dev, PCIEXBAR + 4,
+ (0LL + DEFAULT_PCIEXBAR) >> 32);
+ dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1);
+ dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
+
+ /* Set C0000-FFFFF to access RAM on both reads and writes */
+ dm_pci_write_config8(dev, PAM0, 0x30);
+ dm_pci_write_config8(dev, PAM1, 0x33);
+ dm_pci_write_config8(dev, PAM2, 0x33);
+ dm_pci_write_config8(dev, PAM3, 0x33);
+ dm_pci_write_config8(dev, PAM4, 0x33);
+ dm_pci_write_config8(dev, PAM5, 0x33);
+ dm_pci_write_config8(dev, PAM6, 0x33);
}
+
+static int bd82x6x_northbridge_early_init(struct udevice *dev)
+{
+ const int chipset_type = SANDYBRIDGE_MOBILE;
+ u32 capid0_a;
+ u8 reg8;
+
+ /* Device ID Override Enable should be done very early */
+ dm_pci_read_config32(dev, 0xe4, &capid0_a);
+ if (capid0_a & (1 << 10)) {
+ dm_pci_read_config8(dev, 0xf3, ®8);
+ reg8 &= ~7; /* Clear 2:0 */
+
+ if (chipset_type == SANDYBRIDGE_MOBILE)
+ reg8 |= 1; /* Set bit 0 */
+
+ dm_pci_write_config8(dev, 0xf3, reg8);
+ }
+
+ sandybridge_setup_northbridge_bars(dev);
+
+ /* Device Enable */
+ dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
+
+ return 0;
+}
+
+static int bd82x6x_northbridge_probe(struct udevice *dev)
+{
+ int rev;
+
+ if (!(gd->flags & GD_FLG_RELOC))
+ return bd82x6x_northbridge_early_init(dev);
+
+ rev = bridge_silicon_revision(dev);
+ northbridge_init(dev, rev);
+
+ return 0;
+}
+
+static const struct udevice_id bd82x6x_northbridge_ids[] = {
+ { .compatible = "intel,bd82x6x-northbridge" },
+ { }
+};
+
+U_BOOT_DRIVER(bd82x6x_northbridge_drv) = {
+ .name = "bd82x6x_northbridge",
+ .id = UCLASS_NORTHBRIDGE,
+ .of_match = bd82x6x_northbridge_ids,
+ .probe = bd82x6x_northbridge_probe,
+};
diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c
deleted file mode 100644
index bbab646..0000000
--- a/arch/x86/cpu/ivybridge/pch.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * From Coreboot
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2012 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-
-static int pch_revision_id = -1;
-static int pch_type = -1;
-
-int pch_silicon_revision(void)
-{
- pci_dev_t dev;
-
- dev = PCH_LPC_DEV;
-
- if (pch_revision_id < 0)
- pch_revision_id = x86_pci_read_config8(dev, PCI_REVISION_ID);
- return pch_revision_id;
-}
-
-int pch_silicon_type(void)
-{
- pci_dev_t dev;
-
- dev = PCH_LPC_DEV;
-
- if (pch_type < 0)
- pch_type = x86_pci_read_config8(dev, PCI_DEVICE_ID + 1);
- return pch_type;
-}
-
-int pch_silicon_supported(int type, int rev)
-{
- int cur_type = pch_silicon_type();
- int cur_rev = pch_silicon_revision();
-
- switch (type) {
- case PCH_TYPE_CPT:
- /* CougarPoint minimum revision */
- if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
- return 1;
- /* PantherPoint any revision */
- if (cur_type == PCH_TYPE_PPT)
- return 1;
- break;
-
- case PCH_TYPE_PPT:
- /* PantherPoint minimum revision */
- if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
- return 1;
- break;
- }
-
- return 0;
-}
-
-#define IOBP_RETRY 1000
-static inline int iobp_poll(void)
-{
- unsigned try = IOBP_RETRY;
- u32 data;
-
- while (try--) {
- data = readl(RCB_REG(IOBPS));
- if ((data & 1) == 0)
- return 1;
- udelay(10);
- }
-
- printf("IOBP timeout\n");
- return 0;
-}
-
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
-{
- u32 data;
-
- /* Set the address */
- writel(address, RCB_REG(IOBPIRI));
-
- /* READ OPCODE */
- if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
- writel(IOBPS_RW_BX, RCB_REG(IOBPS));
- else
- writel(IOBPS_READ_AX, RCB_REG(IOBPS));
- if (!iobp_poll())
- return;
-
- /* Read IOBP data */
- data = readl(RCB_REG(IOBPD));
- if (!iobp_poll())
- return;
-
- /* Check for successful transaction */
- if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
- printf("IOBP read 0x%08x failed\n", address);
- return;
- }
-
- /* Update the data */
- data &= andvalue;
- data |= orvalue;
-
- /* WRITE OPCODE */
- if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
- writel(IOBPS_RW_BX, RCB_REG(IOBPS));
- else
- writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
- if (!iobp_poll())
- return;
-
- /* Write IOBP data */
- writel(data, RCB_REG(IOBPD));
- if (!iobp_poll())
- return;
-}
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
deleted file mode 100644
index 5e90f30..0000000
--- a/arch/x86/cpu/ivybridge/pci.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2008,2009
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <pci.h>
-#include <asm/pci.h>
-#include <asm/post.h>
-#include <asm/arch/bd82x6x.h>
-#include <asm/arch/pch.h>
-
-static int pci_ivybridge_probe(struct udevice *bus)
-{
- struct pci_controller *hose = dev_get_uclass_priv(bus);
- pci_dev_t dev;
- u16 reg16;
-
- if (!(gd->flags & GD_FLG_RELOC))
- return 0;
- post_code(0x50);
- bd82x6x_init();
- post_code(0x51);
-
- reg16 = 0xff;
- dev = PCH_DEV;
- reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- x86_pci_write_config16(dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- pci_write_bar32(hose, dev, 0, 0xf0000000);
- post_code(0x52);
-
- return 0;
-}
-
-static const struct dm_pci_ops pci_ivybridge_ops = {
- .read_config = pci_x86_read_config,
- .write_config = pci_x86_write_config,
-};
-
-static const struct udevice_id pci_ivybridge_ids[] = {
- { .compatible = "intel,pci-ivybridge" },
- { }
-};
-
-U_BOOT_DRIVER(pci_ivybridge_drv) = {
- .name = "pci_ivybridge",
- .id = UCLASS_PCI,
- .of_match = pci_ivybridge_ids,
- .ops = &pci_ivybridge_ops,
- .probe = pci_ivybridge_probe,
-};
diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c
index 4493870..c78322a 100644
--- a/arch/x86/cpu/ivybridge/report_platform.c
+++ b/arch/x86/cpu/ivybridge/report_platform.c
@@ -10,6 +10,7 @@
#include <asm/cpu.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
static void report_cpu_info(void)
{
@@ -63,27 +64,27 @@
{0x1E5F, "NM70"},
};
-static void report_pch_info(void)
+static void report_pch_info(struct udevice *dev)
{
const char *pch_type = "Unknown";
int i;
u16 dev_id;
uint8_t rev_id;
- dev_id = x86_pci_read_config16(PCH_LPC_DEV, 2);
+ dm_pci_read_config16(dev, 2, &dev_id);
for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
if (pch_table[i].dev_id == dev_id) {
pch_type = pch_table[i].dev_name;
break;
}
}
- rev_id = x86_pci_read_config8(PCH_LPC_DEV, 8);
+ dm_pci_read_config8(dev, 8, &rev_id);
debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
rev_id);
}
-void report_platform_info(void)
+void report_platform_info(struct udevice *dev)
{
report_cpu_info();
- report_pch_info();
+ report_pch_info(dev);
}
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index e7bf03c..a59d9ed 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -6,48 +6,56 @@
*/
#include <common.h>
+#include <dm.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
#include <asm/arch/bd82x6x.h>
-static inline u32 sir_read(pci_dev_t dev, int idx)
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline u32 sir_read(struct udevice *dev, int idx)
{
- x86_pci_write_config32(dev, SATA_SIRI, idx);
- return x86_pci_read_config32(dev, SATA_SIRD);
+ u32 data;
+
+ dm_pci_write_config32(dev, SATA_SIRI, idx);
+ dm_pci_read_config32(dev, SATA_SIRD, &data);
+
+ return data;
}
-static inline void sir_write(pci_dev_t dev, int idx, u32 value)
+static inline void sir_write(struct udevice *dev, int idx, u32 value)
{
- x86_pci_write_config32(dev, SATA_SIRI, idx);
- x86_pci_write_config32(dev, SATA_SIRD, value);
+ dm_pci_write_config32(dev, SATA_SIRI, idx);
+ dm_pci_write_config32(dev, SATA_SIRD, value);
}
-static void common_sata_init(pci_dev_t dev, unsigned int port_map)
+static void common_sata_init(struct udevice *dev, unsigned int port_map)
{
u32 reg32;
u16 reg16;
/* Set IDE I/O Configuration */
reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
- x86_pci_write_config32(dev, IDE_CONFIG, reg32);
+ dm_pci_write_config32(dev, IDE_CONFIG, reg32);
/* Port enable */
- reg16 = x86_pci_read_config16(dev, 0x92);
+ dm_pci_read_config16(dev, 0x92, ®16);
reg16 &= ~0x3f;
reg16 |= port_map;
- x86_pci_write_config16(dev, 0x92, reg16);
+ dm_pci_write_config16(dev, 0x92, reg16);
/* SATA Initialization register */
port_map &= 0xff;
- x86_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
+ dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
}
-void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
+static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
{
unsigned int port_map, speed_support, port_tx;
- struct pci_controller *hose = pci_bus_to_hose(0);
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
const char *mode;
u32 reg32;
u16 reg16;
@@ -59,33 +67,27 @@
speed_support = fdtdec_get_int(blob, node,
"sata_interface_speed_support", 0);
- /* Enable BARs */
- x86_pci_write_config16(dev, PCI_COMMAND, 0x0007);
-
mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
if (!mode || !strcmp(mode, "ahci")) {
u32 abar;
debug("SATA: Controller in AHCI mode\n");
- /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
- x86_pci_write_config8(dev, INTR_LN, 0x0a);
-
/* Set timings */
- x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
IDE_PPE0 | IDE_IE0 | IDE_TIME0);
- x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
/* Sync DMA */
- x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
- x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
+ dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+ dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
common_sata_init(dev, 0x8000 | port_map);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_bar32(hose, dev, 5);
+ abar = dm_pci_read_bar32(dev, 5);
debug("ABAR: %08X\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = readl(abar + 0x00);
@@ -113,59 +115,54 @@
debug("SATA: Controller in combined mode\n");
/* No AHCI: clear AHCI base */
- pci_write_bar32(hose, dev, 5, 0x00000000);
+ dm_pci_write_bar32(dev, 5, 0x00000000);
/* And without AHCI BAR no memory decoding */
- reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
+ dm_pci_read_config16(dev, PCI_COMMAND, ®16);
reg16 &= ~PCI_COMMAND_MEMORY;
- x86_pci_write_config16(dev, PCI_COMMAND, reg16);
+ dm_pci_write_config16(dev, PCI_COMMAND, reg16);
- x86_pci_write_config8(dev, 0x09, 0x80);
+ dm_pci_write_config8(dev, 0x09, 0x80);
/* Set timings */
- x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
- x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
IDE_PPE0 | IDE_IE0 | IDE_TIME0);
/* Sync DMA */
- x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
- x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
+ dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+ dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
common_sata_init(dev, port_map);
} else {
debug("SATA: Controller in plain-ide mode\n");
/* No AHCI: clear AHCI base */
- pci_write_bar32(hose, dev, 5, 0x00000000);
+ dm_pci_write_bar32(dev, 5, 0x00000000);
/* And without AHCI BAR no memory decoding */
- reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
+ dm_pci_read_config16(dev, PCI_COMMAND, ®16);
reg16 &= ~PCI_COMMAND_MEMORY;
- x86_pci_write_config16(dev, PCI_COMMAND, reg16);
+ dm_pci_write_config16(dev, PCI_COMMAND, reg16);
/*
* Native mode capable on both primary and secondary (0xa)
* OR'ed with enabled (0x50) = 0xf
*/
- x86_pci_write_config8(dev, 0x09, 0x8f);
-
- /* Set Interrupt Line */
- /* Interrupt Pin is set by D31IP.PIP */
- x86_pci_write_config8(dev, INTR_LN, 0xff);
+ dm_pci_write_config8(dev, 0x09, 0x8f);
/* Set timings */
- x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
IDE_PPE0 | IDE_IE0 | IDE_TIME0);
- x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
IDE_SITRE | IDE_ISP_3_CLOCKS |
IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
/* Sync DMA */
- x86_pci_write_config16(dev, IDE_SDMA_CNT,
- IDE_SSDE0 | IDE_PSDE0);
- x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
+ dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
+ dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
common_sata_init(dev, port_map);
}
@@ -173,11 +170,11 @@
/* Set Gen3 Transmitter settings if needed */
port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
if (port_tx)
- pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx);
+ pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);
port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
if (port_tx)
- pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx);
+ pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
/* Additional Programming Requirements */
sir_write(dev, 0x04, 0x00001600);
@@ -202,12 +199,14 @@
sir_write(dev, 0xc8, 0x0c0c0c0c);
sir_write(dev, 0xd4, 0x10000000);
- pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
- pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
+ pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
+ pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
}
-void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
+static void bd82x6x_sata_enable(struct udevice *dev)
{
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
unsigned port_map;
const char *mode;
u16 map = 0;
@@ -222,5 +221,36 @@
port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
map |= (port_map ^ 0x3f) << 8;
- x86_pci_write_config16(dev, 0x90, map);
+ dm_pci_write_config16(dev, 0x90, map);
}
+
+static int bd82x6x_sata_probe(struct udevice *dev)
+{
+ struct udevice *pch;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_PCH, &pch);
+ if (ret)
+ return ret;
+ if (!pch)
+ return -ENODEV;
+
+ if (!(gd->flags & GD_FLG_RELOC))
+ bd82x6x_sata_enable(dev);
+ else
+ bd82x6x_sata_init(dev, pch);
+
+ return 0;
+}
+
+static const struct udevice_id bd82x6x_ahci_ids[] = {
+ { .compatible = "intel,pantherpoint-ahci" },
+ { }
+};
+
+U_BOOT_DRIVER(ahci_ivybridge_drv) = {
+ .name = "ahci_ivybridge",
+ .id = UCLASS_DISK,
+ .of_match = bd82x6x_ahci_ids,
+ .probe = bd82x6x_sata_probe,
+};
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 4372a5c..e23c422 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -18,6 +18,8 @@
#include <rtc.h>
#include <spi.h>
#include <spi_flash.h>
+#include <syscon.h>
+#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <asm/global_data.h>
@@ -283,22 +285,24 @@
/**
* Find the PEI executable in the ROM and execute it.
*
- * @param pei_data: configuration data for UEFI PEI reference code
+ * @dev: Northbridge device
+ * @pei_data: configuration data for UEFI PEI reference code
*/
-int sdram_initialise(struct pei_data *pei_data)
+int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
+ struct pei_data *pei_data)
{
unsigned version;
const char *data;
uint16_t done;
int ret;
- report_platform_info();
+ report_platform_info(dev);
/* Wait for ME to be ready */
- ret = intel_early_me_init();
+ ret = intel_early_me_init(me_dev);
if (ret)
return ret;
- ret = intel_early_me_uma_size();
+ ret = intel_early_me_uma_size(me_dev);
if (ret < 0)
return ret;
@@ -374,12 +378,12 @@
* Send ME init done for SandyBridge here. This is done inside the
* SystemAgent binary on IvyBridge
*/
- done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
+ dm_pci_read_config16(dev, PCI_DEVICE_ID, &done);
done &= BASE_REV_MASK;
if (BASE_REV_SNB == done)
- intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
+ intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS);
else
- intel_early_me_status();
+ intel_early_me_status(me_dev);
post_system_agent_init(pei_data);
report_memory_config();
@@ -495,8 +499,10 @@
*
* This is a bit complicated since on x86 there are system memory holes all
* over the place. We create a list of available memory blocks
+ *
+ * @dev: Northbridge device
*/
-static int sdram_find(pci_dev_t dev)
+static int sdram_find(struct udevice *dev)
{
struct memory_info *info = &gd->arch.meminfo;
uint32_t tseg_base, uma_size, tolud;
@@ -505,6 +511,7 @@
uint64_t uma_memory_size;
unsigned long long tomk;
uint16_t ggc;
+ u32 val;
/* Total Memory 2GB example:
*
@@ -533,24 +540,27 @@
*/
/* Top of Upper Usable DRAM, including remap */
- touud = x86_pci_read_config32(dev, TOUUD+4);
- touud <<= 32;
- touud |= x86_pci_read_config32(dev, TOUUD);
+ dm_pci_read_config32(dev, TOUUD + 4, &val);
+ touud = (uint64_t)val << 32;
+ dm_pci_read_config32(dev, TOUUD, &val);
+ touud |= val;
/* Top of Lower Usable DRAM */
- tolud = x86_pci_read_config32(dev, TOLUD);
+ dm_pci_read_config32(dev, TOLUD, &tolud);
/* Top of Memory - does not account for any UMA */
- tom = x86_pci_read_config32(dev, 0xa4);
- tom <<= 32;
- tom |= x86_pci_read_config32(dev, 0xa0);
+ dm_pci_read_config32(dev, 0xa4, &val);
+ tom = (uint64_t)val << 32;
+ dm_pci_read_config32(dev, 0xa0, &val);
+ tom |= val;
debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
/* ME UMA needs excluding if total memory <4GB */
- me_base = x86_pci_read_config32(dev, 0x74);
- me_base <<= 32;
- me_base |= x86_pci_read_config32(dev, 0x70);
+ dm_pci_read_config32(dev, 0x74, &val);
+ me_base = (uint64_t)val << 32;
+ dm_pci_read_config32(dev, 0x70, &val);
+ me_base |= val;
debug("MEBASE %llx\n", me_base);
@@ -568,7 +578,7 @@
}
/* Graphics memory comes next */
- ggc = x86_pci_read_config16(dev, GGC);
+ dm_pci_read_config16(dev, GGC, &ggc);
if (!(ggc & 2)) {
debug("IGD decoded, subtracting ");
@@ -588,7 +598,7 @@
}
/* Calculate TSEG size from its base which must be below GTT */
- tseg_base = x86_pci_read_config32(dev, 0xb8);
+ dm_pci_read_config32(dev, 0xb8, &tseg_base);
uma_size = (uma_memory_base - tseg_base) >> 10;
tomk -= uma_size;
uma_memory_base = tomk * 1024ULL;
@@ -723,15 +733,23 @@
{ 0, 4, 0x0000 }, /* P13= Empty */
},
};
- pci_dev_t dev = PCI_BDF(0, 0, 0);
+ struct udevice *dev, *me_dev;
int ret;
+ ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+ if (ret)
+ return ret;
+ if (!dev)
+ return -ENODEV;
+ ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
+ if (ret)
+ return ret;
debug("Boot mode %d\n", gd->arch.pei_boot_mode);
debug("mrc_input %p\n", pei_data.mrc_input);
pei_data.boot_mode = gd->arch.pei_boot_mode;
ret = copy_spd(&pei_data);
if (!ret)
- ret = sdram_initialise(&pei_data);
+ ret = sdram_initialise(dev, me_dev, &pei_data);
if (ret)
return ret;
diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c
deleted file mode 100644
index da11aee..0000000
--- a/arch/x86/cpu/ivybridge/usb_ehci.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * From Coreboot
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-
-void bd82x6x_usb_ehci_init(pci_dev_t dev)
-{
- u32 reg32;
-
- /* Disable Wake on Disconnect in RMH */
- reg32 = readl(RCB_REG(0x35b0));
- reg32 |= 0x22;
- writel(reg32, RCB_REG(0x35b0));
-
- debug("EHCI: Setting up controller.. ");
- reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER;
- /* reg32 |= PCI_COMMAND_SERR; */
- x86_pci_write_config32(dev, PCI_COMMAND, reg32);
-
- debug("done.\n");
-}
diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c
deleted file mode 100644
index f77b804..0000000
--- a/arch/x86/cpu/ivybridge/usb_xhci.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * From Coreboot
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-
-void bd82x6x_usb_xhci_init(pci_dev_t dev)
-{
- u32 reg32;
-
- debug("XHCI: Setting up controller.. ");
-
- /* lock overcurrent map */
- reg32 = x86_pci_read_config32(dev, 0x44);
- reg32 |= 1;
- x86_pci_write_config32(dev, 0x44, reg32);
-
- /* Enable clock gating */
- reg32 = x86_pci_read_config32(dev, 0x40);
- reg32 &= ~((1 << 20) | (1 << 21));
- reg32 |= (1 << 19) | (1 << 18) | (1 << 17);
- reg32 |= (1 << 10) | (1 << 9) | (1 << 8);
- reg32 |= (1 << 31); /* lock */
- x86_pci_write_config32(dev, 0x40, reg32);
-
- debug("done.\n");
-}
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 46111c9..5a7b929 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -96,11 +96,6 @@
return 0;
}
-int arch_misc_init(void)
-{
- return pirq_init();
-}
-
#ifdef CONFIG_GENERATE_MP_TABLE
int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
{
diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile
index 8f1d018..6d670d7 100644
--- a/arch/x86/cpu/quark/Makefile
+++ b/arch/x86/cpu/quark/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += car.o dram.o msg_port.o quark.o
+obj-y += car.o dram.o irq.o msg_port.o quark.o
obj-y += mrc.o mrc_util.o hte.o smc.o
diff --git a/arch/x86/cpu/quark/irq.c b/arch/x86/cpu/quark/irq.c
new file mode 100644
index 0000000..1f8f909
--- /dev/null
+++ b/arch/x86/cpu/quark/irq.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/irq.h>
+#include <asm/arch/device.h>
+#include <asm/arch/quark.h>
+
+int quark_irq_router_probe(struct udevice *dev)
+{
+ struct quark_rcba *rcba;
+ u32 base;
+
+ qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
+ base &= ~MEM_BAR_EN;
+ rcba = (struct quark_rcba *)base;
+
+ /*
+ * Route Quark PCI device interrupt pin to PIRQ
+ *
+ * Route device#23's INTA/B/C/D to PIRQA/B/C/D
+ * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
+ */
+ writew(PIRQC, &rcba->rmu_ir);
+ writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
+ &rcba->d23_ir);
+ writew(PIRQD, &rcba->core_ir);
+ writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
+ &rcba->d20d21_ir);
+
+ return irq_router_common_init(dev);
+}
+
+static const struct udevice_id quark_irq_router_ids[] = {
+ { .compatible = "intel,quark-irq-router" },
+ { }
+};
+
+U_BOOT_DRIVER(quark_irq_router_drv) = {
+ .name = "quark_intel_irq",
+ .id = UCLASS_IRQ,
+ .of_match = quark_irq_router_ids,
+ .probe = quark_irq_router_probe,
+};
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 72c681d..6e20930 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -7,12 +7,10 @@
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
-#include <asm/irq.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/pci.h>
#include <asm/post.h>
-#include <asm/processor.h>
#include <asm/arch/device.h>
#include <asm/arch/msg_port.h>
#include <asm/arch/quark.h>
@@ -346,29 +344,6 @@
return pci_mmc_init("Quark SDHCI", mmc_supported);
}
-void cpu_irq_init(void)
-{
- struct quark_rcba *rcba;
- u32 base;
-
- qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
- base &= ~MEM_BAR_EN;
- rcba = (struct quark_rcba *)base;
-
- /*
- * Route Quark PCI device interrupt pin to PIRQ
- *
- * Route device#23's INTA/B/C/D to PIRQA/B/C/D
- * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
- */
- writew(PIRQC, &rcba->rmu_ir);
- writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
- &rcba->d23_ir);
- writew(PIRQD, &rcba->core_ir);
- writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
- &rcba->d20d21_ir);
-}
-
int arch_misc_init(void)
{
#ifdef CONFIG_ENABLE_MRC_CACHE
@@ -380,7 +355,7 @@
mrccache_save();
#endif
- return pirq_init();
+ return 0;
}
void board_final_cleanup(void)
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index 660f967..af3ffad 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += fsp_configs.o
+obj-y += fsp_configs.o irq.o
obj-y += tnc.o topcliff.o
diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c
new file mode 100644
index 0000000..44369f7
--- /dev/null
+++ b/arch/x86/cpu/queensbay/irq.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pci.h>
+#include <asm/arch/device.h>
+#include <asm/arch/tnc.h>
+
+int queensbay_irq_router_probe(struct udevice *dev)
+{
+ struct tnc_rcba *rcba;
+ u32 base;
+
+ base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
+ base &= ~MEM_BAR_EN;
+ rcba = (struct tnc_rcba *)base;
+
+ /* Make sure all internal PCI devices are using INTA */
+ writel(INTA, &rcba->d02ip);
+ writel(INTA, &rcba->d03ip);
+ writel(INTA, &rcba->d27ip);
+ writel(INTA, &rcba->d31ip);
+ writel(INTA, &rcba->d23ip);
+ writel(INTA, &rcba->d24ip);
+ writel(INTA, &rcba->d25ip);
+ writel(INTA, &rcba->d26ip);
+
+ /*
+ * Route TunnelCreek PCI device interrupt pin to PIRQ
+ *
+ * Since PCIe downstream ports received INTx are routed to PIRQ
+ * A/B/C/D directly and not configurable, we have to route PCIe
+ * root ports' INTx to PIRQ A/B/C/D as well. For other devices
+ * on TunneCreek, route them to PIRQ E/F/G/H.
+ */
+ writew(PIRQE, &rcba->d02ir);
+ writew(PIRQF, &rcba->d03ir);
+ writew(PIRQG, &rcba->d27ir);
+ writew(PIRQH, &rcba->d31ir);
+ writew(PIRQA, &rcba->d23ir);
+ writew(PIRQB, &rcba->d24ir);
+ writew(PIRQC, &rcba->d25ir);
+ writew(PIRQD, &rcba->d26ir);
+
+ return irq_router_common_init(dev);
+}
+
+static const struct udevice_id queensbay_irq_router_ids[] = {
+ { .compatible = "intel,queensbay-irq-router" },
+ { }
+};
+
+U_BOOT_DRIVER(queensbay_irq_router_drv) = {
+ .name = "queensbay_intel_irq",
+ .id = UCLASS_IRQ,
+ .of_match = queensbay_irq_router_ids,
+ .probe = queensbay_irq_router_probe,
+};
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index fb81919..75f7adb 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -69,46 +69,9 @@
return 0;
}
-void cpu_irq_init(void)
-{
- struct tnc_rcba *rcba;
- u32 base;
-
- base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
- base &= ~MEM_BAR_EN;
- rcba = (struct tnc_rcba *)base;
-
- /* Make sure all internal PCI devices are using INTA */
- writel(INTA, &rcba->d02ip);
- writel(INTA, &rcba->d03ip);
- writel(INTA, &rcba->d27ip);
- writel(INTA, &rcba->d31ip);
- writel(INTA, &rcba->d23ip);
- writel(INTA, &rcba->d24ip);
- writel(INTA, &rcba->d25ip);
- writel(INTA, &rcba->d26ip);
-
- /*
- * Route TunnelCreek PCI device interrupt pin to PIRQ
- *
- * Since PCIe downstream ports received INTx are routed to PIRQ
- * A/B/C/D directly and not configurable, we have to route PCIe
- * root ports' INTx to PIRQ A/B/C/D as well. For other devices
- * on TunneCreek, route them to PIRQ E/F/G/H.
- */
- writew(PIRQE, &rcba->d02ir);
- writew(PIRQF, &rcba->d03ir);
- writew(PIRQG, &rcba->d27ir);
- writew(PIRQH, &rcba->d31ir);
- writew(PIRQA, &rcba->d23ir);
- writew(PIRQB, &rcba->d24ir);
- writew(PIRQC, &rcba->d25ir);
- writew(PIRQD, &rcba->d26ir);
-}
-
int arch_misc_init(void)
{
unprotect_spi_flash();
- return pirq_init();
+ return 0;
}
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index d3380de..9bf707b 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -65,23 +65,6 @@
};
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "winbond,w25q64dw", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x006e0000 0x00010000>;
- };
- };
- };
-
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
@@ -133,66 +116,91 @@
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "ibase";
- intel,ibase-offset = <0x50>;
- intel,pirq-link = <8 8>;
- intel,pirq-mask = <0xdee0>;
- intel,pirq-routing = <
- /* BayTrail PCI devices */
- PCI_BDF(0, 2, 0) INTA PIRQA
- PCI_BDF(0, 3, 0) INTA PIRQA
- PCI_BDF(0, 16, 0) INTA PIRQA
- PCI_BDF(0, 17, 0) INTA PIRQA
- PCI_BDF(0, 18, 0) INTA PIRQA
- PCI_BDF(0, 19, 0) INTA PIRQA
- PCI_BDF(0, 20, 0) INTA PIRQA
- PCI_BDF(0, 21, 0) INTA PIRQA
- PCI_BDF(0, 22, 0) INTA PIRQA
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 24, 0) INTA PIRQA
- PCI_BDF(0, 24, 1) INTC PIRQC
- PCI_BDF(0, 24, 2) INTD PIRQD
- PCI_BDF(0, 24, 3) INTB PIRQB
- PCI_BDF(0, 24, 4) INTA PIRQA
- PCI_BDF(0, 24, 5) INTC PIRQC
- PCI_BDF(0, 24, 6) INTD PIRQD
- PCI_BDF(0, 24, 7) INTB PIRQB
- PCI_BDF(0, 26, 0) INTA PIRQA
- PCI_BDF(0, 27, 0) INTA PIRQA
- PCI_BDF(0, 28, 0) INTA PIRQA
- PCI_BDF(0, 28, 1) INTB PIRQB
- PCI_BDF(0, 28, 2) INTC PIRQC
- PCI_BDF(0, 28, 3) INTD PIRQD
- PCI_BDF(0, 29, 0) INTA PIRQA
- PCI_BDF(0, 30, 0) INTA PIRQA
- PCI_BDF(0, 30, 1) INTD PIRQD
- PCI_BDF(0, 30, 2) INTB PIRQB
- PCI_BDF(0, 30, 3) INTC PIRQC
- PCI_BDF(0, 30, 4) INTD PIRQD
- PCI_BDF(0, 30, 5) INTB PIRQB
- PCI_BDF(0, 31, 3) INTB PIRQB
+ compatible = "intel,pch9";
- /* PCIe root ports downstream interrupts */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(1, 0, 0) INTB PIRQB
- PCI_BDF(1, 0, 0) INTC PIRQC
- PCI_BDF(1, 0, 0) INTD PIRQD
- PCI_BDF(2, 0, 0) INTA PIRQB
- PCI_BDF(2, 0, 0) INTB PIRQC
- PCI_BDF(2, 0, 0) INTC PIRQD
- PCI_BDF(2, 0, 0) INTD PIRQA
- PCI_BDF(3, 0, 0) INTA PIRQC
- PCI_BDF(3, 0, 0) INTB PIRQD
- PCI_BDF(3, 0, 0) INTC PIRQA
- PCI_BDF(3, 0, 0) INTD PIRQB
- PCI_BDF(4, 0, 0) INTA PIRQD
- PCI_BDF(4, 0, 0) INTB PIRQA
- PCI_BDF(4, 0, 0) INTC PIRQB
- PCI_BDF(4, 0, 0) INTD PIRQC
- >;
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "ibase";
+ intel,ibase-offset = <0x50>;
+ intel,pirq-link = <8 8>;
+ intel,pirq-mask = <0xdee0>;
+ intel,pirq-routing = <
+ /* BayTrail PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQA
+ PCI_BDF(0, 3, 0) INTA PIRQA
+ PCI_BDF(0, 16, 0) INTA PIRQA
+ PCI_BDF(0, 17, 0) INTA PIRQA
+ PCI_BDF(0, 18, 0) INTA PIRQA
+ PCI_BDF(0, 19, 0) INTA PIRQA
+ PCI_BDF(0, 20, 0) INTA PIRQA
+ PCI_BDF(0, 21, 0) INTA PIRQA
+ PCI_BDF(0, 22, 0) INTA PIRQA
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 24, 0) INTA PIRQA
+ PCI_BDF(0, 24, 1) INTC PIRQC
+ PCI_BDF(0, 24, 2) INTD PIRQD
+ PCI_BDF(0, 24, 3) INTB PIRQB
+ PCI_BDF(0, 24, 4) INTA PIRQA
+ PCI_BDF(0, 24, 5) INTC PIRQC
+ PCI_BDF(0, 24, 6) INTD PIRQD
+ PCI_BDF(0, 24, 7) INTB PIRQB
+ PCI_BDF(0, 26, 0) INTA PIRQA
+ PCI_BDF(0, 27, 0) INTA PIRQA
+ PCI_BDF(0, 28, 0) INTA PIRQA
+ PCI_BDF(0, 28, 1) INTB PIRQB
+ PCI_BDF(0, 28, 2) INTC PIRQC
+ PCI_BDF(0, 28, 3) INTD PIRQD
+ PCI_BDF(0, 29, 0) INTA PIRQA
+ PCI_BDF(0, 30, 0) INTA PIRQA
+ PCI_BDF(0, 30, 1) INTD PIRQD
+ PCI_BDF(0, 30, 2) INTB PIRQB
+ PCI_BDF(0, 30, 3) INTC PIRQC
+ PCI_BDF(0, 30, 4) INTD PIRQD
+ PCI_BDF(0, 30, 5) INTB PIRQB
+ PCI_BDF(0, 31, 3) INTB PIRQB
+
+ /*
+ * PCIe root ports downstream
+ * interrupts
+ */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
+ PCI_BDF(3, 0, 0) INTA PIRQC
+ PCI_BDF(3, 0, 0) INTB PIRQD
+ PCI_BDF(3, 0, 0) INTC PIRQA
+ PCI_BDF(3, 0, 0) INTD PIRQB
+ PCI_BDF(4, 0, 0) INTA PIRQD
+ PCI_BDF(4, 0, 0) INTB PIRQA
+ PCI_BDF(4, 0, 0) INTC PIRQB
+ PCI_BDF(4, 0, 0) INTD PIRQC
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64dw",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x006e0000 0x00010000>;
+ };
+ };
+ };
};
};
diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts
index 194f0eb..4e9e410 100644
--- a/arch/x86/dts/broadwell_som-6896.dts
+++ b/arch/x86/dts/broadwell_som-6896.dts
@@ -29,16 +29,22 @@
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- };
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- reg = <0>;
- compatible = "winbond,w25q128", "spi-flash";
- memory-map = <0xff000000 0x01000000>;
+ pch@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,pch9";
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "winbond,w25q128", "spi-flash";
+ memory-map = <0xff000000 0x01000000>;
+ };
+ };
};
};
+
};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index c4469a9..d148d6e 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -12,12 +12,48 @@
aliases {
spi0 = "/pci/pch/spi";
+ usb0 = &usb_0;
+ usb1 = &usb_1;
};
config {
silent_console = <0>;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "intel,core-gen3";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "intel,core-gen3";
+ reg = <1>;
+ intel,apic-id = <1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "intel,core-gen3";
+ reg = <2>;
+ intel,apic-id = <2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "intel,core-gen3";
+ reg = <3>;
+ intel,apic-id = <3>;
+ };
+
+ };
+
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
@@ -159,21 +195,22 @@
};
pci {
- compatible = "intel,pci-ivybridge", "pci-x86";
+ compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xefff>;
- sata {
- compatible = "intel,pantherpoint-ahci";
- intel,sata-mode = "ahci";
- intel,sata-port-map = <1>;
- intel,sata-port0-gen3-tx = <0x00880a7f>;
+
+ northbridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ compatible = "intel,bd82x6x-northbridge";
+ u-boot,dm-pre-reloc;
};
- gma {
+ gma@2,0 {
+ reg = <0x00001000 0 0 0 0>;
compatible = "intel,gma";
intel,dp_hotplug = <0 0 0x06>;
intel,panel-port-select = <1>;
@@ -186,20 +223,35 @@
intel,pch-backlight = <0x04000000>;
};
- pch {
+ me@16,0 {
+ reg = <0x0000b000 0 0 0 0>;
+ compatible = "intel,me";
+ u-boot,dm-pre-reloc;
+ };
+
+ usb_1: usb@1a,0 {
+ reg = <0x0000d000 0 0 0 0>;
+ compatible = "ehci-pci";
+ };
+
+ usb_0: usb@1d,0 {
+ reg = <0x0000e800 0 0 0 0>;
+ compatible = "ehci-pci";
+ };
+
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,bd82x6x", "intel,pch";
+ compatible = "intel,bd82x6x", "intel,pch9";
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
- gen-dec = <0x800 0xfc 0x900 0xfc>;
- intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
0x80 0x80 0x80 0x80>;
intel,gpi-routing = <0 0 0 0 0 0 0 2
1 0 0 0 0 0 0 0>;
/* Enable EC SMI source */
intel,alt-gp-smi-enable = <0x0100>;
+
spi {
#address-cells = <1>;
#size-cells = <0>;
@@ -222,6 +274,8 @@
compatible = "intel,bd82x6x-lpc";
#address-cells = <1>;
#size-cells = <0>;
+ u-boot,dm-pre-reloc;
+ intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
cros-ec@200 {
compatible = "google,cros-ec";
reg = <0x204 1 0x200 1 0x880 0x80>;
@@ -239,6 +293,21 @@
};
};
};
+
+ sata@1f,2 {
+ compatible = "intel,pantherpoint-ahci";
+ reg = <0x0000fa00 0 0 0 0>;
+ u-boot,dm-pre-reloc;
+ intel,sata-mode = "ahci";
+ intel,sata-port-map = <1>;
+ intel,sata-port0-gen3-tx = <0x00880a7f>;
+ };
+
+ smbus: smbus@1f,3 {
+ compatible = "intel,ich-i2c";
+ reg = <0x0000fb00 0 0 0 0>;
+ u-boot,dm-pre-reloc;
+ };
};
tpm {
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 4e2b517..2302701 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -51,21 +51,27 @@
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xf000>;
- };
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #size-cells = <1>;
- #address-cells = <1>;
- reg = <0>;
- compatible = "winbond,w25q64", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x003e0000 0x00010000>;
+ pch@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,pch9";
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #size-cells = <1>;
+ #address-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x003e0000 0x00010000>;
+ };
+ };
};
};
};
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 84231b3..d6dd0b4 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -72,17 +72,6 @@
stdout-path = "/serial";
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- reg = <0>;
- compatible = "sst,25vf016b", "spi-flash";
- memory-map = <0xffe00000 0x00200000>;
- };
- };
-
microcode {
update@0 {
#include "microcode/m0220661105_cv.dtsi"
@@ -170,68 +159,85 @@
};
};
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 8>;
- intel,pirq-mask = <0xcee0>;
- intel,pirq-routing = <
- /* TunnelCreek PCI devices */
- PCI_BDF(0, 2, 0) INTA PIRQE
- PCI_BDF(0, 3, 0) INTA PIRQF
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 23, 0) INTB PIRQB
- PCI_BDF(0, 23, 0) INTC PIRQC
- PCI_BDF(0, 23, 0) INTD PIRQD
- PCI_BDF(0, 24, 0) INTA PIRQB
- PCI_BDF(0, 24, 0) INTB PIRQC
- PCI_BDF(0, 24, 0) INTC PIRQD
- PCI_BDF(0, 24, 0) INTD PIRQA
- PCI_BDF(0, 25, 0) INTA PIRQC
- PCI_BDF(0, 25, 0) INTB PIRQD
- PCI_BDF(0, 25, 0) INTC PIRQA
- PCI_BDF(0, 25, 0) INTD PIRQB
- PCI_BDF(0, 26, 0) INTA PIRQD
- PCI_BDF(0, 26, 0) INTB PIRQA
- PCI_BDF(0, 26, 0) INTC PIRQB
- PCI_BDF(0, 26, 0) INTD PIRQC
- PCI_BDF(0, 27, 0) INTA PIRQG
- /*
- * Topcliff PCI devices
- *
- * Note on the Crown Bay board, Topcliff chipset
- * is connected to TunnelCreek PCIe port 0, so
- * its bus number is 1 for its PCIe port and 2
- * for its PCI devices per U-Boot current PCI
- * bus enumeration algorithm.
- */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(2, 0, 1) INTA PIRQA
- PCI_BDF(2, 0, 2) INTA PIRQA
- PCI_BDF(2, 2, 0) INTB PIRQD
- PCI_BDF(2, 2, 1) INTB PIRQD
- PCI_BDF(2, 2, 2) INTB PIRQD
- PCI_BDF(2, 2, 3) INTB PIRQD
- PCI_BDF(2, 2, 4) INTB PIRQD
- PCI_BDF(2, 4, 0) INTC PIRQC
- PCI_BDF(2, 4, 1) INTC PIRQC
- PCI_BDF(2, 6, 0) INTD PIRQB
- PCI_BDF(2, 8, 0) INTA PIRQA
- PCI_BDF(2, 8, 1) INTA PIRQA
- PCI_BDF(2, 8, 2) INTA PIRQA
- PCI_BDF(2, 8, 3) INTA PIRQA
- PCI_BDF(2, 10, 0) INTB PIRQD
- PCI_BDF(2, 10, 1) INTB PIRQD
- PCI_BDF(2, 10, 2) INTB PIRQD
- PCI_BDF(2, 10, 3) INTB PIRQD
- PCI_BDF(2, 10, 4) INTB PIRQD
- PCI_BDF(2, 12, 0) INTC PIRQC
- PCI_BDF(2, 12, 1) INTC PIRQC
- PCI_BDF(2, 12, 2) INTC PIRQC
- PCI_BDF(2, 12, 3) INTC PIRQC
- PCI_BDF(2, 12, 4) INTC PIRQC
- >;
+ compatible = "intel,pch7";
+
+ irq-router {
+ compatible = "intel,queensbay-irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0xcee0>;
+ intel,pirq-routing = <
+ /* TunnelCreek PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQE
+ PCI_BDF(0, 3, 0) INTA PIRQF
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 23, 0) INTB PIRQB
+ PCI_BDF(0, 23, 0) INTC PIRQC
+ PCI_BDF(0, 23, 0) INTD PIRQD
+ PCI_BDF(0, 24, 0) INTA PIRQB
+ PCI_BDF(0, 24, 0) INTB PIRQC
+ PCI_BDF(0, 24, 0) INTC PIRQD
+ PCI_BDF(0, 24, 0) INTD PIRQA
+ PCI_BDF(0, 25, 0) INTA PIRQC
+ PCI_BDF(0, 25, 0) INTB PIRQD
+ PCI_BDF(0, 25, 0) INTC PIRQA
+ PCI_BDF(0, 25, 0) INTD PIRQB
+ PCI_BDF(0, 26, 0) INTA PIRQD
+ PCI_BDF(0, 26, 0) INTB PIRQA
+ PCI_BDF(0, 26, 0) INTC PIRQB
+ PCI_BDF(0, 26, 0) INTD PIRQC
+ PCI_BDF(0, 27, 0) INTA PIRQG
+ /*
+ * Topcliff PCI devices
+ *
+ * Note on the Crown Bay board, Topcliff
+ * chipset is connected to TunnelCreek
+ * PCIe port 0, so its bus number is 1
+ * for its PCIe port and 2 for its PCI
+ * devices per U-Boot current PCI bus
+ * enumeration algorithm.
+ */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(2, 0, 1) INTA PIRQA
+ PCI_BDF(2, 0, 2) INTA PIRQA
+ PCI_BDF(2, 2, 0) INTB PIRQD
+ PCI_BDF(2, 2, 1) INTB PIRQD
+ PCI_BDF(2, 2, 2) INTB PIRQD
+ PCI_BDF(2, 2, 3) INTB PIRQD
+ PCI_BDF(2, 2, 4) INTB PIRQD
+ PCI_BDF(2, 4, 0) INTC PIRQC
+ PCI_BDF(2, 4, 1) INTC PIRQC
+ PCI_BDF(2, 6, 0) INTD PIRQB
+ PCI_BDF(2, 8, 0) INTA PIRQA
+ PCI_BDF(2, 8, 1) INTA PIRQA
+ PCI_BDF(2, 8, 2) INTA PIRQA
+ PCI_BDF(2, 8, 3) INTA PIRQA
+ PCI_BDF(2, 10, 0) INTB PIRQD
+ PCI_BDF(2, 10, 1) INTB PIRQD
+ PCI_BDF(2, 10, 2) INTB PIRQD
+ PCI_BDF(2, 10, 3) INTB PIRQD
+ PCI_BDF(2, 10, 4) INTB PIRQD
+ PCI_BDF(2, 12, 0) INTC PIRQC
+ PCI_BDF(2, 12, 1) INTC PIRQC
+ PCI_BDF(2, 12, 2) INTC PIRQC
+ PCI_BDF(2, 12, 3) INTC PIRQC
+ PCI_BDF(2, 12, 4) INTC PIRQC
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "sst,25vf016b",
+ "spi-flash";
+ memory-map = <0xffe00000 0x00200000>;
+ };
+ };
};
};
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 55165e1..a2f5a1f 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -79,37 +79,59 @@
current-speed = <115200>;
};
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 8>;
- intel,pirq-mask = <0xdef8>;
- intel,pirq-routing = <
- PCI_BDF(0, 20, 0) INTA PIRQE
- PCI_BDF(0, 20, 1) INTB PIRQF
- PCI_BDF(0, 20, 2) INTC PIRQG
- PCI_BDF(0, 20, 3) INTD PIRQH
- PCI_BDF(0, 20, 4) INTA PIRQE
- PCI_BDF(0, 20, 5) INTB PIRQF
- PCI_BDF(0, 20, 6) INTC PIRQG
- PCI_BDF(0, 20, 7) INTD PIRQH
- PCI_BDF(0, 21, 0) INTA PIRQE
- PCI_BDF(0, 21, 1) INTB PIRQF
- PCI_BDF(0, 21, 2) INTC PIRQG
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 23, 1) INTB PIRQB
+ compatible = "intel,pch7";
- /* PCIe root ports downstream interrupts */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(1, 0, 0) INTB PIRQB
- PCI_BDF(1, 0, 0) INTC PIRQC
- PCI_BDF(1, 0, 0) INTD PIRQD
- PCI_BDF(2, 0, 0) INTA PIRQB
- PCI_BDF(2, 0, 0) INTB PIRQC
- PCI_BDF(2, 0, 0) INTC PIRQD
- PCI_BDF(2, 0, 0) INTD PIRQA
- >;
+ irq-router {
+ compatible = "intel,quark-irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0xdef8>;
+ intel,pirq-routing = <
+ PCI_BDF(0, 20, 0) INTA PIRQE
+ PCI_BDF(0, 20, 1) INTB PIRQF
+ PCI_BDF(0, 20, 2) INTC PIRQG
+ PCI_BDF(0, 20, 3) INTD PIRQH
+ PCI_BDF(0, 20, 4) INTA PIRQE
+ PCI_BDF(0, 20, 5) INTB PIRQF
+ PCI_BDF(0, 20, 6) INTC PIRQG
+ PCI_BDF(0, 20, 7) INTD PIRQH
+ PCI_BDF(0, 21, 0) INTA PIRQE
+ PCI_BDF(0, 21, 1) INTB PIRQF
+ PCI_BDF(0, 21, 2) INTC PIRQG
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 23, 1) INTB PIRQB
+
+ /* PCIe root ports downstream interrupts */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #size-cells = <1>;
+ #address-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x00010000 0x00010000>;
+ };
+ };
+ };
};
};
@@ -127,21 +149,4 @@
bank-name = "B";
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #size-cells = <1>;
- #address-cells = <1>;
- reg = <0>;
- compatible = "winbond,w25q64", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x00010000 0x00010000>;
- };
- };
- };
-
};
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index bbfd6d4..e7ef7c9 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -150,66 +150,91 @@
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "ibase";
- intel,ibase-offset = <0x50>;
- intel,pirq-link = <8 8>;
- intel,pirq-mask = <0xdee0>;
- intel,pirq-routing = <
- /* BayTrail PCI devices */
- PCI_BDF(0, 2, 0) INTA PIRQA
- PCI_BDF(0, 3, 0) INTA PIRQA
- PCI_BDF(0, 16, 0) INTA PIRQA
- PCI_BDF(0, 17, 0) INTA PIRQA
- PCI_BDF(0, 18, 0) INTA PIRQA
- PCI_BDF(0, 19, 0) INTA PIRQA
- PCI_BDF(0, 20, 0) INTA PIRQA
- PCI_BDF(0, 21, 0) INTA PIRQA
- PCI_BDF(0, 22, 0) INTA PIRQA
- PCI_BDF(0, 23, 0) INTA PIRQA
- PCI_BDF(0, 24, 0) INTA PIRQA
- PCI_BDF(0, 24, 1) INTC PIRQC
- PCI_BDF(0, 24, 2) INTD PIRQD
- PCI_BDF(0, 24, 3) INTB PIRQB
- PCI_BDF(0, 24, 4) INTA PIRQA
- PCI_BDF(0, 24, 5) INTC PIRQC
- PCI_BDF(0, 24, 6) INTD PIRQD
- PCI_BDF(0, 24, 7) INTB PIRQB
- PCI_BDF(0, 26, 0) INTA PIRQA
- PCI_BDF(0, 27, 0) INTA PIRQA
- PCI_BDF(0, 28, 0) INTA PIRQA
- PCI_BDF(0, 28, 1) INTB PIRQB
- PCI_BDF(0, 28, 2) INTC PIRQC
- PCI_BDF(0, 28, 3) INTD PIRQD
- PCI_BDF(0, 29, 0) INTA PIRQA
- PCI_BDF(0, 30, 0) INTA PIRQA
- PCI_BDF(0, 30, 1) INTD PIRQD
- PCI_BDF(0, 30, 2) INTB PIRQB
- PCI_BDF(0, 30, 3) INTC PIRQC
- PCI_BDF(0, 30, 4) INTD PIRQD
- PCI_BDF(0, 30, 5) INTB PIRQB
- PCI_BDF(0, 31, 3) INTB PIRQB
+ compatible = "pci8086,0f1c", "intel,pch9";
- /* PCIe root ports downstream interrupts */
- PCI_BDF(1, 0, 0) INTA PIRQA
- PCI_BDF(1, 0, 0) INTB PIRQB
- PCI_BDF(1, 0, 0) INTC PIRQC
- PCI_BDF(1, 0, 0) INTD PIRQD
- PCI_BDF(2, 0, 0) INTA PIRQB
- PCI_BDF(2, 0, 0) INTB PIRQC
- PCI_BDF(2, 0, 0) INTC PIRQD
- PCI_BDF(2, 0, 0) INTD PIRQA
- PCI_BDF(3, 0, 0) INTA PIRQC
- PCI_BDF(3, 0, 0) INTB PIRQD
- PCI_BDF(3, 0, 0) INTC PIRQA
- PCI_BDF(3, 0, 0) INTD PIRQB
- PCI_BDF(4, 0, 0) INTA PIRQD
- PCI_BDF(4, 0, 0) INTB PIRQA
- PCI_BDF(4, 0, 0) INTC PIRQB
- PCI_BDF(4, 0, 0) INTD PIRQC
- >;
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "ibase";
+ intel,ibase-offset = <0x50>;
+ intel,pirq-link = <8 8>;
+ intel,pirq-mask = <0xdee0>;
+ intel,pirq-routing = <
+ /* BayTrail PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQA
+ PCI_BDF(0, 3, 0) INTA PIRQA
+ PCI_BDF(0, 16, 0) INTA PIRQA
+ PCI_BDF(0, 17, 0) INTA PIRQA
+ PCI_BDF(0, 18, 0) INTA PIRQA
+ PCI_BDF(0, 19, 0) INTA PIRQA
+ PCI_BDF(0, 20, 0) INTA PIRQA
+ PCI_BDF(0, 21, 0) INTA PIRQA
+ PCI_BDF(0, 22, 0) INTA PIRQA
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 24, 0) INTA PIRQA
+ PCI_BDF(0, 24, 1) INTC PIRQC
+ PCI_BDF(0, 24, 2) INTD PIRQD
+ PCI_BDF(0, 24, 3) INTB PIRQB
+ PCI_BDF(0, 24, 4) INTA PIRQA
+ PCI_BDF(0, 24, 5) INTC PIRQC
+ PCI_BDF(0, 24, 6) INTD PIRQD
+ PCI_BDF(0, 24, 7) INTB PIRQB
+ PCI_BDF(0, 26, 0) INTA PIRQA
+ PCI_BDF(0, 27, 0) INTA PIRQA
+ PCI_BDF(0, 28, 0) INTA PIRQA
+ PCI_BDF(0, 28, 1) INTB PIRQB
+ PCI_BDF(0, 28, 2) INTC PIRQC
+ PCI_BDF(0, 28, 3) INTD PIRQD
+ PCI_BDF(0, 29, 0) INTA PIRQA
+ PCI_BDF(0, 30, 0) INTA PIRQA
+ PCI_BDF(0, 30, 1) INTD PIRQD
+ PCI_BDF(0, 30, 2) INTB PIRQB
+ PCI_BDF(0, 30, 3) INTC PIRQC
+ PCI_BDF(0, 30, 4) INTD PIRQD
+ PCI_BDF(0, 30, 5) INTB PIRQB
+ PCI_BDF(0, 31, 3) INTB PIRQB
+
+ /*
+ * PCIe root ports downstream
+ * interrupts
+ */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
+ PCI_BDF(3, 0, 0) INTA PIRQC
+ PCI_BDF(3, 0, 0) INTB PIRQD
+ PCI_BDF(3, 0, 0) INTC PIRQA
+ PCI_BDF(3, 0, 0) INTD PIRQB
+ PCI_BDF(4, 0, 0) INTA PIRQD
+ PCI_BDF(4, 0, 0) INTB PIRQA
+ PCI_BDF(4, 0, 0) INTC PIRQB
+ PCI_BDF(4, 0, 0) INTD PIRQC
+ >;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "stmicro,n25q064a",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x006f0000 0x00010000>;
+ };
+ };
+ };
};
};
@@ -269,23 +294,6 @@
};
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "stmicro,n25q064a", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x006f0000 0x00010000>;
- };
- };
- };
-
microcode {
update@0 {
#include "microcode/m0130673322.dtsi"
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 9086b46..9c3f2a0 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -51,18 +51,22 @@
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1,0 {
+ pch@1,0 {
reg = <0x00000800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 4>;
- intel,pirq-mask = <0x0e40>;
- intel,pirq-routing = <
- /* PIIX UHCI */
- PCI_BDF(0, 1, 2) INTD PIRQD
- /* e1000 NIC */
- PCI_BDF(0, 3, 0) INTA PIRQC
- >;
+ compatible = "intel,pch7";
+
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 4>;
+ intel,pirq-mask = <0x0e40>;
+ intel,pirq-routing = <
+ /* PIIX UHCI */
+ PCI_BDF(0, 1, 2) INTD PIRQD
+ /* e1000 NIC */
+ PCI_BDF(0, 3, 0) INTA PIRQC
+ >;
+ };
};
};
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 145e811..5d601b3 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -62,24 +62,28 @@
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "pci";
- intel,pirq-link = <0x60 8>;
- intel,pirq-mask = <0x0e40>;
- intel,pirq-routing = <
- /* e1000 NIC */
- PCI_BDF(0, 2, 0) INTA PIRQG
- /* ICH9 UHCI */
- PCI_BDF(0, 29, 0) INTA PIRQA
- PCI_BDF(0, 29, 1) INTB PIRQB
- PCI_BDF(0, 29, 2) INTC PIRQC
- /* ICH9 EHCI */
- PCI_BDF(0, 29, 7) INTD PIRQD
- /* ICH9 SATA */
- PCI_BDF(0, 31, 2) INTA PIRQA
- >;
+ compatible = "intel,pch9";
+
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "pci";
+ intel,pirq-link = <0x60 8>;
+ intel,pirq-mask = <0x0e40>;
+ intel,pirq-routing = <
+ /* e1000 NIC */
+ PCI_BDF(0, 2, 0) INTA PIRQG
+ /* ICH9 UHCI */
+ PCI_BDF(0, 29, 0) INTA PIRQA
+ PCI_BDF(0, 29, 1) INTB PIRQB
+ PCI_BDF(0, 29, 2) INTC PIRQC
+ /* ICH9 EHCI */
+ PCI_BDF(0, 29, 7) INTD PIRQD
+ /* ICH9 SATA */
+ PCI_BDF(0, 31, 2) INTA PIRQA
+ >;
+ };
};
};
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index fcdf6e2..e866580 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -7,27 +7,6 @@
#ifndef _ASM_ARCH_BD82X6X_H
#define _ASM_ARCH_BD82X6X_H
-void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
-void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
-void bd82x6x_pci_init(pci_dev_t dev);
-void bd82x6x_usb_ehci_init(pci_dev_t dev);
-void bd82x6x_usb_xhci_init(pci_dev_t dev);
-int gma_func0_init(struct udevice *dev, const void *blob, int node);
-int bd82x6x_init(void);
-
-/**
- * struct x86_cpu_priv - Information about a single CPU
- *
- * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
- * just a number representing the CPU core
- *
- * TODO: Move this to driver model once lifecycle is understood
- */
-struct x86_cpu_priv {
- int apic_id;
- int start_err;
-};
-
-int model_206ax_init(struct x86_cpu_priv *cpu);
+int gma_func0_init(struct udevice *dev);
#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h
index 3a0809d..eb1b73f 100644
--- a/arch/x86/include/asm/arch-ivybridge/me.h
+++ b/arch/x86/include/asm/arch-ivybridge/me.h
@@ -345,12 +345,47 @@
u8 reserved[3];
};
-/* Defined in me_status.c for both romstage and ramstage */
+/**
+ * intel_me_status() - Check Intel Management Engine status
+ *
+ * struct hfs: Firmware status
+ * struct gmes: Management engine status
+ */
void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
-void intel_early_me_status(void);
-int intel_early_me_init(void);
-int intel_early_me_uma_size(void);
-int intel_early_me_init_done(u8 status);
+/**
+ * intel_early_me_status() - Check early Management Engine Status
+ *
+ * @me_dev: Management engine PCI device
+ */
+void intel_early_me_status(struct udevice *me_dev);
+
+/**
+ * intel_early_me_init() - Early Intel Management Engine init
+ *
+ * @me_dev: Management engine PCI device
+ * @return 0 if OK, -ve on error
+ */
+int intel_early_me_init(struct udevice *me_dev);
+
+/**
+ * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine
+ *
+ * @me_dev: Management engine PCI device
+ * @return UMA size if OK, -EINVAL on error
+ */
+int intel_early_me_uma_size(struct udevice *me_dev);
+
+/**
+ * intel_early_me_init_done() - Complete Intel Management Engine init
+ *
+ * @dev: Northbridge device
+ * @me_dev: Management engine PCI device
+ * @status: Status result (ME_INIT_...)
+ * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT
+ * if ME did not respond
+ */
+int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
+ uint status);
#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index 31437c8..af3e8e7 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -30,11 +30,6 @@
#define SMBUS_IO_BASE 0x0400
-int pch_silicon_revision(void);
-int pch_silicon_type(void);
-int pch_silicon_supported(int type, int rev);
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
@@ -470,17 +465,23 @@
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
-int lpc_init(struct pci_controller *hose, pci_dev_t dev);
-void lpc_enable(pci_dev_t dev);
+/**
+ * pch_silicon_revision() - Read silicon device ID from the PCH
+ *
+ * @dev: PCH device
+ * @return silicon device ID
+ */
+int pch_silicon_type(struct udevice *dev);
/**
- * lpc_early_init() - set up LPC serial ports and other early things
+ * pch_pch_iobp_update() - Update a pch register
*
- * @blob: Device tree blob
- * @node: Offset of LPC node
- * @dev: PCH PCI device containing the LPC
- * @return 0 if OK, -ve on error
+ * @dev: PCH device
+ * @address: Address to update
+ * @andvalue: Value to AND with existing value
+ * @orvalue: Value to OR with existing value
*/
-int lpc_early_init(const void *blob, int node, pci_dev_t dev);
+void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
+ u32 orvalue);
#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index c960525..d137d67 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -108,12 +108,15 @@
#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x)
-int bridge_silicon_revision(void);
+/**
+ * bridge_silicon_revision() - Get the Northbridge revision
+ *
+ * @dev: Northbridge device
+ * @return revision ID (bits 3:0) and bridge ID (bits 7:4)
+ */
+int bridge_silicon_revision(struct udevice *dev);
-void northbridge_enable(pci_dev_t dev);
-void northbridge_init(pci_dev_t dev);
-
-void report_platform_info(void);
+void report_platform_info(struct udevice *dev);
void sandybridge_early_init(int chipset_type);
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index c70183c..18b0345 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -45,6 +45,17 @@
GDT_BASE_HIGH_MASK = 0xf,
};
+/*
+ * System controllers in an x86 system. We mostly need to just find these and
+ * use them on PCI. At some point these might have their own uclass (e.g.
+ * UCLASS_VIDEO for the GMA device).
+ */
+enum {
+ X86_NONE,
+ X86_SYSCON_ME, /* Intel Management Engine */
+ X86_SYSCON_GMA, /* Intel Graphics Media Accelerator */
+};
+
struct cpuid_result {
uint32_t eax;
uint32_t ebx;
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 6697da3..5b9e673 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -56,23 +56,10 @@
#define PIRQ_BITMAP 0xdef8
/**
- * cpu_irq_init() - Initialize CPU IRQ routing
+ * irq_router_common_init() - Perform common x86 interrupt init
*
- * This initializes some platform-specific registers related to IRQ routing,
- * like configuring internal PCI devices to use which PCI interrupt pin,
- * and which PCI interrupt pin is mapped to which PIRQ line. Note on some
- * platforms, such IRQ routing might be hard-coded thus cannot configure.
+ * This creates the PIRQ routing table and routes the IRQs
*/
-void cpu_irq_init(void);
-
-/**
- * pirq_init() - Initialize platform PIRQ routing
- *
- * This initializes the PIRQ routing on the platform and configures all PCI
- * devices' interrupt line register to a working IRQ number on the 8259 PIC.
- *
- * @return 0 if OK, -ve on error
- */
-int pirq_init(void);
+int irq_router_common_init(struct udevice *dev);
#endif /* _ARCH_IRQ_H_ */
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index dbf8e95..9c143ca 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -77,8 +77,6 @@
void quick_ram_check(void);
-int x86_init_cpus(void);
-
#define PCI_VGA_RAM_IMAGE_START 0xc0000
#endif /* _U_BOOT_I386_H_ */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index cd5ecb6..d9fc296 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -19,12 +19,12 @@
obj-y += mpspec.o
obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
obj-y += cmd_mtrr.o
+obj-y += northbridge-uclass.o
obj-$(CONFIG_I8259_PIC) += i8259.o
obj-$(CONFIG_I8254_TIMER) += i8254.o
ifndef CONFIG_DM_PCI
obj-$(CONFIG_PCI) += pci_type1.o
endif
-obj-y += pch-uclass.o
obj-y += pirq_routing.o
obj-y += relocate.o
obj-y += physmem.o
diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c
index f3ad116..0faa582 100644
--- a/arch/x86/lib/mpspec.c
+++ b/arch/x86/lib/mpspec.c
@@ -292,19 +292,19 @@
struct mpc_config_intsrc *intsrc_base;
int intsrc_entries = 0;
const void *blob = gd->fdt_blob;
- int node;
+ struct udevice *dev;
int len, count;
const u32 *cell;
- int i;
+ int i, ret;
- /* Get I/O interrupt information from device tree */
- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IRQ_ROUTER);
- if (node < 0) {
+ ret = uclass_first_device(UCLASS_IRQ, &dev);
+ if (ret && ret != -ENODEV) {
debug("%s: Cannot find irq router node\n", __func__);
- return -ENOENT;
+ return ret;
}
- cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
+ /* Get I/O interrupt information from device tree */
+ cell = fdt_getprop(blob, dev->of_offset, "intel,pirq-routing", &len);
if (!cell)
return -ENOENT;
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 53a1259..67bace4 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -243,8 +243,12 @@
goto err_entry;
data = (struct mrc_data_container *)gd->arch.mrc_output;
ret = mrccache_update(sf, &entry, data);
- if (!ret)
+ if (!ret) {
debug("Saved MRC data with checksum %04x\n", data->checksum);
+ } else if (ret == -EEXIST) {
+ debug("MRC data is the same as last time, skipping save\n");
+ ret = 0;
+ }
err_entry:
if (ret)
diff --git a/arch/x86/lib/northbridge-uclass.c b/arch/x86/lib/northbridge-uclass.c
new file mode 100644
index 0000000..64b6257
--- /dev/null
+++ b/arch/x86/lib/northbridge-uclass.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/root.h>
+
+UCLASS_DRIVER(northbridge) = {
+ .id = UCLASS_NORTHBRIDGE,
+ .name = "northbridge",
+};
diff --git a/arch/x86/lib/pch-uclass.c b/arch/x86/lib/pch-uclass.c
deleted file mode 100644
index 20dfa81..0000000
--- a/arch/x86/lib/pch-uclass.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <dm/root.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int pch_uclass_post_bind(struct udevice *bus)
-{
- /*
- * Scan the device tree for devices
- *
- * Before relocation, only bind devices marked for pre-relocation
- * use.
- */
- return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
- gd->flags & GD_FLG_RELOC ? false : true);
-}
-
-UCLASS_DRIVER(pch) = {
- .id = UCLASS_PCH,
- .name = "pch",
- .post_bind = pch_uclass_post_bind,
-};
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 6a8fca6..e582abb 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -16,7 +16,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
@@ -1023,10 +1022,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index f1bed51..1bd65a8 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -42,7 +42,7 @@
* The IR chip can show up under the following addresses:
* 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
* 0x09 (Verified on T1040RDB-PA)
- * 0x38 (Verified on T2080QDS, T2081QDS)
+ * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB)
*/
static int find_ir_chip_on_i2c(void)
{
@@ -292,7 +292,7 @@
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
u32 fusesr;
- u8 vid;
+ u8 vid, buf;
int vdd_target, vdd_current, vdd_last;
int ret, i2caddress;
unsigned long vdd_string_override;
@@ -346,6 +346,21 @@
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
}
+ /* check IR chip work on Intel mode*/
+ ret = i2c_read(i2caddress,
+ IR36021_INTEL_MODE_OOFSET,
+ 1, (void *)&buf, 1);
+ if (ret) {
+ printf("VID: failed to read IR chip mode.\n");
+ ret = -1;
+ goto exit;
+ }
+ if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
+ printf("VID: IR Chip is not used in Intel mode.\n");
+ ret = -1;
+ goto exit;
+ }
+
/* get the voltage ID from fuse status register */
fusesr = in_be32(&gur->dcfg_fusesr);
/*
diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h
index a9c7bb4..9182c20 100644
--- a/board/freescale/common/vid.h
+++ b/board/freescale/common/vid.h
@@ -11,6 +11,10 @@
#define IR36021_LOOP1_VOUT_OFFSET 0x9A
#define IR36021_MFR_ID_OFFSET 0x92
#define IR36021_MFR_ID 0x43
+#define IR36021_INTEL_MODE_OOFSET 0x14
+#define IR36021_MODE_MASK 0x20
+#define IR36021_INTEL_MODE 0x00
+#define IR36021_AMD_MODE 0x20
/* step the IR regulator in 5mV increments */
#define IR_VDD_STEP_DOWN 5
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 6f0fea1..f41985d 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
@@ -125,11 +124,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
return 0;
}
diff --git a/board/freescale/mx25pdk/Makefile b/board/freescale/mx25pdk/Makefile
index 0b288f2..02085b6 100644
--- a/board/freescale/mx25pdk/Makefile
+++ b/board/freescale/mx25pdk/Makefile
@@ -7,4 +7,3 @@
#
obj-y := mx25pdk.o
-obj-y += lowlevel_init.o
diff --git a/board/freescale/mx25pdk/lowlevel_init.S b/board/freescale/mx25pdk/lowlevel_init.S
deleted file mode 100644
index 8c581b5..0000000
--- a/board/freescale/mx25pdk/lowlevel_init.S
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2011 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov pc, lr
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index 01dac72..788d3c3 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -186,3 +186,6 @@
return 0;
}
+
+/* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */
+void lowlevel_init(void) {}
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index f8ae973..bbcc5bb 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -47,6 +47,9 @@
#define QSPI_PAD_CTRL \
(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
@@ -196,6 +199,38 @@
gpio_direction_output(IOX_STCP, 1);
};
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const gpmi_pads[] = {
+ MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+ /* NAND_USDHC_BUS_CLK is set in rom */
+ set_clk_nand();
+}
+#endif
+
#ifdef CONFIG_VIDEO_MXS
static iomux_v3_cfg_t const lcd_pads[] = {
MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
@@ -503,6 +538,10 @@
setup_fec();
#endif
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
#ifdef CONFIG_VIDEO_MXS
setup_lcd();
#endif
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index e600bdb..c6a7242 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
@@ -140,8 +139,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
- setup_portals();
board_config_lanes_mux();
return 0;
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
index 708afca..76793a1 100644
--- a/board/freescale/t102xqds/t102xqds.c
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
@@ -280,10 +279,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_mux_lane_to_slot();
board_retimer_ds125df111_init();
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index fddd240..01dbf38 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t102xrdb.h"
@@ -151,10 +150,6 @@
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
#ifdef CONFIG_T1024RDB
board_mux_lane();
#endif
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index eaca57f..d7d56b4 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
@@ -153,10 +152,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
return 0;
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 3227652..ec97677 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -16,7 +16,6 @@
#include <asm/fsl_fdt.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "../common/sleep.h"
@@ -84,11 +83,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
return 0;
}
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 7c89cd5..bfea3a1 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
@@ -356,11 +355,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index 0c2c1c5..0cb05aa 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t208xrdb.h"
@@ -81,11 +80,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
index 5441094..f1393f2 100644
--- a/board/freescale/t4qds/t4240emu.c
+++ b/board/freescale/t4qds/t4240emu.c
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -56,11 +55,6 @@
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
return 0;
}
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 4f2cccd..d6df144 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
@@ -552,11 +551,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index fac442b..406fb13 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -15,12 +15,12 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t4rdb.h"
#include "cpld.h"
+#include "../common/vid.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -75,10 +75,12 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
+ /*
+ * Adjust core voltage according to voltage ID
+ * This function changes I2C mux to channel 2.
+ */
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
return 0;
}
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 1b97a8f..d12d742 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -14,14 +14,6 @@
int arch_early_init_r(void)
{
- struct udevice *dev;
- int ret;
-
- /* Make sure the platform controller hub is up and running */
- ret = uclass_get_device(UCLASS_PCH, 0, &dev);
- if (ret)
- return ret;
-
return 0;
}
diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c
index 9f64945..52a1906 100644
--- a/board/renesas/sh7753evb/sh7753evb.c
+++ b/board/renesas/sh7753evb/sh7753evb.c
@@ -113,6 +113,7 @@
writel(val, ðer->malr);
}
+#if defined(CONFIG_SH_32BIT)
/*****************************************************************
* This PMB must be set on this timing. The lowlevel_init is run on
* Area 0(phys 0x00000000), so we have to map it.
@@ -154,13 +155,16 @@
writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
}
+#endif
int board_init(void)
{
struct gether_control_regs *gether = GETHER_CONTROL_BASE;
init_gpio();
+#if defined(CONFIG_SH_32BIT)
set_pmb_on_board_init();
+#endif
/* Sets TXnDLY to B'010 */
writel(0x00000202, &gether->gbecont);
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index d891a38..eca218c 100644
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -43,7 +43,7 @@
/* Local functions */
static int detect_num_flash_banks(void);
static long int get_ddr_bank_size(short cs, long *base);
-static void set_cs_bounds(short cs, long base, long size);
+static void set_cs_bounds(short cs, ulong base, ulong size);
static void set_cs_config(short cs, long config);
static void set_ddr_config(void);
@@ -314,7 +314,7 @@
/**************************************************************************
* Sets DDR bank CS bounds.
*/
-static void set_cs_bounds(short cs, long base, long size)
+static void set_cs_bounds(short cs, ulong base, ulong size)
{
debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs);
if(size == 0){
diff --git a/cmd/Kconfig b/cmd/Kconfig
new file mode 100644
index 0000000..2ed0263
--- /dev/null
+++ b/cmd/Kconfig
@@ -0,0 +1,585 @@
+menu "Command line interface"
+
+config HUSH_PARSER
+ bool "Use hush shell"
+ select SYS_HUSH_PARSER
+ help
+ This option enables the "hush" shell (from Busybox) as command line
+ interpreter, thus enabling powerful command line syntax like
+ if...then...else...fi conditionals or `&&' and '||'
+ constructs ("shell scripts").
+
+ If disabled, you get the old, much simpler behaviour with a somewhat
+ smaller memory footprint.
+
+config SYS_HUSH_PARSER
+ bool
+ help
+ Backward compatibility.
+
+config SYS_PROMPT
+ string "Shell prompt"
+ default "=> "
+ help
+ This string is displayed in the command line to the left of the
+ cursor.
+
+menu "Autoboot options"
+
+config AUTOBOOT_KEYED
+ bool "Stop autobooting via specific input key / string"
+ default n
+ help
+ This option enables stopping (aborting) of the automatic
+ boot feature only by issuing a specific input key or
+ string. If not enabled, any input key will abort the
+ U-Boot automatic booting process and bring the device
+ to the U-Boot prompt for user input.
+
+config AUTOBOOT_PROMPT
+ string "Autoboot stop prompt"
+ depends on AUTOBOOT_KEYED
+ default "Autoboot in %d seconds\\n"
+ help
+ This string is displayed before the boot delay selected by
+ CONFIG_BOOTDELAY starts. If it is not defined there is no
+ output indicating that autoboot is in progress.
+
+ Note that this define is used as the (only) argument to a
+ printf() call, so it may contain '%' format specifications,
+ provided that it also includes, sepearated by commas exactly
+ like in a printf statement, the required arguments. It is
+ the responsibility of the user to select only such arguments
+ that are valid in the given context.
+
+config AUTOBOOT_ENCRYPTION
+ bool "Enable encryption in autoboot stopping"
+ depends on AUTOBOOT_KEYED
+ default n
+
+config AUTOBOOT_DELAY_STR
+ string "Delay autobooting via specific input key / string"
+ depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
+ help
+ This option delays the automatic boot feature by issuing
+ a specific input key or string. If CONFIG_AUTOBOOT_DELAY_STR
+ or the environment variable "bootdelaykey" is specified
+ and this string is received from console input before
+ autoboot starts booting, U-Boot gives a command prompt. The
+ U-Boot prompt will time out if CONFIG_BOOT_RETRY_TIME is
+ used, otherwise it never times out.
+
+config AUTOBOOT_STOP_STR
+ string "Stop autobooting via specific input key / string"
+ depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
+ help
+ This option enables stopping (aborting) of the automatic
+ boot feature only by issuing a specific input key or
+ string. If CONFIG_AUTOBOOT_STOP_STR or the environment
+ variable "bootstopkey" is specified and this string is
+ received from console input before autoboot starts booting,
+ U-Boot gives a command prompt. The U-Boot prompt never
+ times out, even if CONFIG_BOOT_RETRY_TIME is used.
+
+config AUTOBOOT_KEYED_CTRLC
+ bool "Enable Ctrl-C autoboot interruption"
+ depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
+ default n
+ help
+ This option allows for the boot sequence to be interrupted
+ by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey".
+ Setting this variable provides an escape sequence from the
+ limited "password" strings.
+
+config AUTOBOOT_STOP_STR_SHA256
+ string "Stop autobooting via SHA256 encrypted password"
+ depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
+ help
+ This option adds the feature to only stop the autobooting,
+ and therefore boot into the U-Boot prompt, when the input
+ string / password matches a values that is encypted via
+ a SHA256 hash and saved in the environment.
+
+endmenu
+
+comment "Commands"
+
+menu "Info commands"
+
+config CMD_BDI
+ bool "bdinfo"
+ default y
+ help
+ Print board info
+
+config CMD_CONSOLE
+ bool "coninfo"
+ default y
+ help
+ Print console devices and information.
+
+config CMD_CPU
+ bool "cpu"
+ help
+ Print information about available CPUs. This normally shows the
+ number of CPUs, type (e.g. manufacturer, architecture, product or
+ internal name) and clock frequency. Other information may be
+ available depending on the CPU driver.
+
+config CMD_LICENSE
+ bool "license"
+ help
+ Print GPL license text
+
+endmenu
+
+menu "Boot commands"
+
+config CMD_BOOTD
+ bool "bootd"
+ default y
+ help
+ Run the command stored in the environment "bootcmd", i.e.
+ "bootd" does the same thing as "run bootcmd".
+
+config CMD_BOOTM
+ bool "bootm"
+ default y
+ help
+ Boot an application image from the memory.
+
+config CMD_ELF
+ bool "bootelf, bootvx"
+ default y
+ help
+ Boot an ELF/vxWorks image from the memory.
+
+config CMD_GO
+ bool "go"
+ default y
+ help
+ Start an application at a given address.
+
+config CMD_RUN
+ bool "run"
+ default y
+ help
+ Run the command in the given environment variable.
+
+config CMD_IMI
+ bool "iminfo"
+ default y
+ help
+ Print header information for application image.
+
+config CMD_IMLS
+ bool "imls"
+ default y
+ help
+ List all images found in flash
+
+config CMD_XIMG
+ bool "imxtract"
+ default y
+ help
+ Extract a part of a multi-image.
+
+config CMD_POWEROFF
+ bool
+
+endmenu
+
+menu "Environment commands"
+
+config CMD_EXPORTENV
+ bool "env export"
+ default y
+ help
+ Export environments.
+
+config CMD_IMPORTENV
+ bool "env import"
+ default y
+ help
+ Import environments.
+
+config CMD_EDITENV
+ bool "editenv"
+ default y
+ help
+ Edit environment variable.
+
+config CMD_SAVEENV
+ bool "saveenv"
+ default y
+ help
+ Save all environment variables into the compiled-in persistent
+ storage.
+
+config CMD_ENV_EXISTS
+ bool "env exists"
+ default y
+ help
+ Check if a variable is defined in the environment for use in
+ shell scripting.
+
+endmenu
+
+menu "Memory commands"
+
+config CMD_MEMORY
+ bool "md, mm, nm, mw, cp, cmp, base, loop"
+ default y
+ help
+ Memeory commands.
+ md - memory display
+ mm - memory modify (auto-incrementing address)
+ nm - memory modify (constant address)
+ mw - memory write (fill)
+ cp - memory copy
+ cmp - memory compare
+ base - print or set address offset
+ loop - initinite loop on address range
+
+config CMD_CRC32
+ bool "crc32"
+ default y
+ help
+ Compute CRC32.
+
+config LOOPW
+ bool "loopw"
+ help
+ Infinite write loop on address range
+
+config CMD_MEMTEST
+ bool "memtest"
+ help
+ Simple RAM read/write test.
+
+config CMD_MX_CYCLIC
+ bool "mdc, mwc"
+ help
+ mdc - memory display cyclic
+ mwc - memory write cyclic
+
+config CMD_MEMINFO
+ bool "meminfo"
+ help
+ Display memory information.
+
+endmenu
+
+menu "Device access commands"
+
+config CMD_DM
+ bool "dm - Access to driver model information"
+ depends on DM
+ default y
+ help
+ Provides access to driver model data structures and information,
+ such as a list of devices, list of uclasses and the state of each
+ device (e.g. activated). This is not required for operation, but
+ can be useful to see the state of driver model for debugging or
+ interest.
+
+config CMD_DEMO
+ bool "demo - Demonstration commands for driver model"
+ depends on DM
+ help
+ Provides a 'demo' command which can be used to play around with
+ driver model. To use this properly you will need to enable one or
+ both of the demo devices (DM_DEMO_SHAPE and DM_DEMO_SIMPLE).
+ Otherwise you will always get an empty list of devices. The demo
+ devices are defined in the sandbox device tree, so the easiest
+ option is to use sandbox and pass the -d point to sandbox's
+ u-boot.dtb file.
+
+config CMD_LOADB
+ bool "loadb"
+ default y
+ help
+ Load a binary file over serial line.
+
+config CMD_LOADS
+ bool "loads"
+ default y
+ help
+ Load an S-Record file over serial line
+
+config CMD_FLASH
+ bool "flinfo, erase, protect"
+ default y
+ help
+ NOR flash support.
+ flinfo - print FLASH memory information
+ erase - FLASH memory
+ protect - enable or disable FLASH write protection
+
+config CMD_ARMFLASH
+ depends on FLASH_CFI_DRIVER
+ bool "armflash"
+ help
+ ARM Ltd reference designs flash partition access
+
+config CMD_NAND
+ bool "nand"
+ help
+ NAND support.
+
+config CMD_SF
+ bool "sf"
+ help
+ SPI Flash support
+
+config CMD_SPI
+ bool "sspi"
+ help
+ SPI utility command.
+
+config CMD_I2C
+ bool "i2c"
+ help
+ I2C support.
+
+config CMD_USB
+ bool "usb"
+ help
+ USB support.
+
+config CMD_FPGA
+ bool "fpga"
+ default y
+ help
+ FPGA support.
+
+config CMD_REMOTEPROC
+ bool "remoteproc"
+ depends on REMOTEPROC
+ help
+ Support for Remote Processor control
+
+config CMD_GPIO
+ bool "gpio"
+ help
+ GPIO support.
+
+endmenu
+
+
+menu "Shell scripting commands"
+
+config CMD_ECHO
+ bool "echo"
+ default y
+ help
+ Echo args to console
+
+config CMD_ITEST
+ bool "itest"
+ default y
+ help
+ Return true/false on integer compare.
+
+config CMD_SOURCE
+ bool "source"
+ default y
+ help
+ Run script from memory
+
+config CMD_SETEXPR
+ bool "setexpr"
+ default y
+ help
+ Evaluate boolean and math expressions and store the result in an env
+ variable.
+ Also supports loading the value at a memory location into a variable.
+ If CONFIG_REGEX is enabled, setexpr also supports a gsub function.
+
+endmenu
+
+menu "Network commands"
+
+config CMD_NET
+ bool "bootp, tftpboot"
+ select NET
+ default y
+ help
+ Network commands.
+ bootp - boot image via network using BOOTP/TFTP protocol
+ tftpboot - boot image via network using TFTP protocol
+
+config CMD_TFTPPUT
+ bool "tftp put"
+ help
+ TFTP put command, for uploading files to a server
+
+config CMD_TFTPSRV
+ bool "tftpsrv"
+ help
+ Act as a TFTP server and boot the first received file
+
+config CMD_RARP
+ bool "rarpboot"
+ help
+ Boot image via network using RARP/TFTP protocol
+
+config CMD_DHCP
+ bool "dhcp"
+ help
+ Boot image via network using DHCP/TFTP protocol
+
+config CMD_NFS
+ bool "nfs"
+ default y
+ help
+ Boot image via network using NFS protocol.
+
+config CMD_PING
+ bool "ping"
+ help
+ Send ICMP ECHO_REQUEST to network host
+
+config CMD_CDP
+ bool "cdp"
+ help
+ Perform CDP network configuration
+
+config CMD_SNTP
+ bool "sntp"
+ help
+ Synchronize RTC via network
+
+config CMD_DNS
+ bool "dns"
+ help
+ Lookup the IP of a hostname
+
+config CMD_LINK_LOCAL
+ bool "linklocal"
+ help
+ Acquire a network IP address using the link-local protocol
+
+endmenu
+
+menu "Misc commands"
+
+config CMD_AMBAPP
+ bool "ambapp"
+ depends on LEON3
+ default y
+ help
+ Lists AMBA Plug-n-Play information.
+
+config SYS_AMBAPP_PRINT_ON_STARTUP
+ bool "Show AMBA PnP info on startup"
+ depends on CMD_AMBAPP
+ default n
+ help
+ Show AMBA Plug-n-Play information on startup.
+
+config CMD_TIME
+ bool "time"
+ help
+ Run commands and summarize execution time.
+
+# TODO: rename to CMD_SLEEP
+config CMD_MISC
+ bool "sleep"
+ default y
+ help
+ Delay execution for some time
+
+config CMD_TIMER
+ bool "timer"
+ help
+ Access the system timer.
+
+config CMD_SETGETDCR
+ bool "getdcr, setdcr, getidcr, setidcr"
+ depends on 4xx
+ default y
+ help
+ getdcr - Get an AMCC PPC 4xx DCR's value
+ setdcr - Set an AMCC PPC 4xx DCR's value
+ getidcr - Get a register value via indirect DCR addressing
+ setidcr - Set a register value via indirect DCR addressing
+
+config CMD_SOUND
+ bool "sound"
+ depends on SOUND
+ help
+ This provides basic access to the U-Boot's sound support. The main
+ feature is to play a beep.
+
+ sound init - set up sound system
+ sound play - play a sound
+
+endmenu
+
+config CMD_BOOTSTAGE
+ bool "Enable the 'bootstage' command"
+ depends on BOOTSTAGE
+ help
+ Add a 'bootstage' command which supports printing a report
+ and un/stashing of bootstage data.
+
+menu "Power commands"
+config CMD_PMIC
+ bool "Enable Driver Model PMIC command"
+ depends on DM_PMIC
+ help
+ This is the pmic command, based on a driver model pmic's API.
+ Command features are unchanged:
+ - list - list pmic devices
+ - pmic dev <id> - show or [set] operating pmic device (NEW)
+ - pmic dump - dump registers
+ - pmic read address - read byte of register at address
+ - pmic write address - write byte to register at address
+ The only one change for this command is 'dev' subcommand.
+
+config CMD_REGULATOR
+ bool "Enable Driver Model REGULATOR command"
+ depends on DM_REGULATOR
+ help
+ This command is based on driver model regulator's API.
+ User interface features:
+ - list - list regulator devices
+ - regulator dev <id> - show or [set] operating regulator device
+ - regulator info - print constraints info
+ - regulator status - print operating status
+ - regulator value <val] <-f> - print/[set] voltage value [uV]
+ - regulator current <val> - print/[set] current value [uA]
+ - regulator mode <id> - print/[set] operating mode id
+ - regulator enable - enable the regulator output
+ - regulator disable - disable the regulator output
+
+ The '-f' (force) option can be used for set the value which exceeds
+ the limits, which are found in device-tree and are kept in regulator's
+ uclass platdata structure.
+
+endmenu
+
+menu "Security commands"
+config CMD_TPM
+ bool "Enable the 'tpm' command"
+ depends on TPM
+ help
+ This provides a means to talk to a TPM from the command line. A wide
+ range of commands if provided - see 'tpm help' for details. The
+ command requires a suitable TPM on your board and the correct driver
+ must be enabled.
+
+config CMD_TPM_TEST
+ bool "Enable the 'tpm test' command"
+ depends on CMD_TPM
+ help
+ This provides a a series of tests to confirm that the TPM is working
+ correctly. The tests cover initialisation, non-volatile RAM, extend,
+ global lock and checking that timing is within expectations. The
+ tests pass correctly on Infineon TPMs but may need to be adjusted
+ for other devices.
+
+endmenu
+
+endmenu
diff --git a/cmd/Makefile b/cmd/Makefile
new file mode 100644
index 0000000..03f7e0a
--- /dev/null
+++ b/cmd/Makefile
@@ -0,0 +1,166 @@
+#
+# (C) Copyright 2004-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+# core command
+obj-y += boot.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-y += help.o
+obj-y += version.o
+
+# command
+obj-$(CONFIG_CMD_AES) += aes.o
+obj-$(CONFIG_CMD_AMBAPP) += ambapp.o
+obj-$(CONFIG_CMD_ARMFLASH) += armflash.o
+obj-$(CONFIG_SOURCE) += source.o
+obj-$(CONFIG_CMD_SOURCE) += source.o
+obj-$(CONFIG_CMD_BDI) += bdinfo.o
+obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
+obj-$(CONFIG_CMD_BMP) += bmp.o
+obj-$(CONFIG_CMD_BOOTMENU) += bootmenu.o
+obj-$(CONFIG_CMD_BOOTLDR) += bootldr.o
+obj-$(CONFIG_CMD_BOOTSTAGE) += bootstage.o
+obj-$(CONFIG_CMD_CACHE) += cache.o
+obj-$(CONFIG_CMD_CBFS) += cbfs.o
+obj-$(CONFIG_CMD_CLK) += clk.o
+obj-$(CONFIG_CMD_CONSOLE) += console.o
+obj-$(CONFIG_CMD_CPLBINFO) += cplbinfo.o
+obj-$(CONFIG_CMD_CPU) += cpu.o
+obj-$(CONFIG_DATAFLASH_MMC_SELECT) += dataflash_mmc_mux.o
+obj-$(CONFIG_CMD_DATE) += date.o
+obj-$(CONFIG_CMD_DEMO) += demo.o
+obj-$(CONFIG_CMD_SOUND) += sound.o
+ifdef CONFIG_4xx
+obj-$(CONFIG_CMD_SETGETDCR) += dcr.o
+endif
+ifdef CONFIG_POST
+obj-$(CONFIG_CMD_DIAG) += diag.o
+endif
+obj-$(CONFIG_CMD_DISPLAY) += display.o
+obj-$(CONFIG_CMD_DTT) += dtt.o
+obj-$(CONFIG_CMD_ECHO) += echo.o
+obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
+obj-$(CONFIG_CMD_EEPROM) += eeprom.o
+obj-$(CONFIG_EFI_STUB) += efi.o
+obj-$(CONFIG_CMD_ELF) += elf.o
+obj-$(CONFIG_SYS_HUSH_PARSER) += exit.o
+obj-$(CONFIG_CMD_EXT4) += ext4.o
+obj-$(CONFIG_CMD_EXT2) += ext2.o
+obj-$(CONFIG_CMD_FAT) += fat.o
+obj-$(CONFIG_CMD_FDC) += fdc.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_CMD_FITUPD) += fitupd.o
+obj-$(CONFIG_CMD_FLASH) += flash.o
+ifdef CONFIG_FPGA
+obj-$(CONFIG_CMD_FPGA) += fpga.o
+endif
+obj-$(CONFIG_CMD_FPGAD) += fpgad.o
+obj-$(CONFIG_CMD_FS_GENERIC) += fs.o
+obj-$(CONFIG_CMD_FUSE) += fuse.o
+obj-$(CONFIG_CMD_GETTIME) += gettime.o
+obj-$(CONFIG_CMD_GPIO) += gpio.o
+obj-$(CONFIG_CMD_I2C) += i2c.o
+obj-$(CONFIG_CMD_IOTRACE) += iotrace.o
+obj-$(CONFIG_CMD_HASH) += hash.o
+obj-$(CONFIG_CMD_IDE) += ide.o
+obj-$(CONFIG_CMD_IMMAP) += immap.o
+obj-$(CONFIG_CMD_INI) += ini.o
+obj-$(CONFIG_CMD_IRQ) += irq.o
+obj-$(CONFIG_CMD_ITEST) += itest.o
+obj-$(CONFIG_CMD_JFFS2) += jffs2.o
+obj-$(CONFIG_CMD_CRAMFS) += cramfs.o
+obj-$(CONFIG_CMD_LDRINFO) += ldrinfo.o
+obj-$(CONFIG_CMD_LED) += led.o
+obj-$(CONFIG_CMD_LICENSE) += license.o
+obj-y += load.o
+obj-$(CONFIG_LOGBUFFER) += log.o
+obj-$(CONFIG_ID_EEPROM) += mac.o
+obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
+obj-$(CONFIG_CMD_MEMORY) += mem.o
+obj-$(CONFIG_CMD_IO) += io.o
+obj-$(CONFIG_CMD_MFSL) += mfsl.o
+obj-$(CONFIG_CMD_MII) += mii.o
+ifdef CONFIG_PHYLIB
+obj-$(CONFIG_CMD_MII) += mdio.o
+endif
+obj-$(CONFIG_CMD_MISC) += misc.o
+obj-$(CONFIG_CMD_MMC) += mmc.o
+obj-$(CONFIG_CMD_MMC_SPI) += mmc_spi.o
+obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o
+obj-$(CONFIG_CMD_NAND) += nand.o
+obj-$(CONFIG_CMD_NET) += net.o
+obj-$(CONFIG_CMD_ONENAND) += onenand.o
+obj-$(CONFIG_CMD_OTP) += otp.o
+obj-$(CONFIG_CMD_PART) += part.o
+ifdef CONFIG_PCI
+obj-$(CONFIG_CMD_PCI) += pci.o
+endif
+obj-y += pcmcia.o
+obj-$(CONFIG_CMD_PORTIO) += portio.o
+obj-$(CONFIG_CMD_PXE) += pxe.o
+obj-$(CONFIG_CMD_READ) += read.o
+obj-$(CONFIG_CMD_REGINFO) += reginfo.o
+obj-$(CONFIG_CMD_REISER) += reiser.o
+obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
+obj-$(CONFIG_SANDBOX) += host.o
+obj-$(CONFIG_CMD_SATA) += sata.o
+obj-$(CONFIG_CMD_SF) += sf.o
+obj-$(CONFIG_CMD_SCSI) += scsi.o
+obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o
+obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
+obj-$(CONFIG_CMD_SOFTSWITCH) += softswitch.o
+obj-$(CONFIG_CMD_SPI) += spi.o
+obj-$(CONFIG_CMD_SPIBOOTLDR) += spibootldr.o
+obj-$(CONFIG_CMD_STRINGS) += strings.o
+obj-$(CONFIG_CMD_TERMINAL) += terminal.o
+obj-$(CONFIG_CMD_TIME) += time.o
+obj-$(CONFIG_CMD_TRACE) += trace.o
+obj-$(CONFIG_SYS_HUSH_PARSER) += test.o
+obj-$(CONFIG_CMD_TPM) += tpm.o
+obj-$(CONFIG_CMD_TPM_TEST) += tpm_test.o
+obj-$(CONFIG_CMD_TSI148) += tsi148.o
+obj-$(CONFIG_CMD_UBI) += ubi.o
+obj-$(CONFIG_CMD_UBIFS) += ubifs.o
+obj-$(CONFIG_CMD_UNIVERSE) += universe.o
+obj-$(CONFIG_CMD_UNZIP) += unzip.o
+ifdef CONFIG_LZMA
+obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o
+endif
+
+obj-$(CONFIG_CMD_USB) += usb.o
+obj-$(CONFIG_CMD_FASTBOOT) += fastboot.o
+obj-$(CONFIG_CMD_FS_UUID) += fs_uuid.o
+
+obj-$(CONFIG_CMD_USB_MASS_STORAGE) += usb_mass_storage.o
+obj-$(CONFIG_CMD_THOR_DOWNLOAD) += thordown.o
+obj-$(CONFIG_CMD_XIMG) += ximg.o
+obj-$(CONFIG_YAFFS2) += yaffs2.o
+obj-$(CONFIG_CMD_SPL) += spl.o
+obj-$(CONFIG_CMD_ZIP) += zip.o
+obj-$(CONFIG_CMD_ZFS) += zfs.o
+
+obj-$(CONFIG_CMD_DFU) += dfu.o
+obj-$(CONFIG_CMD_GPT) += gpt.o
+obj-$(CONFIG_CMD_ETHSW) += ethsw.o
+
+# Power
+obj-$(CONFIG_CMD_PMIC) += pmic.o
+obj-$(CONFIG_CMD_REGULATOR) += regulator.o
+endif # !CONFIG_SPL_BUILD
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_SATA_SUPPORT
+obj-$(CONFIG_CMD_SCSI) += scsi.o
+endif
+endif # CONFIG_SPL_BUILD
+
+obj-$(CONFIG_CMD_BLOB) += blob.o
+
+# core command
+obj-y += nvedit.o
+obj-y += disk.o
diff --git a/common/cmd_aes.c b/cmd/aes.c
similarity index 100%
rename from common/cmd_aes.c
rename to cmd/aes.c
diff --git a/common/cmd_ambapp.c b/cmd/ambapp.c
similarity index 100%
rename from common/cmd_ambapp.c
rename to cmd/ambapp.c
diff --git a/common/cmd_armflash.c b/cmd/armflash.c
similarity index 100%
rename from common/cmd_armflash.c
rename to cmd/armflash.c
diff --git a/common/cmd_bdinfo.c b/cmd/bdinfo.c
similarity index 100%
rename from common/cmd_bdinfo.c
rename to cmd/bdinfo.c
diff --git a/common/cmd_bedbug.c b/cmd/bedbug.c
similarity index 100%
rename from common/cmd_bedbug.c
rename to cmd/bedbug.c
diff --git a/common/cmd_blob.c b/cmd/blob.c
similarity index 100%
rename from common/cmd_blob.c
rename to cmd/blob.c
diff --git a/common/cmd_bmp.c b/cmd/bmp.c
similarity index 100%
rename from common/cmd_bmp.c
rename to cmd/bmp.c
diff --git a/common/cmd_boot.c b/cmd/boot.c
similarity index 100%
rename from common/cmd_boot.c
rename to cmd/boot.c
diff --git a/common/cmd_bootldr.c b/cmd/bootldr.c
similarity index 100%
rename from common/cmd_bootldr.c
rename to cmd/bootldr.c
diff --git a/common/cmd_bootm.c b/cmd/bootm.c
similarity index 100%
rename from common/cmd_bootm.c
rename to cmd/bootm.c
diff --git a/common/cmd_bootmenu.c b/cmd/bootmenu.c
similarity index 100%
rename from common/cmd_bootmenu.c
rename to cmd/bootmenu.c
diff --git a/common/cmd_bootstage.c b/cmd/bootstage.c
similarity index 100%
rename from common/cmd_bootstage.c
rename to cmd/bootstage.c
diff --git a/common/cmd_cache.c b/cmd/cache.c
similarity index 100%
rename from common/cmd_cache.c
rename to cmd/cache.c
diff --git a/common/cmd_cbfs.c b/cmd/cbfs.c
similarity index 100%
rename from common/cmd_cbfs.c
rename to cmd/cbfs.c
diff --git a/common/cmd_clk.c b/cmd/clk.c
similarity index 100%
rename from common/cmd_clk.c
rename to cmd/clk.c
diff --git a/common/cmd_console.c b/cmd/console.c
similarity index 100%
rename from common/cmd_console.c
rename to cmd/console.c
diff --git a/common/cmd_cplbinfo.c b/cmd/cplbinfo.c
similarity index 100%
rename from common/cmd_cplbinfo.c
rename to cmd/cplbinfo.c
diff --git a/common/cmd_cpu.c b/cmd/cpu.c
similarity index 100%
rename from common/cmd_cpu.c
rename to cmd/cpu.c
diff --git a/common/cmd_cramfs.c b/cmd/cramfs.c
similarity index 100%
rename from common/cmd_cramfs.c
rename to cmd/cramfs.c
diff --git a/common/cmd_dataflash_mmc_mux.c b/cmd/dataflash_mmc_mux.c
similarity index 100%
rename from common/cmd_dataflash_mmc_mux.c
rename to cmd/dataflash_mmc_mux.c
diff --git a/common/cmd_date.c b/cmd/date.c
similarity index 100%
rename from common/cmd_date.c
rename to cmd/date.c
diff --git a/common/cmd_dcr.c b/cmd/dcr.c
similarity index 100%
rename from common/cmd_dcr.c
rename to cmd/dcr.c
diff --git a/common/cmd_demo.c b/cmd/demo.c
similarity index 100%
rename from common/cmd_demo.c
rename to cmd/demo.c
diff --git a/common/cmd_dfu.c b/cmd/dfu.c
similarity index 100%
rename from common/cmd_dfu.c
rename to cmd/dfu.c
diff --git a/common/cmd_diag.c b/cmd/diag.c
similarity index 100%
rename from common/cmd_diag.c
rename to cmd/diag.c
diff --git a/common/cmd_disk.c b/cmd/disk.c
similarity index 100%
rename from common/cmd_disk.c
rename to cmd/disk.c
diff --git a/common/cmd_display.c b/cmd/display.c
similarity index 100%
rename from common/cmd_display.c
rename to cmd/display.c
diff --git a/common/cmd_dtt.c b/cmd/dtt.c
similarity index 98%
rename from common/cmd_dtt.c
rename to cmd/dtt.c
index f2e750f..dd427a3 100644
--- a/common/cmd_dtt.c
+++ b/cmd/dtt.c
@@ -12,6 +12,7 @@
#include <dtt.h>
#include <i2c.h>
#include <tmu.h>
+#include <linux/bug.h>
#if defined CONFIG_DTT_SENSORS
static unsigned long sensor_initialized;
diff --git a/common/cmd_echo.c b/cmd/echo.c
similarity index 100%
rename from common/cmd_echo.c
rename to cmd/echo.c
diff --git a/common/cmd_eeprom.c b/cmd/eeprom.c
similarity index 100%
rename from common/cmd_eeprom.c
rename to cmd/eeprom.c
diff --git a/common/cmd_efi.c b/cmd/efi.c
similarity index 100%
rename from common/cmd_efi.c
rename to cmd/efi.c
diff --git a/common/cmd_elf.c b/cmd/elf.c
similarity index 100%
rename from common/cmd_elf.c
rename to cmd/elf.c
diff --git a/common/cmd_ethsw.c b/cmd/ethsw.c
similarity index 100%
rename from common/cmd_ethsw.c
rename to cmd/ethsw.c
diff --git a/common/cmd_exit.c b/cmd/exit.c
similarity index 100%
rename from common/cmd_exit.c
rename to cmd/exit.c
diff --git a/common/cmd_ext2.c b/cmd/ext2.c
similarity index 100%
rename from common/cmd_ext2.c
rename to cmd/ext2.c
diff --git a/common/cmd_ext4.c b/cmd/ext4.c
similarity index 100%
rename from common/cmd_ext4.c
rename to cmd/ext4.c
diff --git a/common/cmd_fastboot.c b/cmd/fastboot.c
similarity index 100%
rename from common/cmd_fastboot.c
rename to cmd/fastboot.c
diff --git a/common/cmd_fat.c b/cmd/fat.c
similarity index 100%
rename from common/cmd_fat.c
rename to cmd/fat.c
diff --git a/common/cmd_fdc.c b/cmd/fdc.c
similarity index 100%
rename from common/cmd_fdc.c
rename to cmd/fdc.c
diff --git a/common/cmd_fdt.c b/cmd/fdt.c
similarity index 100%
rename from common/cmd_fdt.c
rename to cmd/fdt.c
diff --git a/common/cmd_fitupd.c b/cmd/fitupd.c
similarity index 100%
rename from common/cmd_fitupd.c
rename to cmd/fitupd.c
diff --git a/common/cmd_flash.c b/cmd/flash.c
similarity index 100%
rename from common/cmd_flash.c
rename to cmd/flash.c
diff --git a/common/cmd_fpga.c b/cmd/fpga.c
similarity index 100%
rename from common/cmd_fpga.c
rename to cmd/fpga.c
diff --git a/common/cmd_fpgad.c b/cmd/fpgad.c
similarity index 100%
rename from common/cmd_fpgad.c
rename to cmd/fpgad.c
diff --git a/common/cmd_fs.c b/cmd/fs.c
similarity index 100%
rename from common/cmd_fs.c
rename to cmd/fs.c
diff --git a/common/cmd_fs_uuid.c b/cmd/fs_uuid.c
similarity index 100%
rename from common/cmd_fs_uuid.c
rename to cmd/fs_uuid.c
diff --git a/common/cmd_fuse.c b/cmd/fuse.c
similarity index 100%
rename from common/cmd_fuse.c
rename to cmd/fuse.c
diff --git a/common/cmd_gettime.c b/cmd/gettime.c
similarity index 100%
rename from common/cmd_gettime.c
rename to cmd/gettime.c
diff --git a/common/cmd_gpio.c b/cmd/gpio.c
similarity index 100%
rename from common/cmd_gpio.c
rename to cmd/gpio.c
diff --git a/common/cmd_gpt.c b/cmd/gpt.c
similarity index 100%
rename from common/cmd_gpt.c
rename to cmd/gpt.c
diff --git a/common/cmd_hash.c b/cmd/hash.c
similarity index 100%
rename from common/cmd_hash.c
rename to cmd/hash.c
diff --git a/common/cmd_help.c b/cmd/help.c
similarity index 100%
rename from common/cmd_help.c
rename to cmd/help.c
diff --git a/common/cmd_host.c b/cmd/host.c
similarity index 100%
rename from common/cmd_host.c
rename to cmd/host.c
diff --git a/common/cmd_i2c.c b/cmd/i2c.c
similarity index 100%
rename from common/cmd_i2c.c
rename to cmd/i2c.c
diff --git a/common/cmd_ide.c b/cmd/ide.c
similarity index 100%
rename from common/cmd_ide.c
rename to cmd/ide.c
diff --git a/common/cmd_immap.c b/cmd/immap.c
similarity index 100%
rename from common/cmd_immap.c
rename to cmd/immap.c
diff --git a/common/cmd_ini.c b/cmd/ini.c
similarity index 100%
rename from common/cmd_ini.c
rename to cmd/ini.c
diff --git a/common/cmd_io.c b/cmd/io.c
similarity index 100%
rename from common/cmd_io.c
rename to cmd/io.c
diff --git a/common/cmd_iotrace.c b/cmd/iotrace.c
similarity index 100%
rename from common/cmd_iotrace.c
rename to cmd/iotrace.c
diff --git a/common/cmd_irq.c b/cmd/irq.c
similarity index 100%
rename from common/cmd_irq.c
rename to cmd/irq.c
diff --git a/common/cmd_itest.c b/cmd/itest.c
similarity index 100%
rename from common/cmd_itest.c
rename to cmd/itest.c
diff --git a/common/cmd_jffs2.c b/cmd/jffs2.c
similarity index 100%
rename from common/cmd_jffs2.c
rename to cmd/jffs2.c
diff --git a/common/cmd_ldrinfo.c b/cmd/ldrinfo.c
similarity index 100%
rename from common/cmd_ldrinfo.c
rename to cmd/ldrinfo.c
diff --git a/common/cmd_led.c b/cmd/led.c
similarity index 100%
rename from common/cmd_led.c
rename to cmd/led.c
diff --git a/common/cmd_license.c b/cmd/license.c
similarity index 100%
rename from common/cmd_license.c
rename to cmd/license.c
diff --git a/common/cmd_load.c b/cmd/load.c
similarity index 100%
rename from common/cmd_load.c
rename to cmd/load.c
diff --git a/common/cmd_log.c b/cmd/log.c
similarity index 100%
rename from common/cmd_log.c
rename to cmd/log.c
diff --git a/common/cmd_lzmadec.c b/cmd/lzmadec.c
similarity index 100%
rename from common/cmd_lzmadec.c
rename to cmd/lzmadec.c
diff --git a/common/cmd_mac.c b/cmd/mac.c
similarity index 100%
rename from common/cmd_mac.c
rename to cmd/mac.c
diff --git a/common/cmd_md5sum.c b/cmd/md5sum.c
similarity index 100%
rename from common/cmd_md5sum.c
rename to cmd/md5sum.c
diff --git a/common/cmd_mdio.c b/cmd/mdio.c
similarity index 100%
rename from common/cmd_mdio.c
rename to cmd/mdio.c
diff --git a/common/cmd_mem.c b/cmd/mem.c
similarity index 100%
rename from common/cmd_mem.c
rename to cmd/mem.c
diff --git a/common/cmd_mfsl.c b/cmd/mfsl.c
similarity index 100%
rename from common/cmd_mfsl.c
rename to cmd/mfsl.c
diff --git a/common/cmd_mii.c b/cmd/mii.c
similarity index 100%
rename from common/cmd_mii.c
rename to cmd/mii.c
diff --git a/common/cmd_misc.c b/cmd/misc.c
similarity index 100%
rename from common/cmd_misc.c
rename to cmd/misc.c
diff --git a/common/cmd_mmc.c b/cmd/mmc.c
similarity index 100%
rename from common/cmd_mmc.c
rename to cmd/mmc.c
diff --git a/common/cmd_mmc_spi.c b/cmd/mmc_spi.c
similarity index 100%
rename from common/cmd_mmc_spi.c
rename to cmd/mmc_spi.c
diff --git a/common/cmd_mp.c b/cmd/mp.c
similarity index 100%
rename from common/cmd_mp.c
rename to cmd/mp.c
diff --git a/common/cmd_mtdparts.c b/cmd/mtdparts.c
similarity index 100%
rename from common/cmd_mtdparts.c
rename to cmd/mtdparts.c
diff --git a/common/cmd_nand.c b/cmd/nand.c
similarity index 100%
rename from common/cmd_nand.c
rename to cmd/nand.c
diff --git a/common/cmd_net.c b/cmd/net.c
similarity index 100%
rename from common/cmd_net.c
rename to cmd/net.c
diff --git a/common/cmd_nvedit.c b/cmd/nvedit.c
similarity index 100%
rename from common/cmd_nvedit.c
rename to cmd/nvedit.c
diff --git a/common/cmd_onenand.c b/cmd/onenand.c
similarity index 100%
rename from common/cmd_onenand.c
rename to cmd/onenand.c
diff --git a/common/cmd_otp.c b/cmd/otp.c
similarity index 100%
rename from common/cmd_otp.c
rename to cmd/otp.c
diff --git a/common/cmd_part.c b/cmd/part.c
similarity index 100%
rename from common/cmd_part.c
rename to cmd/part.c
diff --git a/common/cmd_pci.c b/cmd/pci.c
similarity index 100%
rename from common/cmd_pci.c
rename to cmd/pci.c
diff --git a/common/cmd_pcmcia.c b/cmd/pcmcia.c
similarity index 100%
rename from common/cmd_pcmcia.c
rename to cmd/pcmcia.c
diff --git a/common/cmd_pmic.c b/cmd/pmic.c
similarity index 100%
rename from common/cmd_pmic.c
rename to cmd/pmic.c
diff --git a/common/cmd_portio.c b/cmd/portio.c
similarity index 100%
rename from common/cmd_portio.c
rename to cmd/portio.c
diff --git a/common/cmd_pxe.c b/cmd/pxe.c
similarity index 100%
rename from common/cmd_pxe.c
rename to cmd/pxe.c
diff --git a/common/cmd_read.c b/cmd/read.c
similarity index 100%
rename from common/cmd_read.c
rename to cmd/read.c
diff --git a/common/cmd_reginfo.c b/cmd/reginfo.c
similarity index 100%
rename from common/cmd_reginfo.c
rename to cmd/reginfo.c
diff --git a/common/cmd_regulator.c b/cmd/regulator.c
similarity index 100%
rename from common/cmd_regulator.c
rename to cmd/regulator.c
diff --git a/common/cmd_reiser.c b/cmd/reiser.c
similarity index 100%
rename from common/cmd_reiser.c
rename to cmd/reiser.c
diff --git a/common/cmd_remoteproc.c b/cmd/remoteproc.c
similarity index 100%
rename from common/cmd_remoteproc.c
rename to cmd/remoteproc.c
diff --git a/common/cmd_sata.c b/cmd/sata.c
similarity index 100%
rename from common/cmd_sata.c
rename to cmd/sata.c
diff --git a/common/cmd_scsi.c b/cmd/scsi.c
similarity index 100%
rename from common/cmd_scsi.c
rename to cmd/scsi.c
diff --git a/common/cmd_setexpr.c b/cmd/setexpr.c
similarity index 100%
rename from common/cmd_setexpr.c
rename to cmd/setexpr.c
diff --git a/common/cmd_sf.c b/cmd/sf.c
similarity index 100%
rename from common/cmd_sf.c
rename to cmd/sf.c
diff --git a/common/cmd_sha1sum.c b/cmd/sha1sum.c
similarity index 100%
rename from common/cmd_sha1sum.c
rename to cmd/sha1sum.c
diff --git a/common/cmd_softswitch.c b/cmd/softswitch.c
similarity index 100%
rename from common/cmd_softswitch.c
rename to cmd/softswitch.c
diff --git a/common/cmd_sound.c b/cmd/sound.c
similarity index 100%
rename from common/cmd_sound.c
rename to cmd/sound.c
diff --git a/common/cmd_source.c b/cmd/source.c
similarity index 100%
rename from common/cmd_source.c
rename to cmd/source.c
diff --git a/common/cmd_spi.c b/cmd/spi.c
similarity index 100%
rename from common/cmd_spi.c
rename to cmd/spi.c
diff --git a/common/cmd_spibootldr.c b/cmd/spibootldr.c
similarity index 100%
rename from common/cmd_spibootldr.c
rename to cmd/spibootldr.c
diff --git a/common/cmd_spl.c b/cmd/spl.c
similarity index 100%
rename from common/cmd_spl.c
rename to cmd/spl.c
diff --git a/common/cmd_strings.c b/cmd/strings.c
similarity index 100%
rename from common/cmd_strings.c
rename to cmd/strings.c
diff --git a/common/cmd_terminal.c b/cmd/terminal.c
similarity index 100%
rename from common/cmd_terminal.c
rename to cmd/terminal.c
diff --git a/common/cmd_test.c b/cmd/test.c
similarity index 100%
rename from common/cmd_test.c
rename to cmd/test.c
diff --git a/common/cmd_thordown.c b/cmd/thordown.c
similarity index 100%
rename from common/cmd_thordown.c
rename to cmd/thordown.c
diff --git a/common/cmd_time.c b/cmd/time.c
similarity index 100%
rename from common/cmd_time.c
rename to cmd/time.c
diff --git a/common/cmd_tpm.c b/cmd/tpm.c
similarity index 100%
rename from common/cmd_tpm.c
rename to cmd/tpm.c
diff --git a/common/cmd_tpm_test.c b/cmd/tpm_test.c
similarity index 100%
rename from common/cmd_tpm_test.c
rename to cmd/tpm_test.c
diff --git a/common/cmd_trace.c b/cmd/trace.c
similarity index 100%
rename from common/cmd_trace.c
rename to cmd/trace.c
diff --git a/common/cmd_tsi148.c b/cmd/tsi148.c
similarity index 100%
rename from common/cmd_tsi148.c
rename to cmd/tsi148.c
diff --git a/common/cmd_ubi.c b/cmd/ubi.c
similarity index 100%
rename from common/cmd_ubi.c
rename to cmd/ubi.c
diff --git a/common/cmd_ubifs.c b/cmd/ubifs.c
similarity index 100%
rename from common/cmd_ubifs.c
rename to cmd/ubifs.c
diff --git a/common/cmd_universe.c b/cmd/universe.c
similarity index 100%
rename from common/cmd_universe.c
rename to cmd/universe.c
diff --git a/common/cmd_unzip.c b/cmd/unzip.c
similarity index 100%
rename from common/cmd_unzip.c
rename to cmd/unzip.c
diff --git a/common/cmd_usb.c b/cmd/usb.c
similarity index 100%
rename from common/cmd_usb.c
rename to cmd/usb.c
diff --git a/common/cmd_usb_mass_storage.c b/cmd/usb_mass_storage.c
similarity index 100%
rename from common/cmd_usb_mass_storage.c
rename to cmd/usb_mass_storage.c
diff --git a/common/cmd_version.c b/cmd/version.c
similarity index 100%
rename from common/cmd_version.c
rename to cmd/version.c
diff --git a/common/cmd_ximg.c b/cmd/ximg.c
similarity index 100%
rename from common/cmd_ximg.c
rename to cmd/ximg.c
diff --git a/common/cmd_yaffs2.c b/cmd/yaffs2.c
similarity index 100%
rename from common/cmd_yaffs2.c
rename to cmd/yaffs2.c
diff --git a/common/cmd_zfs.c b/cmd/zfs.c
similarity index 100%
rename from common/cmd_zfs.c
rename to cmd/zfs.c
diff --git a/common/cmd_zip.c b/cmd/zip.c
similarity index 100%
rename from common/cmd_zip.c
rename to cmd/zip.c
diff --git a/common/Kconfig b/common/Kconfig
index 9d446bf..067545d 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1,522 +1,3 @@
-menu "Command line interface"
-
-config HUSH_PARSER
- bool "Use hush shell"
- select SYS_HUSH_PARSER
- help
- This option enables the "hush" shell (from Busybox) as command line
- interpreter, thus enabling powerful command line syntax like
- if...then...else...fi conditionals or `&&' and '||'
- constructs ("shell scripts").
-
- If disabled, you get the old, much simpler behaviour with a somewhat
- smaller memory footprint.
-
-config SYS_HUSH_PARSER
- bool
- help
- Backward compatibility.
-
-config SYS_PROMPT
- string "Shell prompt"
- default "=> "
- help
- This string is displayed in the command line to the left of the
- cursor.
-
-menu "Autoboot options"
-
-config AUTOBOOT_KEYED
- bool "Stop autobooting via specific input key / string"
- default n
- help
- This option enables stopping (aborting) of the automatic
- boot feature only by issuing a specific input key or
- string. If not enabled, any input key will abort the
- U-Boot automatic booting process and bring the device
- to the U-Boot prompt for user input.
-
-config AUTOBOOT_PROMPT
- string "Autoboot stop prompt"
- depends on AUTOBOOT_KEYED
- default "Autoboot in %d seconds\\n"
- help
- This string is displayed before the boot delay selected by
- CONFIG_BOOTDELAY starts. If it is not defined there is no
- output indicating that autoboot is in progress.
-
- Note that this define is used as the (only) argument to a
- printf() call, so it may contain '%' format specifications,
- provided that it also includes, sepearated by commas exactly
- like in a printf statement, the required arguments. It is
- the responsibility of the user to select only such arguments
- that are valid in the given context.
-
-config AUTOBOOT_ENCRYPTION
- bool "Enable encryption in autoboot stopping"
- depends on AUTOBOOT_KEYED
- default n
-
-config AUTOBOOT_DELAY_STR
- string "Delay autobooting via specific input key / string"
- depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
- help
- This option delays the automatic boot feature by issuing
- a specific input key or string. If CONFIG_AUTOBOOT_DELAY_STR
- or the environment variable "bootdelaykey" is specified
- and this string is received from console input before
- autoboot starts booting, U-Boot gives a command prompt. The
- U-Boot prompt will time out if CONFIG_BOOT_RETRY_TIME is
- used, otherwise it never times out.
-
-config AUTOBOOT_STOP_STR
- string "Stop autobooting via specific input key / string"
- depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
- help
- This option enables stopping (aborting) of the automatic
- boot feature only by issuing a specific input key or
- string. If CONFIG_AUTOBOOT_STOP_STR or the environment
- variable "bootstopkey" is specified and this string is
- received from console input before autoboot starts booting,
- U-Boot gives a command prompt. The U-Boot prompt never
- times out, even if CONFIG_BOOT_RETRY_TIME is used.
-
-config AUTOBOOT_KEYED_CTRLC
- bool "Enable Ctrl-C autoboot interruption"
- depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
- default n
- help
- This option allows for the boot sequence to be interrupted
- by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey".
- Setting this variable provides an escape sequence from the
- limited "password" strings.
-
-config AUTOBOOT_STOP_STR_SHA256
- string "Stop autobooting via SHA256 encrypted password"
- depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
- help
- This option adds the feature to only stop the autobooting,
- and therefore boot into the U-Boot prompt, when the input
- string / password matches a values that is encypted via
- a SHA256 hash and saved in the environment.
-
-endmenu
-
-comment "Commands"
-
-menu "Info commands"
-
-config CMD_BDI
- bool "bdinfo"
- default y
- help
- Print board info
-
-config CMD_CONSOLE
- bool "coninfo"
- default y
- help
- Print console devices and information.
-
-config CMD_CPU
- bool "cpu"
- help
- Print information about available CPUs. This normally shows the
- number of CPUs, type (e.g. manufacturer, architecture, product or
- internal name) and clock frequency. Other information may be
- available depending on the CPU driver.
-
-config CMD_LICENSE
- bool "license"
- help
- Print GPL license text
-
-endmenu
-
-menu "Boot commands"
-
-config CMD_BOOTD
- bool "bootd"
- default y
- help
- Run the command stored in the environment "bootcmd", i.e.
- "bootd" does the same thing as "run bootcmd".
-
-config CMD_BOOTM
- bool "bootm"
- default y
- help
- Boot an application image from the memory.
-
-config CMD_ELF
- bool "bootelf, bootvx"
- default y
- help
- Boot an ELF/vxWorks image from the memory.
-
-config CMD_GO
- bool "go"
- default y
- help
- Start an application at a given address.
-
-config CMD_RUN
- bool "run"
- default y
- help
- Run the command in the given environment variable.
-
-config CMD_IMI
- bool "iminfo"
- default y
- help
- Print header information for application image.
-
-config CMD_IMLS
- bool "imls"
- default y
- help
- List all images found in flash
-
-config CMD_XIMG
- bool "imxtract"
- default y
- help
- Extract a part of a multi-image.
-
-config CMD_POWEROFF
- bool
-
-endmenu
-
-menu "Environment commands"
-
-config CMD_EXPORTENV
- bool "env export"
- default y
- help
- Export environments.
-
-config CMD_IMPORTENV
- bool "env import"
- default y
- help
- Import environments.
-
-config CMD_EDITENV
- bool "editenv"
- default y
- help
- Edit environment variable.
-
-config CMD_SAVEENV
- bool "saveenv"
- default y
- help
- Save all environment variables into the compiled-in persistent
- storage.
-
-config CMD_ENV_EXISTS
- bool "env exists"
- default y
- help
- Check if a variable is defined in the environment for use in
- shell scripting.
-
-endmenu
-
-menu "Memory commands"
-
-config CMD_MEMORY
- bool "md, mm, nm, mw, cp, cmp, base, loop"
- default y
- help
- Memeory commands.
- md - memory display
- mm - memory modify (auto-incrementing address)
- nm - memory modify (constant address)
- mw - memory write (fill)
- cp - memory copy
- cmp - memory compare
- base - print or set address offset
- loop - initinite loop on address range
-
-config CMD_CRC32
- bool "crc32"
- default y
- help
- Compute CRC32.
-
-config LOOPW
- bool "loopw"
- help
- Infinite write loop on address range
-
-config CMD_MEMTEST
- bool "memtest"
- help
- Simple RAM read/write test.
-
-config CMD_MX_CYCLIC
- bool "mdc, mwc"
- help
- mdc - memory display cyclic
- mwc - memory write cyclic
-
-config CMD_MEMINFO
- bool "meminfo"
- help
- Display memory information.
-
-endmenu
-
-menu "Device access commands"
-
-config CMD_DM
- bool "dm - Access to driver model information"
- depends on DM
- default y
- help
- Provides access to driver model data structures and information,
- such as a list of devices, list of uclasses and the state of each
- device (e.g. activated). This is not required for operation, but
- can be useful to see the state of driver model for debugging or
- interest.
-
-config CMD_DEMO
- bool "demo - Demonstration commands for driver model"
- depends on DM
- help
- Provides a 'demo' command which can be used to play around with
- driver model. To use this properly you will need to enable one or
- both of the demo devices (DM_DEMO_SHAPE and DM_DEMO_SIMPLE).
- Otherwise you will always get an empty list of devices. The demo
- devices are defined in the sandbox device tree, so the easiest
- option is to use sandbox and pass the -d point to sandbox's
- u-boot.dtb file.
-
-config CMD_LOADB
- bool "loadb"
- default y
- help
- Load a binary file over serial line.
-
-config CMD_LOADS
- bool "loads"
- default y
- help
- Load an S-Record file over serial line
-
-config CMD_FLASH
- bool "flinfo, erase, protect"
- default y
- help
- NOR flash support.
- flinfo - print FLASH memory information
- erase - FLASH memory
- protect - enable or disable FLASH write protection
-
-config CMD_ARMFLASH
- depends on FLASH_CFI_DRIVER
- bool "armflash"
- help
- ARM Ltd reference designs flash partition access
-
-config CMD_NAND
- bool "nand"
- help
- NAND support.
-
-config CMD_SF
- bool "sf"
- help
- SPI Flash support
-
-config CMD_SPI
- bool "sspi"
- help
- SPI utility command.
-
-config CMD_I2C
- bool "i2c"
- help
- I2C support.
-
-config CMD_USB
- bool "usb"
- help
- USB support.
-
-config CMD_FPGA
- bool "fpga"
- default y
- help
- FPGA support.
-
-config CMD_REMOTEPROC
- bool "remoteproc"
- depends on REMOTEPROC
- help
- Support for Remote Processor control
-
-config CMD_GPIO
- bool "gpio"
- help
- GPIO support.
-
-endmenu
-
-
-menu "Shell scripting commands"
-
-config CMD_ECHO
- bool "echo"
- default y
- help
- Echo args to console
-
-config CMD_ITEST
- bool "itest"
- default y
- help
- Return true/false on integer compare.
-
-config CMD_SOURCE
- bool "source"
- default y
- help
- Run script from memory
-
-config CMD_SETEXPR
- bool "setexpr"
- default y
- help
- Evaluate boolean and math expressions and store the result in an env
- variable.
- Also supports loading the value at a memory location into a variable.
- If CONFIG_REGEX is enabled, setexpr also supports a gsub function.
-
-endmenu
-
-menu "Network commands"
-
-config CMD_NET
- bool "bootp, tftpboot"
- select NET
- default y
- help
- Network commands.
- bootp - boot image via network using BOOTP/TFTP protocol
- tftpboot - boot image via network using TFTP protocol
-
-config CMD_TFTPPUT
- bool "tftp put"
- help
- TFTP put command, for uploading files to a server
-
-config CMD_TFTPSRV
- bool "tftpsrv"
- help
- Act as a TFTP server and boot the first received file
-
-config CMD_RARP
- bool "rarpboot"
- help
- Boot image via network using RARP/TFTP protocol
-
-config CMD_DHCP
- bool "dhcp"
- help
- Boot image via network using DHCP/TFTP protocol
-
-config CMD_NFS
- bool "nfs"
- default y
- help
- Boot image via network using NFS protocol.
-
-config CMD_PING
- bool "ping"
- help
- Send ICMP ECHO_REQUEST to network host
-
-config CMD_CDP
- bool "cdp"
- help
- Perform CDP network configuration
-
-config CMD_SNTP
- bool "sntp"
- help
- Synchronize RTC via network
-
-config CMD_DNS
- bool "dns"
- help
- Lookup the IP of a hostname
-
-config CMD_LINK_LOCAL
- bool "linklocal"
- help
- Acquire a network IP address using the link-local protocol
-
-endmenu
-
-menu "Misc commands"
-
-config CMD_AMBAPP
- bool "ambapp"
- depends on LEON3
- default y
- help
- Lists AMBA Plug-n-Play information.
-
-config SYS_AMBAPP_PRINT_ON_STARTUP
- bool "Show AMBA PnP info on startup"
- depends on CMD_AMBAPP
- default n
- help
- Show AMBA Plug-n-Play information on startup.
-
-config CMD_TIME
- bool "time"
- help
- Run commands and summarize execution time.
-
-# TODO: rename to CMD_SLEEP
-config CMD_MISC
- bool "sleep"
- default y
- help
- Delay execution for some time
-
-config CMD_TIMER
- bool "timer"
- help
- Access the system timer.
-
-config CMD_SETGETDCR
- bool "getdcr, setdcr, getidcr, setidcr"
- depends on 4xx
- default y
- help
- getdcr - Get an AMCC PPC 4xx DCR's value
- setdcr - Set an AMCC PPC 4xx DCR's value
- getidcr - Get a register value via indirect DCR addressing
- setidcr - Set a register value via indirect DCR addressing
-
-config CMD_SOUND
- bool "sound"
- depends on SOUND
- help
- This provides basic access to the U-Boot's sound support. The main
- feature is to play a beep.
-
- sound init - set up sound system
- sound play - play a sound
-
-endmenu
-
menu "Boot timing"
config BOOTSTAGE
@@ -565,13 +46,6 @@
a new ID will be allocated from this stash. If you exceed
the limit, recording will stop.
-config CMD_BOOTSTAGE
- bool "Enable the 'bootstage' command"
- depends on BOOTSTAGE
- help
- Add a 'bootstage' command which supports printing a report
- and un/stashing of bootstage data.
-
config BOOTSTAGE_FDT
bool "Store boot timing information in the OS device tree"
depends on BOOTSTAGE
@@ -623,66 +97,6 @@
endmenu
-menu "Power commands"
-config CMD_PMIC
- bool "Enable Driver Model PMIC command"
- depends on DM_PMIC
- help
- This is the pmic command, based on a driver model pmic's API.
- Command features are unchanged:
- - list - list pmic devices
- - pmic dev <id> - show or [set] operating pmic device (NEW)
- - pmic dump - dump registers
- - pmic read address - read byte of register at address
- - pmic write address - write byte to register at address
- The only one change for this command is 'dev' subcommand.
-
-config CMD_REGULATOR
- bool "Enable Driver Model REGULATOR command"
- depends on DM_REGULATOR
- help
- This command is based on driver model regulator's API.
- User interface features:
- - list - list regulator devices
- - regulator dev <id> - show or [set] operating regulator device
- - regulator info - print constraints info
- - regulator status - print operating status
- - regulator value <val] <-f> - print/[set] voltage value [uV]
- - regulator current <val> - print/[set] current value [uA]
- - regulator mode <id> - print/[set] operating mode id
- - regulator enable - enable the regulator output
- - regulator disable - disable the regulator output
-
- The '-f' (force) option can be used for set the value which exceeds
- the limits, which are found in device-tree and are kept in regulator's
- uclass platdata structure.
-
-endmenu
-
-menu "Security commands"
-config CMD_TPM
- bool "Enable the 'tpm' command"
- depends on TPM
- help
- This provides a means to talk to a TPM from the command line. A wide
- range of commands if provided - see 'tpm help' for details. The
- command requires a suitable TPM on your board and the correct driver
- must be enabled.
-
-config CMD_TPM_TEST
- bool "Enable the 'tpm test' command"
- depends on CMD_TPM
- help
- This provides a a series of tests to confirm that the TPM is working
- correctly. The tests cover initialisation, non-volatile RAM, extend,
- global lock and checking that timing is within expectations. The
- tests pass correctly on Infineon TPMs but may need to be adjusted
- for other devices.
-
-endmenu
-
-endmenu
-
config CONSOLE_RECORD
bool "Console recording"
help
diff --git a/common/Makefile b/common/Makefile
index 2492275..5998411 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -31,11 +31,7 @@
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o
-# core command
-obj-y += cmd_boot.o
-obj-$(CONFIG_CMD_BOOTM) += cmd_bootm.o bootm.o bootm_os.o
-obj-y += cmd_help.o
-obj-y += cmd_version.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o bootm_os.o
# environment
obj-y += env_attr.o
@@ -58,143 +54,17 @@
obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
-# command
-obj-$(CONFIG_CMD_AES) += cmd_aes.o
-obj-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o
-obj-$(CONFIG_CMD_ARMFLASH) += cmd_armflash.o
-obj-$(CONFIG_SOURCE) += cmd_source.o
-obj-$(CONFIG_CMD_SOURCE) += cmd_source.o
-obj-$(CONFIG_CMD_BDI) += cmd_bdinfo.o
-obj-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
-obj-$(CONFIG_CMD_BMP) += cmd_bmp.o
-obj-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o
-obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
-obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
-obj-$(CONFIG_CMD_CACHE) += cmd_cache.o
-obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
-obj-$(CONFIG_CMD_CLK) += cmd_clk.o
-obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o
-obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
-obj-$(CONFIG_CMD_CPU) += cmd_cpu.o
-obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
-obj-$(CONFIG_CMD_DATE) += cmd_date.o
-obj-$(CONFIG_CMD_DEMO) += cmd_demo.o
-obj-$(CONFIG_CMD_SOUND) += cmd_sound.o
-ifdef CONFIG_4xx
-obj-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
-endif
-ifdef CONFIG_POST
-obj-$(CONFIG_CMD_DIAG) += cmd_diag.o
-endif
-obj-$(CONFIG_CMD_DISPLAY) += cmd_display.o
-obj-$(CONFIG_CMD_DTT) += cmd_dtt.o
-obj-$(CONFIG_CMD_ECHO) += cmd_echo.o
-obj-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o
-obj-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o
-obj-$(CONFIG_EFI_STUB) += cmd_efi.o
-obj-$(CONFIG_CMD_ELF) += cmd_elf.o
-obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o
-obj-$(CONFIG_CMD_EXT4) += cmd_ext4.o
-obj-$(CONFIG_CMD_EXT2) += cmd_ext2.o
-obj-$(CONFIG_CMD_FAT) += cmd_fat.o
-obj-$(CONFIG_CMD_FDC) += cmd_fdc.o
-obj-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
-obj-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o
-obj-$(CONFIG_CMD_FLASH) += cmd_flash.o
-ifdef CONFIG_FPGA
-obj-$(CONFIG_CMD_FPGA) += cmd_fpga.o
-endif
-obj-$(CONFIG_CMD_FPGAD) += cmd_fpgad.o
-obj-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
-obj-$(CONFIG_CMD_FUSE) += cmd_fuse.o
-obj-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
-obj-$(CONFIG_CMD_GPIO) += cmd_gpio.o
-obj-$(CONFIG_CMD_I2C) += cmd_i2c.o
-obj-$(CONFIG_CMD_IOTRACE) += cmd_iotrace.o
-obj-$(CONFIG_CMD_HASH) += cmd_hash.o
-obj-$(CONFIG_CMD_IDE) += cmd_ide.o
-obj-$(CONFIG_CMD_IMMAP) += cmd_immap.o
-obj-$(CONFIG_CMD_INI) += cmd_ini.o
-obj-$(CONFIG_CMD_IRQ) += cmd_irq.o
-obj-$(CONFIG_CMD_ITEST) += cmd_itest.o
-obj-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
-obj-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o
-obj-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o
-obj-$(CONFIG_CMD_LED) += cmd_led.o
-obj-$(CONFIG_CMD_LICENSE) += cmd_license.o
-obj-y += cmd_load.o
-obj-$(CONFIG_LOGBUFFER) += cmd_log.o
-obj-$(CONFIG_ID_EEPROM) += cmd_mac.o
-obj-$(CONFIG_CMD_MD5SUM) += cmd_md5sum.o
-obj-$(CONFIG_CMD_MEMORY) += cmd_mem.o
-obj-$(CONFIG_CMD_IO) += cmd_io.o
-obj-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
+obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
+obj-$(CONFIG_OF_LIBFDT) += fdt_support.o
+
obj-$(CONFIG_MII) += miiphyutil.o
obj-$(CONFIG_CMD_MII) += miiphyutil.o
obj-$(CONFIG_PHYLIB) += miiphyutil.o
-obj-$(CONFIG_CMD_MII) += cmd_mii.o
-ifdef CONFIG_PHYLIB
-obj-$(CONFIG_CMD_MII) += cmd_mdio.o
-endif
-obj-$(CONFIG_CMD_MISC) += cmd_misc.o
-obj-$(CONFIG_CMD_MMC) += cmd_mmc.o
-obj-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
-obj-$(CONFIG_MP) += cmd_mp.o
-obj-$(CONFIG_CMD_MTDPARTS) += cmd_mtdparts.o
-obj-$(CONFIG_CMD_NAND) += cmd_nand.o
-obj-$(CONFIG_CMD_NET) += cmd_net.o
-obj-$(CONFIG_CMD_ONENAND) += cmd_onenand.o
-obj-$(CONFIG_CMD_OTP) += cmd_otp.o
-obj-$(CONFIG_CMD_PART) += cmd_part.o
-ifdef CONFIG_PCI
-obj-$(CONFIG_CMD_PCI) += cmd_pci.o
-endif
-obj-y += cmd_pcmcia.o
-obj-$(CONFIG_CMD_PORTIO) += cmd_portio.o
-obj-$(CONFIG_CMD_PXE) += cmd_pxe.o
-obj-$(CONFIG_CMD_READ) += cmd_read.o
-obj-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o
-obj-$(CONFIG_CMD_REISER) += cmd_reiser.o
-obj-$(CONFIG_CMD_REMOTEPROC) += cmd_remoteproc.o
-obj-$(CONFIG_SANDBOX) += cmd_host.o
-obj-$(CONFIG_CMD_SATA) += cmd_sata.o
-obj-$(CONFIG_CMD_SF) += cmd_sf.o
-obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o
-obj-$(CONFIG_CMD_SHA1SUM) += cmd_sha1sum.o
-obj-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o
-obj-$(CONFIG_CMD_SOFTSWITCH) += cmd_softswitch.o
-obj-$(CONFIG_CMD_SPI) += cmd_spi.o
-obj-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o
-obj-$(CONFIG_CMD_STRINGS) += cmd_strings.o
-obj-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
-obj-$(CONFIG_CMD_TIME) += cmd_time.o
-obj-$(CONFIG_CMD_TRACE) += cmd_trace.o
-obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o
-obj-$(CONFIG_CMD_TPM) += cmd_tpm.o
-obj-$(CONFIG_CMD_TPM_TEST) += cmd_tpm_test.o
-obj-$(CONFIG_CMD_TSI148) += cmd_tsi148.o
-obj-$(CONFIG_CMD_UBI) += cmd_ubi.o
-obj-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
-obj-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
-obj-$(CONFIG_CMD_UNZIP) += cmd_unzip.o
-ifdef CONFIG_LZMA
-obj-$(CONFIG_CMD_LZMADEC) += cmd_lzmadec.o
-endif
+
ifdef CONFIG_CMD_USB
-obj-y += cmd_usb.o
obj-y += usb.o usb_hub.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
-obj-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o
-obj-$(CONFIG_CMD_FS_UUID) += cmd_fs_uuid.o
-
-obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
-obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o
-obj-$(CONFIG_CMD_XIMG) += cmd_ximg.o
-obj-$(CONFIG_YAFFS2) += cmd_yaffs2.o
-obj-$(CONFIG_CMD_SPL) += cmd_spl.o
-obj-$(CONFIG_CMD_ZIP) += cmd_zip.o
-obj-$(CONFIG_CMD_ZFS) += cmd_zfs.o
# others
obj-$(CONFIG_BOOTSTAGE) += bootstage.o
@@ -216,14 +86,8 @@
obj-$(CONFIG_UPDATE_TFTP) += update.o
obj-$(CONFIG_DFU_TFTP) += update.o
obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
-obj-$(CONFIG_CMD_DFU) += cmd_dfu.o
-obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
-obj-$(CONFIG_CMD_ETHSW) += cmd_ethsw.o
-# Power
-obj-$(CONFIG_CMD_PMIC) += cmd_pmic.o
-obj-$(CONFIG_CMD_REGULATOR) += cmd_regulator.o
-endif
+endif # !CONFIG_SPL_BUILD
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
@@ -234,9 +98,6 @@
obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
-ifdef CONFIG_SPL_SATA_SUPPORT
-obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o
-endif
# environment
ifdef CONFIG_SPL_ENV_SUPPORT
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
@@ -250,8 +111,6 @@
obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
endif
endif
-# core command
-obj-y += cmd_nvedit.o
#environment
obj-y += env_common.o
#others
@@ -289,8 +148,6 @@
endif
endif
-obj-$(CONFIG_CMD_BLOB) += cmd_blob.o
-
# We always have this since drivers/ddr/fs/interactive.c needs it
obj-y += cli_simple.o
@@ -299,6 +156,5 @@
obj-y += command.o
obj-y += s_record.o
obj-y += xyzModem.o
-obj-y += cmd_disk.o
CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null)
diff --git a/common/bootm.c b/common/bootm.c
index 58936ca..99d574d 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -435,7 +435,7 @@
bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
return err;
}
- flush_cache(load, (*load_end - load) * sizeof(ulong));
+ flush_cache(load, *load_end - load);
debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end);
bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED);
diff --git a/common/console.c b/common/console.c
index bc37b6d..b3f5fdc 100644
--- a/common/console.c
+++ b/common/console.c
@@ -227,11 +227,6 @@
}
}
-static inline void console_printdevs(int file)
-{
- iomux_printdevs(file);
-}
-
static inline void console_doenv(int file, struct stdio_dev *dev)
{
iomux_doenv(file, dev->name);
@@ -265,11 +260,6 @@
stdio_devices[file]->puts(stdio_devices[file], s);
}
-static inline void console_printdevs(int file)
-{
- printf("%s\n", stdio_devices[file]->name);
-}
-
static inline void console_doenv(int file, struct stdio_dev *dev)
{
console_setfile(file, dev);
@@ -653,44 +643,6 @@
ctrlc_was_pressed = 0;
}
-#ifdef CONFIG_MODEM_SUPPORT_DEBUG
-char screen[1024];
-char *cursor = screen;
-int once = 0;
-inline void dbg(const char *fmt, ...)
-{
- va_list args;
- uint i;
- char printbuffer[CONFIG_SYS_PBSIZE];
-
- if (!once) {
- memset(screen, 0, sizeof(screen));
- once++;
- }
-
- va_start(args, fmt);
-
- /* For this to work, printbuffer must be larger than
- * anything we ever want to print.
- */
- i = vsnprintf(printbuffer, sizeof(printbuffer), fmt, args);
- va_end(args);
-
- if ((screen + sizeof(screen) - 1 - cursor)
- < strlen(printbuffer) + 1) {
- memset(screen, 0, sizeof(screen));
- cursor = screen;
- }
- sprintf(cursor, printbuffer);
- cursor += strlen(printbuffer);
-
-}
-#else
-static inline void dbg(const char *fmt, ...)
-{
-}
-#endif
-
/** U-Boot INIT FUNCTIONS *************************************************/
struct stdio_dev *search_device(int flags, const char *name)
diff --git a/common/env_mmc.c b/common/env_mmc.c
index 15aa43d..bdb452e 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -54,6 +54,11 @@
return 0;
}
+__weak int mmc_get_env_dev(void)
+{
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+
int env_init(void)
{
/* use default */
@@ -74,7 +79,7 @@
static int mmc_set_env_part(struct mmc *mmc)
{
uint part = mmc_get_env_part(mmc);
- int dev = CONFIG_SYS_MMC_ENV_DEV;
+ int dev = mmc_get_env_dev();
int ret = 0;
#ifdef CONFIG_SPL_BUILD
@@ -109,7 +114,7 @@
static void fini_mmc_for_env(struct mmc *mmc)
{
#ifdef CONFIG_SYS_MMC_ENV_PART
- int dev = CONFIG_SYS_MMC_ENV_DEV;
+ int dev = mmc_get_env_dev();
#ifdef CONFIG_SPL_BUILD
dev = 0;
@@ -140,7 +145,8 @@
int saveenv(void)
{
ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
- struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ int dev = mmc_get_env_dev();
+ struct mmc *mmc = find_mmc_device(dev);
u32 offset;
int ret, copy = 0;
const char *errmsg;
@@ -167,8 +173,7 @@
goto fini;
}
- printf("Writing to %sMMC(%d)... ", copy ? "redundant " : "",
- CONFIG_SYS_MMC_ENV_DEV);
+ printf("Writing to %sMMC(%d)... ", copy ? "redundant " : "", dev);
if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)env_new)) {
puts("failed\n");
ret = 1;
@@ -212,7 +217,7 @@
int crc1_ok = 0, crc2_ok = 0;
env_t *ep;
int ret;
- int dev = CONFIG_SYS_MMC_ENV_DEV;
+ int dev = mmc_get_env_dev();
const char *errmsg = NULL;
ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env1, 1);
@@ -298,7 +303,7 @@
struct mmc *mmc;
u32 offset;
int ret;
- int dev = CONFIG_SYS_MMC_ENV_DEV;
+ int dev = mmc_get_env_dev();
const char *errmsg;
#ifdef CONFIG_SPL_BUILD
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index cbb1995..d84865f 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -199,7 +199,7 @@
}
}
- if ((scancode > 0x1d) && (scancode < 0x3a)) {
+ if ((scancode > 0x1d) && (scancode < 0x39)) {
/* Shift pressed */
if (modifier & (LEFT_SHIFT | RIGHT_SHIFT))
keycode = usb_kbd_numkey_shifted[scancode - 0x1e];
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index baa0ed8..1cee7d4 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -1,11 +1,14 @@
CONFIG_X86=y
CONFIG_SYS_MALLOC_F_LEN=0x1800
+CONFIG_DM_I2C=y
CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_TARGET_CHROMEBOOK_LINK=y
CONFIG_HAVE_MRC=y
CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
+CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -17,6 +20,10 @@
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_SYS_I2C_INTEL=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
@@ -34,6 +41,8 @@
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index c368cc0..e4a3821 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -16,6 +16,8 @@
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
@@ -29,6 +31,8 @@
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
diff --git a/doc/device-tree-bindings/serial/8250.txt b/doc/device-tree-bindings/serial/8250.txt
new file mode 100644
index 0000000..91d5ab0
--- /dev/null
+++ b/doc/device-tree-bindings/serial/8250.txt
@@ -0,0 +1,66 @@
+* UART (Universal Asynchronous Receiver/Transmitter)
+
+Required properties:
+- compatible : one of:
+ - "ns8250"
+ - "ns16450"
+ - "ns16550a"
+ - "ns16550"
+ - "ns16750"
+ - "ns16850"
+ - For Tegra20, must contain "nvidia,tegra20-uart"
+ - For other Tegra, must contain '"nvidia,<chip>-uart",
+ "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
+ tegra132, or tegra210.
+ - "nxp,lpc3220-uart"
+ - "ralink,rt2880-uart"
+ - "ibm,qpace-nwp-serial"
+ - "altr,16550-FIFO32"
+ - "altr,16550-FIFO64"
+ - "altr,16550-FIFO128"
+ - "fsl,16550-FIFO64"
+ - "fsl,ns16550"
+ - "serial" if the port type is unknown.
+- reg : offset and length of the register set for the device.
+- interrupts : should contain uart interrupt.
+- clock-frequency : the input clock frequency for the UART
+ or
+ clocks phandle to refer to the clk used as per Documentation/devicetree
+ /bindings/clock/clock-bindings.txt
+
+Optional properties:
+- current-speed : the current active speed of the UART.
+- reg-offset : offset to apply to the mapbase from the start of the registers.
+- reg-shift : quantity to shift the register offsets by.
+- reg-io-width : the size (in bytes) of the IO accesses that should be
+ performed on the device. There are some systems that require 32-bit
+ accesses to the UART (e.g. TI davinci).
+- used-by-rtas : set to indicate that the port is in use by the OpenFirmware
+ RTAS and should not be registered.
+- no-loopback-test: set to indicate that the port does not implements loopback
+ test mode
+- fifo-size: the fifo size of the UART.
+- auto-flow-control: one way to enable automatic flow control support. The
+ driver is allowed to detect support for the capability even without this
+ property.
+
+Note:
+* fsl,ns16550:
+ ------------
+ Freescale DUART is very similar to the PC16552D (and to a
+ pair of NS16550A), albeit with some nonstandard behavior such as
+ erratum A-004737 (relating to incorrect BRK handling).
+
+ Represents a single port that is compatible with the DUART found
+ on many Freescale chips (examples include mpc8349, mpc8548,
+ mpc8641d, p4080 and ls2085a).
+
+Example:
+
+ uart@80230000 {
+ compatible = "ns8250";
+ reg = <0x80230000 0x100>;
+ clock-frequency = <3686400>;
+ interrupts = <10>;
+ reg-shift = <2>;
+ };
diff --git a/doc/device-tree-bindings/serial/ns16550.txt b/doc/device-tree-bindings/serial/ns16550.txt
deleted file mode 100644
index ef0b9ae..0000000
--- a/doc/device-tree-bindings/serial/ns16550.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-NS16550 UART
-
-This UART driver supports many chip variants and is used in mamy SoCs.
-
-Required properties:
-- compatible: "ns16550" or "nvidia,tegra20-uart"
-- reg: start address and size of registers
-- reg-shift: shift value indicating register size: 0=byte, 1=16bit,2=32bit etc.
-- clock-frequency: input clock frequency for the UART (used to calculate the
- baud rate divisor)
diff --git a/doc/device-tree-bindings/serial/omap_serial.txt b/doc/device-tree-bindings/serial/omap_serial.txt
new file mode 100644
index 0000000..7a71b5d
--- /dev/null
+++ b/doc/device-tree-bindings/serial/omap_serial.txt
@@ -0,0 +1,33 @@
+OMAP UART controller
+
+Required properties:
+- compatible : should be "ti,omap2-uart" for OMAP2 controllers
+- compatible : should be "ti,omap3-uart" for OMAP3 controllers
+- compatible : should be "ti,omap4-uart" for OMAP4 controllers
+- compatible : should be "ti,am4372-uart" for AM437x controllers
+- compatible : should be "ti,am3352-uart" for AM335x controllers
+- compatible : should be "ti,dra742-uart" for DRA7x controllers
+- reg : address and length of the register space
+- interrupts or interrupts-extended : Should contain the uart interrupt
+ specifier or both the interrupt
+ controller phandle and interrupt
+ specifier.
+- ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
+
+Optional properties:
+- clock-frequency : frequency of the clock input to the UART
+- dmas : DMA specifier, consisting of a phandle to the DMA controller
+ node and a DMA channel number.
+- dma-names : "rx" for receive channel, "tx" for transmit channel.
+
+Example:
+
+ uart4: serial@49042000 {
+ compatible = "ti,omap3-uart";
+ reg = <0x49042000 0x400>;
+ interrupts = <80>;
+ dmas = <&sdma 81 &sdma 82>;
+ dma-names = "tx", "rx";
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
diff --git a/doc/device-tree-bindings/serial/snps-dw-apb-uart.txt b/doc/device-tree-bindings/serial/snps-dw-apb-uart.txt
new file mode 100644
index 0000000..12bbe9f
--- /dev/null
+++ b/doc/device-tree-bindings/serial/snps-dw-apb-uart.txt
@@ -0,0 +1,76 @@
+* Synopsys DesignWare ABP UART
+
+Required properties:
+- compatible : "snps,dw-apb-uart"
+- reg : offset and length of the register set for the device.
+- interrupts : should contain uart interrupt.
+
+Clock handling:
+The clock rate of the input clock needs to be supplied by one of
+- clock-frequency : the input clock frequency for the UART.
+- clocks : phandle to the input clock
+
+The supplying peripheral clock can also be handled, needing a second property
+- clock-names: tuple listing input clock names.
+ Required elements: "baudclk", "apb_pclk"
+
+Optional properties:
+- snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE
+ configuration parameter. Define this if your UART does not implement the busy
+ functionality.
+- resets : phandle to the parent reset controller.
+- reg-shift : quantity to shift the register offsets by. If this property is
+ not present then the register offsets are not shifted.
+- reg-io-width : the size (in bytes) of the IO accesses that should be
+ performed on the device. If this property is not present then single byte
+ accesses are used.
+- dcd-override : Override the DCD modem status signal. This signal will always
+ be reported as active instead of being obtained from the modem status
+ register. Define this if your serial port does not use this pin.
+- dsr-override : Override the DTS modem status signal. This signal will always
+ be reported as active instead of being obtained from the modem status
+ register. Define this if your serial port does not use this pin.
+- cts-override : Override the CTS modem status signal. This signal will always
+ be reported as active instead of being obtained from the modem status
+ register. Define this if your serial port does not use this pin.
+- ri-override : Override the RI modem status signal. This signal will always be
+ reported as inactive instead of being obtained from the modem status register.
+ Define this if your serial port does not use this pin.
+
+Example:
+
+ uart@80230000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x80230000 0x100>;
+ clock-frequency = <3686400>;
+ interrupts = <10>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dcd-override;
+ dsr-override;
+ cts-override;
+ ri-override;
+ };
+
+Example with one clock:
+
+ uart@80230000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x80230000 0x100>;
+ clocks = <&baudclk>;
+ interrupts = <10>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+Example with two clocks:
+
+ uart@80230000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x80230000 0x100>;
+ clocks = <&baudclk>, <&apb_pclk>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <10>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
diff --git a/drivers/Makefile b/drivers/Makefile
index 00da40b..6294048 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -51,6 +51,7 @@
obj-y += misc/
obj-y += pcmcia/
obj-y += dfu/
+obj-$(CONFIG_X86) += pch/
obj-y += rtc/
obj-y += sound/
obj-y += timer/
diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c
index dec6230..7717246 100644
--- a/drivers/bios_emulator/atibios.c
+++ b/drivers/bios_emulator/atibios.c
@@ -226,11 +226,19 @@
at this stage the controller has its I/O and memory space enabled and
that all other controllers are in a disabled state.
****************************************************************************/
+#ifdef CONFIG_DM_PCI
+static void PCI_doBIOSPOST(struct udevice *pcidev, BE_VGAInfo *vga_info,
+ int vesa_mode, struct vbe_mode_info *mode_info)
+#else
static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
int vesa_mode, struct vbe_mode_info *mode_info)
+#endif
{
RMREGS regs;
RMSREGS sregs;
+#ifdef CONFIG_DM_PCI
+ pci_dev_t bdf;
+#endif
/* Determine the value to store in AX for BIOS POST. Per the PCI specs,
AH must contain the bus and AL must contain the devfn, encoded as
@@ -238,9 +246,14 @@
*/
memset(®s, 0, sizeof(regs));
memset(&sregs, 0, sizeof(sregs));
+#ifdef CONFIG_DM_PCI
+ bdf = dm_pci_get_bdf(pcidev);
+ regs.x.ax = (int)PCI_BUS(bdf) << 8 |
+ (int)PCI_DEV(bdf) << 3 | (int)PCI_FUNC(bdf);
+#else
regs.x.ax = ((int)PCI_BUS(pcidev) << 8) |
((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev);
-
+#endif
/*Setup the X86 emulator for the VGA BIOS*/
BE_setVGA(vga_info);
@@ -281,15 +294,28 @@
it programmed to all 1's. It must be restored to the correct value
later.
****************************************************************************/
+#ifdef CONFIG_DM_PCI
+static u32 PCI_findBIOSAddr(struct udevice *pcidev, int *bar)
+#else
static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar)
+#endif
{
u32 base, size;
for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) {
+#ifdef CONFIG_DM_PCI
+ dm_pci_read_config32(pcidev, *bar, &base);
+#else
pci_read_config_dword(pcidev, *bar, &base);
+#endif
if (!(base & 0x1)) {
+#ifdef CONFIG_DM_PCI
+ dm_pci_write_config32(pcidev, *bar, 0xFFFFFFFF);
+ dm_pci_read_config32(pcidev, *bar, &size);
+#else
pci_write_config_dword(pcidev, *bar, 0xFFFFFFFF);
pci_read_config_dword(pcidev, *bar, &size);
+#endif
size = ~(size & ~0xFF) + 1;
if (size >= MAX_BIOSLEN)
return base & ~0xFF;
@@ -312,11 +338,19 @@
Anyway to fix this we change all I/O mapped base registers and
chop off the top bits.
****************************************************************************/
+#ifdef CONFIG_DM_PCI
+static void PCI_fixupIObase(struct udevice *pcidev, int reg, u32 *base)
+#else
static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base)
+#endif
{
if ((*base & 0x1) && (*base > 0xFFFE)) {
*base &= 0xFFFF;
+#ifdef CONFIG_DM_PCI
+ dm_pci_write_config32(pcidev, reg, *base);
+#else
pci_write_config_dword(pcidev, reg, *base);
+#endif
}
}
@@ -331,18 +365,30 @@
REMARKS:
Maps a pointer to the BIOS image on the graphics card on the PCI bus.
****************************************************************************/
+#ifdef CONFIG_DM_PCI
+void *PCI_mapBIOSImage(struct udevice *pcidev)
+#else
void *PCI_mapBIOSImage(pci_dev_t pcidev)
+#endif
{
u32 BIOSImageBus;
int BIOSImageBAR;
u8 *BIOSImage;
/*Save PCI BAR registers that might get changed*/
+#ifdef CONFIG_DM_PCI
+ dm_pci_read_config32(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
+ dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
+ dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
+ dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
+ dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
+#else
pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
+#endif
/*Fix up I/O base registers to less than 64K */
if(saveBaseAddress14 != 0)
@@ -361,13 +407,21 @@
return NULL;
}
+#ifdef CONFIG_DM_PCI
+ BIOSImage = dm_pci_bus_to_virt(pcidev, BIOSImageBus,
+ PCI_REGION_MEM, 0, MAP_NOCACHE);
+
+ /*Change the PCI BAR registers to map it onto the bus.*/
+ dm_pci_write_config32(pcidev, BIOSImageBAR, 0);
+ dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
+#else
BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus,
PCI_REGION_MEM, 0, MAP_NOCACHE);
/*Change the PCI BAR registers to map it onto the bus.*/
pci_write_config_dword(pcidev, BIOSImageBAR, 0);
pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
-
+#endif
udelay(1);
/*Check that the BIOS image is valid. If not fail, or return the
@@ -387,6 +441,16 @@
REMARKS:
Unmaps the BIOS image for the device and restores framebuffer mappings
****************************************************************************/
+#ifdef CONFIG_DM_PCI
+void PCI_unmapBIOSImage(struct udevice *pcidev, void *BIOSImage)
+{
+ dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
+ dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10);
+ dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14);
+ dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
+ dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
+}
+#else
void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage)
{
pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
@@ -395,6 +459,7 @@
pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
}
+#endif
/****************************************************************************
PARAMETERS:
@@ -408,13 +473,22 @@
Loads and POST's the display controllers BIOS, directly from the BIOS
image we can extract over the PCI bus.
****************************************************************************/
+#ifdef CONFIG_DM_PCI
+static int PCI_postController(struct udevice *pcidev, uchar *bios_rom,
+ int bios_len, BE_VGAInfo *vga_info,
+ int vesa_mode, struct vbe_mode_info *mode_info)
+#else
static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
BE_VGAInfo *vga_info, int vesa_mode,
struct vbe_mode_info *mode_info)
+#endif
{
u32 bios_image_len;
uchar *mapped_bios;
uchar *copy_of_bios;
+#ifdef CONFIG_DM_PCI
+ pci_dev_t bdf;
+#endif
if (bios_rom) {
copy_of_bios = bios_rom;
@@ -442,9 +516,16 @@
}
/*Save information in vga_info structure*/
+#ifdef CONFIG_DM_PCI
+ bdf = dm_pci_get_bdf(pcidev);
+ vga_info->function = PCI_FUNC(bdf);
+ vga_info->device = PCI_DEV(bdf);
+ vga_info->bus = PCI_BUS(bdf);
+#else
vga_info->function = PCI_FUNC(pcidev);
vga_info->device = PCI_DEV(pcidev);
vga_info->bus = PCI_BUS(pcidev);
+#endif
vga_info->pcidev = pcidev;
vga_info->BIOSImage = copy_of_bios;
vga_info->BIOSImageLen = bios_image_len;
@@ -462,13 +543,22 @@
return true;
}
+#ifdef CONFIG_DM_PCI
+int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **vga_infop)
+#else
int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop)
+#endif
{
BE_VGAInfo *VGAInfo;
+#ifdef CONFIG_DM_PCI
+ pci_dev_t bdf = dm_pci_get_bdf(pcidev);
printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
- PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev));
-
+ PCI_BUS(bdf), PCI_FUNC(bdf), PCI_DEV(bdf));
+#else
+ printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
+ PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev));
+#endif
/*Initialise the x86 BIOS emulator*/
if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) {
printf("videoboot: Out of memory!\n");
@@ -486,9 +576,15 @@
X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func);
}
+#ifdef CONFIG_DM_PCI
+int biosemu_run(struct udevice *pcidev, uchar *bios_rom, int bios_len,
+ BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+ struct vbe_mode_info *mode_info)
+#else
int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
struct vbe_mode_info *mode_info)
+#endif
{
/*Post all the display controller BIOS'es*/
if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info,
@@ -522,7 +618,12 @@
Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
and the X86 BIOS emulator module.
****************************************************************************/
+#ifdef CONFIG_DM_PCI
+int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
+ int clean_up)
+#else
int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up)
+#endif
{
BE_VGAInfo *VGAInfo;
int ret;
diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c
index dd4c0a4..77c7f94 100644
--- a/drivers/bios_emulator/bios.c
+++ b/drivers/bios_emulator/bios.c
@@ -185,12 +185,21 @@
case 0xB103: /* Find PCI class code */
M.x86.R_AH = DEVICE_NOT_FOUND;
#ifdef __KERNEL__
+#ifdef CONFIG_DM_PCI
+ dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG,
+ &interface);
+ dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE,
+ &subclass);
+ dm_pci_read_config8(_BE_env.vgaInfo.pcidev,
+ PCI_CLASS_DEVICE + 1, &baseclass);
+#else
pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG,
&interface);
pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE,
&subclass);
pci_read_config_byte(_BE_env.vgaInfo.pcidev,
PCI_CLASS_DEVICE + 1, &baseclass);
+#endif
if (M.x86.R_CL == interface && M.x86.R_CH == subclass
&& (u8) (M.x86.R_ECX >> 16) == baseclass) {
#else
@@ -209,8 +218,13 @@
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
+# ifdef CONFIG_DM_PCI
+ dm_pci_read_config8(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
+ &M.x86.R_CL);
+# else
pci_read_config_byte(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
&M.x86.R_CL);
+# endif
#else
M.x86.R_CL =
(u8) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_BYTE,
@@ -224,8 +238,13 @@
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
+# ifdef CONFIG_DM_PCI
+ dm_pci_read_config16(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
+ &M.x86.R_CX);
+# else
pci_read_config_word(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
&M.x86.R_CX);
+# endif
#else
M.x86.R_CX =
(u16) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_WORD,
@@ -239,8 +258,13 @@
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
+# ifdef CONFIG_DM_PCI
+ dm_pci_read_config32(_BE_env.vgaInfo.pcidev,
+ M.x86.R_DI, &M.x86.R_ECX);
+# else
pci_read_config_dword(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, &M.x86.R_ECX);
+# endif
#else
M.x86.R_ECX =
(u32) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_DWORD,
@@ -254,8 +278,13 @@
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
+# ifdef CONFIG_DM_PCI
+ dm_pci_write_config8(_BE_env.vgaInfo.pcidev,
+ M.x86.R_DI, M.x86.R_CL);
+# else
pci_write_config_byte(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, M.x86.R_CL);
+# endif
#else
PCI_accessReg(M.x86.R_DI, M.x86.R_CL, PCI_WRITE_BYTE,
_BE_env.vgaInfo.pciInfo);
@@ -268,8 +297,13 @@
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
+# ifdef CONFIG_DM_PCI
+ dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
+ M.x86.R_DI, M.x86.R_CX);
+# else
pci_write_config_word(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, M.x86.R_CX);
+# endif
#else
PCI_accessReg(M.x86.R_DI, M.x86.R_CX, PCI_WRITE_WORD,
_BE_env.vgaInfo.pciInfo);
@@ -282,8 +316,13 @@
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
+# ifdef CONFIG_DM_PCI
+ dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
+ M.x86.R_DI, M.x86.R_ECX);
+# else
pci_write_config_dword(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, M.x86.R_ECX);
+# endif
#else
PCI_accessReg(M.x86.R_DI, M.x86.R_ECX, PCI_WRITE_DWORD,
_BE_env.vgaInfo.pciInfo);
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index e69de29..990f768 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -0,0 +1,9 @@
+config DISK
+ bool "Support disk controllers with driver model"
+ depends on DM
+ default y if DM
+ help
+ This enables a uclass for disk controllers in U-Boot. Various driver
+ types can use this, such as AHCI/SATA. It does not provide any standard
+ operations at present. The block device interface has not been converted
+ to driver model.
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index eb8bda9..5eb87e0 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -5,6 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_DISK) += disk-uclass.o
obj-$(CONFIG_SCSI_AHCI) += ahci.o
obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
diff --git a/drivers/block/disk-uclass.c b/drivers/block/disk-uclass.c
new file mode 100644
index 0000000..d665b35
--- /dev/null
+++ b/drivers/block/disk-uclass.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+
+UCLASS_DRIVER(disk) = {
+ .id = UCLASS_DISK,
+ .name = "disk",
+};
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index a1c9478..c4fc216 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -172,7 +172,8 @@
dm_dbg(" - found match at '%s'\n", entry->name);
ret = device_bind(parent, entry, name, NULL, offset, &dev);
if (ret) {
- dm_warn("Error binding driver '%s'\n", entry->name);
+ dm_warn("Error binding driver '%s': %d\n", entry->name,
+ ret);
return ret;
} else {
dev->driver_data = id->data;
diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index 686c320..a0666d0 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -32,7 +32,7 @@
return regmap_init_mem(dev, &priv->regmap);
}
-struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data)
+int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
{
struct udevice *dev;
struct uclass *uc;
@@ -40,22 +40,29 @@
ret = uclass_get(UCLASS_SYSCON, &uc);
if (ret)
- return ERR_PTR(ret);
+ return ret;
uclass_foreach_dev(dev, uc) {
if (dev->driver_data == driver_data) {
- struct syscon_uc_info *priv;
- int ret;
-
- ret = device_probe(dev);
- if (ret)
- return ERR_PTR(ret);
- priv = dev_get_uclass_priv(dev);
-
- return priv->regmap;
+ *devp = dev;
+ return device_probe(dev);
}
}
- return ERR_PTR(-ENODEV);
+ return -ENODEV;
+}
+
+struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data)
+{
+ struct syscon_uc_info *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = syscon_get_by_driver_data(driver_data, &dev);
+ if (ret)
+ return ERR_PTR(ret);
+ priv = dev_get_uclass_priv(dev);
+
+ return priv->regmap;
}
void *syscon_get_first_range(ulong driver_data)
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 22defcd..a6dc935 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -215,7 +215,7 @@
#if defined(CONFIG_MX23)
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
#endif
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 3ed4d89..d603b55 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -10,6 +10,7 @@
#include <fdtdec.h>
#include <malloc.h>
#include <asm/gpio.h>
+#include <linux/bug.h>
#include <linux/ctype.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 14adda2..46b83e7 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -58,6 +58,15 @@
bindings are supported.
Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
+config SYS_I2C_INTEL
+ bool "Intel I2C/SMBUS driver"
+ depends on DM_I2C
+ help
+ Add support for the Intel SMBUS driver. So far this driver is just
+ a stub which perhaps some basic init. There is no implementation of
+ the I2C API meaning that any I2C operations will immediately fail
+ for now.
+
config SYS_I2C_ROCKCHIP
bool "Rockchip I2C driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index bbbc0dc..c75c579 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -21,6 +21,7 @@
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
+obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c
new file mode 100644
index 0000000..3d777ff
--- /dev/null
+++ b/drivers/i2c/intel_i2c.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/pch.h>
+
+int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ return -ENOSYS;
+}
+
+int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, uint chip_flags)
+{
+ return -ENOSYS;
+}
+
+int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ return 0;
+}
+
+static int intel_i2c_probe(struct udevice *dev)
+{
+ /*
+ * So far this is just setup code for ivybridge SMbus. When we have
+ * a full I2C driver this may need to be moved, generalised or made
+ * dependant on a particular compatible string.
+ *
+ * Set SMBus I/O base
+ */
+ dm_pci_write_config32(dev, SMB_BASE,
+ SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+ /* Set SMBus enable. */
+ dm_pci_write_config8(dev, HOSTC, HST_EN);
+
+ /* Set SMBus I/O space enable. */
+ dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+
+ /* Disable interrupt generation. */
+ outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+ /* Clear any lingering errors, so transactions can run. */
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+ debug("SMBus controller enabled\n");
+
+ return 0;
+}
+
+static const struct dm_i2c_ops intel_i2c_ops = {
+ .xfer = intel_i2c_xfer,
+ .probe_chip = intel_i2c_probe_chip,
+ .set_bus_speed = intel_i2c_set_bus_speed,
+};
+
+static const struct udevice_id intel_i2c_ids[] = {
+ { .compatible = "intel,ich-i2c" },
+ { }
+};
+
+U_BOOT_DRIVER(intel_i2c) = {
+ .name = "i2c_intel",
+ .id = UCLASS_I2C,
+ .of_match = intel_i2c_ids,
+ .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
+ .ops = &intel_i2c_ops,
+ .probe = intel_i2c_probe,
+};
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index f15cf36..ba019a0 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -30,7 +30,7 @@
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
-#if defined(CONFIG_MX6)
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
#else
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
@@ -152,7 +152,7 @@
int max_ecc_strength_supported;
/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
- if (is_cpu_type(MXC_CPU_MX6SX))
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
max_ecc_strength_supported = 62;
else
max_ecc_strength_supported = 40;
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index f484e62..baf4e2d 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -30,6 +30,7 @@
#include <linux/slab.h>
#include <linux/major.h>
#else
+#include <linux/bug.h>
#include <linux/log2.h>
#endif
#include <linux/err.h>
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index f2cd32c..d4a6386 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -240,23 +240,23 @@
static inline int INW (struct eth_device *dev, u_long addr)
{
- return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase));
+ return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase));
}
static inline void OUTW (struct eth_device *dev, int command, u_long addr)
{
- *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command);
+ *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command);
}
static inline void OUTL (struct eth_device *dev, int command, u_long addr)
{
- *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
+ *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command);
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
static inline int INL (struct eth_device *dev, u_long addr)
{
- return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase));
+ return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase));
}
static int get_phyreg (struct eth_device *dev, unsigned char addr,
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index bac4610..4b9b372 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
#include <errno.h>
+#include <linux/bug.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 7059c84..97e30f3 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -19,6 +19,7 @@
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
+#include <wait_bit.h>
#include <watchdog.h>
#include <asm/system.h>
#include <asm/arch/hardware.h>
@@ -448,38 +449,6 @@
return 0;
}
-static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
- bool set, unsigned int timeout)
-{
- u32 val;
- unsigned long start = get_timer(0);
-
- while (1) {
- val = readl(reg);
-
- if (!set)
- val = ~val;
-
- if ((val & mask) == mask)
- return 0;
-
- if (get_timer(start) > timeout)
- break;
-
- if (ctrlc()) {
- puts("Abort\n");
- return -EINTR;
- }
-
- udelay(1);
- }
-
- debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
- func, reg, mask, set);
-
- return -ETIMEDOUT;
-}
-
static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
{
u32 addr, size;
@@ -521,7 +490,7 @@
printf("TX buffers exhausted in mid frame\n");
return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE,
- true, 20000);
+ true, 20000, true);
}
/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
new file mode 100644
index 0000000..dde9e86
--- /dev/null
+++ b/drivers/pch/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += pch-uclass.o
+obj-y += pch7.o
+obj-y += pch9.o
diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c
new file mode 100644
index 0000000..4579ed1
--- /dev/null
+++ b/drivers/pch/pch-uclass.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+#include <dm/root.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int pch_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+ struct pch_ops *ops = pch_get_ops(dev);
+
+ *sbasep = 0;
+ if (!ops->get_sbase)
+ return -ENOSYS;
+
+ return ops->get_sbase(dev, sbasep);
+}
+
+enum pch_version pch_get_version(struct udevice *dev)
+{
+ struct pch_ops *ops = pch_get_ops(dev);
+
+ if (!ops->get_version)
+ return -ENOSYS;
+
+ return ops->get_version(dev);
+}
+
+int pch_set_spi_protect(struct udevice *dev, bool protect)
+{
+ struct pch_ops *ops = pch_get_ops(dev);
+
+ if (!ops->set_spi_protect)
+ return -ENOSYS;
+
+ return ops->set_spi_protect(dev, protect);
+}
+
+static int pch_uclass_post_bind(struct udevice *bus)
+{
+ /*
+ * Scan the device tree for devices
+ *
+ * Before relocation, only bind devices marked for pre-relocation
+ * use.
+ */
+ return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
+ gd->flags & GD_FLG_RELOC ? false : true);
+}
+
+UCLASS_DRIVER(pch) = {
+ .id = UCLASS_PCH,
+ .name = "pch",
+ .post_bind = pch_uclass_post_bind,
+};
diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c
new file mode 100644
index 0000000..ef72422
--- /dev/null
+++ b/drivers/pch/pch7.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+
+#define BIOS_CTRL 0xd8
+
+static int pch7_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+ u32 rcba;
+
+ dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+ /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
+ rcba = rcba & 0xffffc000;
+ *sbasep = rcba + 0x3020;
+
+ return 0;
+}
+
+static enum pch_version pch7_get_version(struct udevice *dev)
+{
+ return PCHV_7;
+}
+
+static int pch7_set_spi_protect(struct udevice *dev, bool protect)
+{
+ uint8_t bios_cntl;
+
+ /* Adjust the BIOS write protect to dis/allow write commands */
+ dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
+ if (protect)
+ bios_cntl &= ~BIOS_CTRL_BIOSWE;
+ else
+ bios_cntl |= BIOS_CTRL_BIOSWE;
+ dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
+
+ return 0;
+}
+
+static const struct pch_ops pch7_ops = {
+ .get_sbase = pch7_get_sbase,
+ .get_version = pch7_get_version,
+ .set_spi_protect = pch7_set_spi_protect,
+};
+
+static const struct udevice_id pch7_ids[] = {
+ { .compatible = "intel,pch7" },
+ { }
+};
+
+U_BOOT_DRIVER(pch7_drv) = {
+ .name = "intel-pch7",
+ .id = UCLASS_PCH,
+ .of_match = pch7_ids,
+ .ops = &pch7_ops,
+};
diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c
new file mode 100644
index 0000000..529cb02
--- /dev/null
+++ b/drivers/pch/pch9.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+
+#define SBASE_ADDR 0x54
+
+static int pch9_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+ uint32_t sbase_addr;
+
+ dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
+ *sbasep = sbase_addr & 0xfffffe00;
+
+ return 0;
+}
+
+static enum pch_version pch9_get_version(struct udevice *dev)
+{
+ return PCHV_9;
+}
+
+static const struct pch_ops pch9_ops = {
+ .get_sbase = pch9_get_sbase,
+ .get_version = pch9_get_version,
+};
+
+static const struct udevice_id pch9_ids[] = {
+ { .compatible = "intel,pch9" },
+ { }
+};
+
+U_BOOT_DRIVER(pch9_drv) = {
+ .name = "intel-pch9",
+ .id = UCLASS_PCH,
+ .of_match = pch9_ids,
+ .ops = &pch9_ops,
+};
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 685df9d..61292d7 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -22,7 +22,7 @@
DECLARE_GLOBAL_DATA_PTR;
-static int pci_get_bus(int busnum, struct udevice **busp)
+int pci_get_bus(int busnum, struct udevice **busp)
{
int ret;
@@ -41,20 +41,6 @@
return ret;
}
-struct pci_controller *pci_bus_to_hose(int busnum)
-{
- struct udevice *bus;
- int ret;
-
- ret = pci_get_bus(busnum, &bus);
- if (ret) {
- debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
- return NULL;
- }
-
- return dev_get_uclass_priv(bus);
-}
-
struct udevice *pci_get_controller(struct udevice *dev)
{
while (device_is_on_pci_bus(dev))
@@ -1067,6 +1053,14 @@
return addr & PCI_BASE_ADDRESS_MEM_MASK;
}
+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
+{
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ dm_pci_write_config32(dev, bar, addr);
+}
+
static int _dm_pci_bus_to_phys(struct udevice *ctlr,
pci_addr_t bus_addr, unsigned long flags,
unsigned long skip_mask, phys_addr_t *pa)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 5cfa135..88bc416 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <pci.h>
@@ -167,8 +168,8 @@
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
u16 cmdstat, prefechable_64;
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
pci_mem = ctlr_hose->pci_mem;
pci_prefetch = ctlr_hose->pci_prefetch;
@@ -248,9 +249,8 @@
struct pci_region *pci_mem;
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
-
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
pci_mem = ctlr_hose->pci_mem;
pci_prefetch = ctlr_hose->pci_prefetch;
@@ -311,13 +311,13 @@
unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
unsigned short class;
bool enum_only = false;
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
int n;
#ifdef CONFIG_PCI_ENUM_ONLY
enum_only = true;
#endif
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
pci_mem = ctlr_hose->pci_mem;
pci_prefetch = ctlr_hose->pci_prefetch;
diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c
index dd15eb1..ddaf358 100644
--- a/drivers/pci/pci_compat.c
+++ b/drivers/pci/pci_compat.c
@@ -12,6 +12,7 @@
#include <pci.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
+#include "pci_internal.h"
#define PCI_HOSE_OP(rw, name, size, type) \
int pci_hose_##rw##_config_##name(struct pci_controller *hose, \
@@ -36,3 +37,17 @@
return -1;
return dm_pci_get_bdf(dev);
}
+
+struct pci_controller *pci_bus_to_hose(int busnum)
+{
+ struct udevice *bus;
+ int ret;
+
+ ret = pci_get_bus(busnum, &bus);
+ if (ret) {
+ debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
+ return NULL;
+ }
+
+ return dev_get_uclass_priv(bus);
+}
diff --git a/drivers/pci/pci_internal.h b/drivers/pci/pci_internal.h
index 0867575..616b9c1 100644
--- a/drivers/pci/pci_internal.h
+++ b/drivers/pci/pci_internal.h
@@ -47,4 +47,16 @@
*/
int dm_pciauto_config_device(struct udevice *dev);
+/**
+ * pci_get_bus() - Get a pointer to a bus, given its number
+ *
+ * This looks up a PCI bus based on its bus number. The bus is probed if
+ * necessary.
+ *
+ * @busnum: PCI bus number to look up
+ * @busp: Returns PCI bus on success
+ * @return 0 on success, or -ve error
+ */
+int pci_get_bus(int busnum, struct udevice **busp);
+
#endif
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index ed2f61d..d5bf6f4 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -328,12 +328,12 @@
#ifdef CONFIG_BIOSEMU
BE_VGAInfo *info;
- ret = biosemu_setup(dm_pci_get_bdf(dev), &info);
+ ret = biosemu_setup(dev, &info);
if (ret)
goto err;
biosemu_set_interrupt_handler(0x15, int15_handler);
- ret = biosemu_run(dm_pci_get_bdf(dev), (uchar *)ram, 1 << 16,
- info, true, vesa_mode, &mode_info);
+ ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
+ true, vesa_mode, &mode_info);
if (ret)
goto err;
#endif
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 7eaec6a..6bdebf2 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -7,9 +7,7 @@
#ifndef __PINCTRL_UNIPHIER_H__
#define __PINCTRL_UNIPHIER_H__
-/* TODO: move this to include/linux/bug.h */
-#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:-!!(e); }))
-
+#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/types.h>
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 021b211..93dad33 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -423,11 +423,15 @@
};
#if CONFIG_IS_ENABLED(OF_CONTROL)
+/*
+ * Please consider existing compatible strings before adding a new
+ * one to keep this table compact. Or you may add a generic "ns16550"
+ * compatible string to your dts.
+ */
static const struct udevice_id ns16550_serial_ids[] = {
{ .compatible = "ns16550" },
{ .compatible = "ns16550a" },
{ .compatible = "nvidia,tegra20-uart" },
- { .compatible = "rockchip,rk3036-uart" },
{ .compatible = "snps,dw-apb-uart" },
{ .compatible = "ti,omap2-uart" },
{ .compatible = "ti,omap3-uart" },
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 799ef6a..fcb1e95 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -127,11 +127,6 @@
NS16550_putc(PORT, c);
}
-static void _serial_putc_raw(const char c, const int port)
-{
- NS16550_putc(PORT, c);
-}
-
static void _serial_puts(const char *s, const int port)
{
while (*s) {
@@ -165,12 +160,6 @@
}
static inline void
-serial_putc_raw_dev(unsigned int dev_index,const char c)
-{
- _serial_putc_raw(c,dev_index);
-}
-
-static inline void
serial_puts_dev(unsigned int dev_index,const char *s)
{
_serial_puts(s,dev_index);
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 59eaaea..e543b8f 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -5,14 +5,14 @@
*
* This file is derived from the flashrom project.
*/
-
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
-#include <spi.h>
+#include <pch.h>
#include <pci.h>
#include <pci_ids.h>
+#include <spi.h>
#include <asm/io.h>
#include "ich.h"
@@ -20,10 +20,14 @@
#define SPI_OPCODE_WREN 0x06
#define SPI_OPCODE_FAST_READ 0x0b
+#ifdef DEBUG_TRACE
+#define debug_trace(fmt, args...) debug(fmt, ##args)
+#else
+#define debug_trace(x, args...)
+#endif
+
struct ich_spi_platdata {
- pci_dev_t dev; /* PCI device number */
- int ich_version; /* Controller version, 7 or 9 */
- bool use_sbase; /* Use SBASE instead of RCB */
+ enum pch_version ich_version; /* Controller version, 7 or 9 */
};
struct ich_spi_priv {
@@ -52,7 +56,7 @@
{
u8 value = readb(priv->base + reg);
- debug("read %2.2x from %4.4x\n", value, reg);
+ debug_trace("read %2.2x from %4.4x\n", value, reg);
return value;
}
@@ -61,7 +65,7 @@
{
u16 value = readw(priv->base + reg);
- debug("read %4.4x from %4.4x\n", value, reg);
+ debug_trace("read %4.4x from %4.4x\n", value, reg);
return value;
}
@@ -70,7 +74,7 @@
{
u32 value = readl(priv->base + reg);
- debug("read %8.8x from %4.4x\n", value, reg);
+ debug_trace("read %8.8x from %4.4x\n", value, reg);
return value;
}
@@ -78,19 +82,19 @@
static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
{
writeb(value, priv->base + reg);
- debug("wrote %2.2x to %4.4x\n", value, reg);
+ debug_trace("wrote %2.2x to %4.4x\n", value, reg);
}
static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
{
writew(value, priv->base + reg);
- debug("wrote %4.4x to %4.4x\n", value, reg);
+ debug_trace("wrote %4.4x to %4.4x\n", value, reg);
}
static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
{
writel(value, priv->base + reg);
- debug("wrote %8.8x to %4.4x\n", value, reg);
+ debug_trace("wrote %8.8x to %4.4x\n", value, reg);
}
static void write_reg(struct ich_spi_priv *priv, const void *value,
@@ -116,40 +120,16 @@
ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
}
-/*
- * Check if this device ID matches one of supported Intel PCH devices.
- *
- * Return the ICH version if there is a match, or zero otherwise.
- */
-static int get_ich_version(uint16_t device_id)
-{
- if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
- device_id == PCI_DEVICE_ID_INTEL_ITC_LPC ||
- device_id == PCI_DEVICE_ID_INTEL_QRK_ILB)
- return 7;
-
- if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
- device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
- (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
- device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
- device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||
- device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC ||
- device_id == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC)
- return 9;
-
- return 0;
-}
-
/* @return 1 if the SPI flash supports the 33MHz speed */
-static int ich9_can_do_33mhz(pci_dev_t dev)
+static int ich9_can_do_33mhz(struct udevice *dev)
{
u32 fdod, speed;
/* Observe SPI Descriptor Component Section 0 */
- pci_write_config_dword(dev, 0xb0, 0x1000);
+ dm_pci_write_config32(dev->parent, 0xb0, 0x1000);
/* Extract the Write/Erase SPI Frequency from descriptor */
- pci_read_config_dword(dev, 0xb4, &fdod);
+ dm_pci_read_config32(dev->parent, 0xb4, &fdod);
/* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
speed = (fdod >> 21) & 7;
@@ -157,59 +137,22 @@
return speed == 1;
}
-static int ich_find_spi_controller(struct ich_spi_platdata *ich)
-{
- int last_bus = pci_last_busno();
- int bus;
-
- if (last_bus == -1) {
- debug("No PCI busses?\n");
- return -ENODEV;
- }
-
- for (bus = 0; bus <= last_bus; bus++) {
- uint16_t vendor_id, device_id;
- uint32_t ids;
- pci_dev_t dev;
-
- dev = PCI_BDF(bus, 31, 0);
- pci_read_config_dword(dev, 0, &ids);
- vendor_id = ids;
- device_id = ids >> 16;
-
- if (vendor_id == PCI_VENDOR_ID_INTEL) {
- ich->dev = dev;
- ich->ich_version = get_ich_version(device_id);
- if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
- ich->use_sbase = true;
- return ich->ich_version == 0 ? -ENODEV : 0;
- }
- }
-
- debug("ICH SPI: No ICH found.\n");
- return -ENODEV;
-}
-
-static int ich_init_controller(struct ich_spi_platdata *plat,
+static int ich_init_controller(struct udevice *dev,
+ struct ich_spi_platdata *plat,
struct ich_spi_priv *ctlr)
{
- uint8_t *rcrb; /* Root Complex Register Block */
- uint32_t rcba; /* Root Complex Base Address */
- uint32_t sbase_addr;
- uint8_t *sbase;
-
- pci_read_config_dword(plat->dev, 0xf0, &rcba);
- /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
- rcrb = (uint8_t *)(rcba & 0xffffc000);
+ ulong sbase_addr;
+ void *sbase;
/* SBASE is similar */
- pci_read_config_dword(plat->dev, 0x54, &sbase_addr);
- sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
+ pch_get_sbase(dev->parent, &sbase_addr);
+ sbase = (void *)sbase_addr;
+ debug("%s: sbase=%p\n", __func__, sbase);
- if (plat->ich_version == 7) {
- struct ich7_spi_regs *ich7_spi;
+ if (plat->ich_version == PCHV_7) {
+ struct ich7_spi_regs *ich7_spi = sbase;
- ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
+ ich7_spi = (struct ich7_spi_regs *)sbase;
ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
ctlr->menubytes = sizeof(ich7_spi->opmenu);
@@ -222,13 +165,9 @@
ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
ctlr->preop = offsetof(struct ich7_spi_regs, preop);
ctlr->base = ich7_spi;
- } else if (plat->ich_version == 9) {
- struct ich9_spi_regs *ich9_spi;
+ } else if (plat->ich_version == PCHV_9) {
+ struct ich9_spi_regs *ich9_spi = sbase;
- if (plat->use_sbase)
- ich9_spi = (struct ich9_spi_regs *)sbase;
- else
- ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
ctlr->menubytes = sizeof(ich9_spi->opmenu);
@@ -252,9 +191,9 @@
/* Work out the maximum speed we can support */
ctlr->max_speed = 20000000;
- if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev))
+ if (plat->ich_version == PCHV_9 && ich9_can_do_33mhz(dev))
ctlr->max_speed = 33000000;
- debug("ICH SPI: Version %d detected at %p, speed %ld\n",
+ debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
plat->ich_version, ctlr->base, ctlr->max_speed);
ich_set_bbar(ctlr, 0);
@@ -447,7 +386,7 @@
}
memcpy(trans->cmd, dout, bytes);
trans->cmd_len = bytes;
- debug("ICH SPI: Saved %d bytes\n", bytes);
+ debug_trace("ICH SPI: Saved %d bytes\n", bytes);
return 0;
}
@@ -462,7 +401,7 @@
trans->out = trans->cmd;
trans->bytesout = trans->cmd_len;
using_cmd = 1;
- debug("ICH SPI: Using %d bytes\n", trans->cmd_len);
+ debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len);
} else {
trans->out = dout;
trans->bytesout = dout ? bytes : 0;
@@ -481,7 +420,7 @@
if (ret < 0)
return ret;
- if (plat->ich_version == 7)
+ if (plat->ich_version == PCHV_7)
ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
else
ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
@@ -520,7 +459,7 @@
if (using_cmd && dout && bytes) {
trans->out = dout;
trans->bytesout = bytes;
- debug("ICH SPI: Moving to data, %d bytes\n", bytes);
+ debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes);
}
/* Preset control fields */
@@ -676,30 +615,30 @@
return 0;
}
-static int ich_spi_probe(struct udevice *bus)
+static int ich_spi_probe(struct udevice *dev)
{
- struct ich_spi_platdata *plat = dev_get_platdata(bus);
- struct ich_spi_priv *priv = dev_get_priv(bus);
+ struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ struct ich_spi_priv *priv = dev_get_priv(dev);
uint8_t bios_cntl;
int ret;
- ret = ich_init_controller(plat, priv);
+ /* Check the ICH version */
+ plat->ich_version = pch_get_version(dev->parent);
+
+ ret = ich_init_controller(dev, plat, priv);
if (ret)
return ret;
- /*
- * Disable the BIOS write protect so write commands are allowed. On
- * v9, deassert SMM BIOS Write Protect Disable.
- */
- if (plat->use_sbase) {
+ /* Disable the BIOS write protect so write commands are allowed */
+ ret = pch_set_spi_protect(dev->parent, false);
+ if (ret == -ENOSYS) {
bios_cntl = ich_readb(priv, priv->bcr);
bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
bios_cntl |= 1; /* Write Protect Disable (WPD) */
ich_writeb(priv, bios_cntl, priv->bcr);
- } else {
- pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
- if (plat->ich_version == 9)
- bios_cntl &= ~BIT(5);
- pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
+ } else if (ret) {
+ debug("%s: Failed to disable write-protect: err=%d\n",
+ __func__, ret);
+ return ret;
}
priv->cur_speed = priv->max_speed;
@@ -707,18 +646,6 @@
return 0;
}
-static int ich_spi_ofdata_to_platdata(struct udevice *bus)
-{
- struct ich_spi_platdata *plat = dev_get_platdata(bus);
- int ret;
-
- ret = ich_find_spi_controller(plat);
- if (ret)
- return ret;
-
- return 0;
-}
-
static int ich_spi_set_speed(struct udevice *bus, uint speed)
{
struct ich_spi_priv *priv = dev_get_priv(bus);
@@ -751,7 +678,7 @@
* ICH 7 SPI controller only supports array read command
* and byte program command for SST flash
*/
- if (plat->ich_version == 7) {
+ if (plat->ich_version == PCHV_7) {
slave->mode_rx = SPI_RX_SLOW;
slave->mode = SPI_TX_BYTE;
}
@@ -779,7 +706,6 @@
.id = UCLASS_SPI,
.of_match = ich_spi_ids,
.ops = &ich_spi_ops,
- .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
.priv_auto_alloc_size = sizeof(struct ich_spi_priv),
.child_pre_probe = ich_spi_child_pre_probe,
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 8ff949d..25ccc01 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -18,6 +18,7 @@
#include <malloc.h>
#include <asm/dma-mapping.h>
#include <usb/lin_gadget_compat.h>
+#include <linux/bug.h>
#include <linux/list.h>
#include <linux/usb/ch9.h>
diff --git a/drivers/usb/dwc3/linux-compat.h b/drivers/usb/dwc3/linux-compat.h
index 6c9c279..9e944a3 100644
--- a/drivers/usb/dwc3/linux-compat.h
+++ b/drivers/usb/dwc3/linux-compat.h
@@ -17,8 +17,6 @@
#define dev_WARN(dev, format, arg...) debug(format, ##arg)
#define WARN_ON_ONCE(val) debug("Error %d\n", val)
-#define BUILD_BUG_ON_NOT_POWER_OF_2(n)
-
static inline size_t strlcat(char *dest, const char *src, size_t n)
{
strcat(dest, src);
diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile
index c92d2b0..4c44efc 100644
--- a/drivers/usb/eth/Makefile
+++ b/drivers/usb/eth/Makefile
@@ -9,3 +9,4 @@
obj-$(CONFIG_USB_ETHER_ASIX88179) += asix88179.o
obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
+obj-$(CONFIG_USB_ETHER_RTL8152) += r8152.o r8152_fw.o
diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c
new file mode 100644
index 0000000..325b70c
--- /dev/null
+++ b/drivers/usb/eth/r8152.c
@@ -0,0 +1,1456 @@
+/*
+ * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <usb.h>
+#include <usb/lin_gadget_compat.h>
+#include <linux/mii.h>
+#include <linux/bitops.h>
+#include "usb_ether.h"
+#include "r8152.h"
+
+/* local vars */
+static int curr_eth_dev; /* index for name of next device detected */
+
+struct r8152_dongle {
+ unsigned short vendor;
+ unsigned short product;
+};
+
+struct r8152_version {
+ unsigned short tcr;
+ unsigned short version;
+ bool gmii;
+};
+
+static const struct r8152_dongle const r8152_dongles[] = {
+ /* Realtek */
+ { 0x0bda, 0x8050 },
+ { 0x0bda, 0x8152 },
+ { 0x0bda, 0x8153 },
+
+ /* Samsung */
+ { 0x04e8, 0xa101 },
+
+ /* Lenovo */
+ { 0x17ef, 0x304f },
+ { 0x17ef, 0x3052 },
+ { 0x17ef, 0x3054 },
+ { 0x17ef, 0x3057 },
+ { 0x17ef, 0x7205 },
+ { 0x17ef, 0x720a },
+ { 0x17ef, 0x720b },
+ { 0x17ef, 0x720c },
+
+ /* TP-LINK */
+ { 0x2357, 0x0601 },
+
+ /* Nvidia */
+ { 0x0955, 0x09ff },
+};
+
+static const struct r8152_version const r8152_versions[] = {
+ { 0x4c00, RTL_VER_01, 0 },
+ { 0x4c10, RTL_VER_02, 0 },
+ { 0x5c00, RTL_VER_03, 1 },
+ { 0x5c10, RTL_VER_04, 1 },
+ { 0x5c20, RTL_VER_05, 1 },
+ { 0x5c30, RTL_VER_06, 1 },
+ { 0x4800, RTL_VER_07, 0 },
+};
+
+static
+int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
+{
+ return usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
+ RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
+ value, index, data, size, 500);
+}
+
+static
+int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
+{
+ return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
+ RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
+ value, index, data, size, 500);
+}
+
+int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
+ void *data, u16 type)
+{
+ u16 burst_size = 64;
+ int ret;
+ int txsize;
+
+ /* both size and index must be 4 bytes align */
+ if ((size & 3) || !size || (index & 3) || !data)
+ return -EINVAL;
+
+ if (index + size > 0xffff)
+ return -EINVAL;
+
+ while (size) {
+ txsize = min(size, burst_size);
+ ret = get_registers(tp, index, type, txsize, data);
+ if (ret < 0)
+ break;
+
+ index += txsize;
+ data += txsize;
+ size -= txsize;
+ }
+
+ return ret;
+}
+
+int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
+ u16 size, void *data, u16 type)
+{
+ int ret;
+ u16 byteen_start, byteen_end, byte_en_to_hw;
+ u16 burst_size = 512;
+ int txsize;
+
+ /* both size and index must be 4 bytes align */
+ if ((size & 3) || !size || (index & 3) || !data)
+ return -EINVAL;
+
+ if (index + size > 0xffff)
+ return -EINVAL;
+
+ byteen_start = byteen & BYTE_EN_START_MASK;
+ byteen_end = byteen & BYTE_EN_END_MASK;
+
+ byte_en_to_hw = byteen_start | (byteen_start << 4);
+ ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
+ if (ret < 0)
+ return ret;
+
+ index += 4;
+ data += 4;
+ size -= 4;
+
+ if (size) {
+ size -= 4;
+
+ while (size) {
+ txsize = min(size, burst_size);
+
+ ret = set_registers(tp, index,
+ type | BYTE_EN_DWORD,
+ txsize, data);
+ if (ret < 0)
+ return ret;
+
+ index += txsize;
+ data += txsize;
+ size -= txsize;
+ }
+
+ byte_en_to_hw = byteen_end | (byteen_end >> 4);
+ ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
+}
+
+int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
+{
+ return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
+}
+
+int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
+{
+ return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
+}
+
+int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
+{
+ return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
+}
+
+int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
+{
+ return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
+}
+
+u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
+{
+ __le32 data;
+
+ generic_ocp_read(tp, index, sizeof(data), &data, type);
+
+ return __le32_to_cpu(data);
+}
+
+void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
+{
+ __le32 tmp = __cpu_to_le32(data);
+
+ generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
+}
+
+u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
+{
+ u32 data;
+ __le32 tmp;
+ u8 shift = index & 2;
+
+ index &= ~3;
+
+ generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
+
+ data = __le32_to_cpu(tmp);
+ data >>= (shift * 8);
+ data &= 0xffff;
+
+ return data;
+}
+
+void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
+{
+ u32 mask = 0xffff;
+ __le32 tmp;
+ u16 byen = BYTE_EN_WORD;
+ u8 shift = index & 2;
+
+ data &= mask;
+
+ if (index & 2) {
+ byen <<= shift;
+ mask <<= (shift * 8);
+ data <<= (shift * 8);
+ index &= ~3;
+ }
+
+ tmp = __cpu_to_le32(data);
+
+ generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
+}
+
+u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
+{
+ u32 data;
+ __le32 tmp;
+ u8 shift = index & 3;
+
+ index &= ~3;
+
+ generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
+
+ data = __le32_to_cpu(tmp);
+ data >>= (shift * 8);
+ data &= 0xff;
+
+ return data;
+}
+
+void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
+{
+ u32 mask = 0xff;
+ __le32 tmp;
+ u16 byen = BYTE_EN_BYTE;
+ u8 shift = index & 3;
+
+ data &= mask;
+
+ if (index & 3) {
+ byen <<= shift;
+ mask <<= (shift * 8);
+ data <<= (shift * 8);
+ index &= ~3;
+ }
+
+ tmp = __cpu_to_le32(data);
+
+ generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
+}
+
+u16 ocp_reg_read(struct r8152 *tp, u16 addr)
+{
+ u16 ocp_base, ocp_index;
+
+ ocp_base = addr & 0xf000;
+ if (ocp_base != tp->ocp_base) {
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
+ tp->ocp_base = ocp_base;
+ }
+
+ ocp_index = (addr & 0x0fff) | 0xb000;
+ return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
+}
+
+void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
+{
+ u16 ocp_base, ocp_index;
+
+ ocp_base = addr & 0xf000;
+ if (ocp_base != tp->ocp_base) {
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
+ tp->ocp_base = ocp_base;
+ }
+
+ ocp_index = (addr & 0x0fff) | 0xb000;
+ ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
+}
+
+static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
+{
+ ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
+}
+
+static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
+{
+ return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
+}
+
+void sram_write(struct r8152 *tp, u16 addr, u16 data)
+{
+ ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
+ ocp_reg_write(tp, OCP_SRAM_DATA, data);
+}
+
+int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
+ const u32 mask, bool set, unsigned int timeout)
+{
+ u32 val;
+
+ while (--timeout) {
+ if (ocp_reg)
+ val = ocp_reg_read(tp, index);
+ else
+ val = ocp_read_dword(tp, type, index);
+
+ if (!set)
+ val = ~val;
+
+ if ((val & mask) == mask)
+ return 0;
+
+ mdelay(1);
+ }
+
+ debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
+ __func__, index, mask, timeout);
+
+ return -ETIMEDOUT;
+}
+
+static void r8152b_reset_packet_filter(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
+ ocp_data &= ~FMC_FCR_MCU_EN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
+ ocp_data |= FMC_FCR_MCU_EN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
+}
+
+static void rtl8152_wait_fifo_empty(struct r8152 *tp)
+{
+ int ret;
+
+ ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
+ PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
+ if (ret)
+ debug("Timeout waiting for FIFO empty\n");
+
+ ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
+ TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
+ if (ret)
+ debug("Timeout waiting for TX empty\n");
+}
+
+static void rtl8152_nic_reset(struct r8152 *tp)
+{
+ int ret;
+ u32 ocp_data;
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
+ ocp_data |= BIST_CTRL_SW_RESET;
+ ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
+
+ ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
+ BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
+ if (ret)
+ debug("Timeout waiting for NIC reset\n");
+}
+
+static u8 rtl8152_get_speed(struct r8152 *tp)
+{
+ return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
+}
+
+static void rtl_set_eee_plus(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
+ ocp_data &= ~EEEP_CR_EEEP_TX;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
+}
+
+static void rxdy_gated_en(struct r8152 *tp, bool enable)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
+ if (enable)
+ ocp_data |= RXDY_GATED_EN;
+ else
+ ocp_data &= ~RXDY_GATED_EN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
+}
+
+static void rtl8152_set_rx_mode(struct r8152 *tp)
+{
+ u32 ocp_data;
+ __le32 tmp[2];
+
+ tmp[0] = 0xffffffff;
+ tmp[1] = 0xffffffff;
+
+ pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data |= RCR_APM | RCR_AM | RCR_AB;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+}
+
+static int rtl_enable(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ r8152b_reset_packet_filter(tp);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
+ ocp_data |= PLA_CR_RE | PLA_CR_TE;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
+
+ rxdy_gated_en(tp, false);
+
+ rtl8152_set_rx_mode(tp);
+
+ return 0;
+}
+
+static int rtl8152_enable(struct r8152 *tp)
+{
+ rtl_set_eee_plus(tp);
+
+ return rtl_enable(tp);
+}
+
+static void r8153_set_rx_early_timeout(struct r8152 *tp)
+{
+ u32 ocp_data = tp->coalesce / 8;
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
+}
+
+static void r8153_set_rx_early_size(struct r8152 *tp)
+{
+ u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS) / 4;
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
+}
+
+static int rtl8153_enable(struct r8152 *tp)
+{
+ rtl_set_eee_plus(tp);
+ r8153_set_rx_early_timeout(tp);
+ r8153_set_rx_early_size(tp);
+
+ return rtl_enable(tp);
+}
+
+static void rtl_disable(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data &= ~RCR_ACPT_ALL;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+
+ rxdy_gated_en(tp, true);
+
+ rtl8152_wait_fifo_empty(tp);
+ rtl8152_nic_reset(tp);
+}
+
+static void r8152_power_cut_en(struct r8152 *tp, bool enable)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
+ if (enable)
+ ocp_data |= POWER_CUT;
+ else
+ ocp_data &= ~POWER_CUT;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
+ ocp_data &= ~RESUME_INDICATE;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
+}
+
+static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
+ if (enable)
+ ocp_data |= CPCR_RX_VLAN;
+ else
+ ocp_data &= ~CPCR_RX_VLAN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
+}
+
+static void r8153_u1u2en(struct r8152 *tp, bool enable)
+{
+ u8 u1u2[8];
+
+ if (enable)
+ memset(u1u2, 0xff, sizeof(u1u2));
+ else
+ memset(u1u2, 0x00, sizeof(u1u2));
+
+ usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
+}
+
+static void r8153_u2p3en(struct r8152 *tp, bool enable)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
+ if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
+ ocp_data |= U2P3_ENABLE;
+ else
+ ocp_data &= ~U2P3_ENABLE;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
+}
+
+static void r8153_power_cut_en(struct r8152 *tp, bool enable)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
+ if (enable)
+ ocp_data |= PWR_EN | PHASE2_EN;
+ else
+ ocp_data &= ~(PWR_EN | PHASE2_EN);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
+ ocp_data &= ~PCUT_STATUS;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
+}
+
+static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
+{
+ int ret;
+ unsigned char enetaddr[8] = {0};
+
+ ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
+ if (ret < 0)
+ return ret;
+
+ memcpy(macaddr, enetaddr, ETH_ALEN);
+ return 0;
+}
+
+static void r8152b_disable_aldps(struct r8152 *tp)
+{
+ ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
+ mdelay(20);
+}
+
+static void r8152b_enable_aldps(struct r8152 *tp)
+{
+ ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
+ LINKENA | DIS_SDSAVE);
+}
+
+static void rtl8152_disable(struct r8152 *tp)
+{
+ r8152b_disable_aldps(tp);
+ rtl_disable(tp);
+ r8152b_enable_aldps(tp);
+}
+
+static void r8152b_hw_phy_cfg(struct r8152 *tp)
+{
+ u16 data;
+
+ data = r8152_mdio_read(tp, MII_BMCR);
+ if (data & BMCR_PDOWN) {
+ data &= ~BMCR_PDOWN;
+ r8152_mdio_write(tp, MII_BMCR, data);
+ }
+
+ r8152b_firmware(tp);
+}
+
+static void rtl8152_reinit_ll(struct r8152 *tp)
+{
+ u32 ocp_data;
+ int ret;
+
+ ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
+ PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
+ if (ret)
+ debug("Timeout waiting for link list ready\n");
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
+ ocp_data |= RE_INIT_LL;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
+
+ ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
+ PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
+ if (ret)
+ debug("Timeout waiting for link list ready\n");
+}
+
+static void r8152b_exit_oob(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data &= ~RCR_ACPT_ALL;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+
+ rxdy_gated_en(tp, true);
+ r8152b_hw_phy_cfg(tp);
+
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data &= ~NOW_IS_OOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
+ ocp_data &= ~MCU_BORW_EN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
+
+ rtl8152_reinit_ll(tp);
+ rtl8152_nic_reset(tp);
+
+ /* rx share fifo credit full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
+
+ if (tp->udev->speed == USB_SPEED_FULL ||
+ tp->udev->speed == USB_SPEED_LOW) {
+ /* rx share fifo credit near full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
+ RXFIFO_THR2_FULL);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
+ RXFIFO_THR3_FULL);
+ } else {
+ /* rx share fifo credit near full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
+ RXFIFO_THR2_HIGH);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
+ RXFIFO_THR3_HIGH);
+ }
+
+ /* TX share fifo free credit full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
+
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
+ TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
+ ocp_data |= TCR0_AUTO_FIFO;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
+}
+
+static void r8152b_enter_oob(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data &= ~NOW_IS_OOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
+
+ rtl_disable(tp);
+
+ rtl8152_reinit_ll(tp);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
+
+ rtl_rx_vlan_en(tp, false);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
+ ocp_data |= ALDPS_PROXY_MODE;
+ ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ rxdy_gated_en(tp, false);
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data |= RCR_APM | RCR_AM | RCR_AB;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+}
+
+static void r8153_hw_phy_cfg(struct r8152 *tp)
+{
+ u32 ocp_data;
+ u16 data;
+
+ if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
+ tp->version == RTL_VER_05)
+ ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
+
+ data = r8152_mdio_read(tp, MII_BMCR);
+ if (data & BMCR_PDOWN) {
+ data &= ~BMCR_PDOWN;
+ r8152_mdio_write(tp, MII_BMCR, data);
+ }
+
+ r8153_firmware(tp);
+
+ if (tp->version == RTL_VER_03) {
+ data = ocp_reg_read(tp, OCP_EEE_CFG);
+ data &= ~CTAP_SHORT_EN;
+ ocp_reg_write(tp, OCP_EEE_CFG, data);
+ }
+
+ data = ocp_reg_read(tp, OCP_POWER_CFG);
+ data |= EEE_CLKDIV_EN;
+ ocp_reg_write(tp, OCP_POWER_CFG, data);
+
+ data = ocp_reg_read(tp, OCP_DOWN_SPEED);
+ data |= EN_10M_BGOFF;
+ ocp_reg_write(tp, OCP_DOWN_SPEED, data);
+ data = ocp_reg_read(tp, OCP_POWER_CFG);
+ data |= EN_10M_PLLOFF;
+ ocp_reg_write(tp, OCP_POWER_CFG, data);
+ sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
+ ocp_data |= PFM_PWM_SWITCH;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
+
+ /* Enable LPF corner auto tune */
+ sram_write(tp, SRAM_LPF_CFG, 0xf70f);
+
+ /* Adjust 10M Amplitude */
+ sram_write(tp, SRAM_10M_AMP1, 0x00af);
+ sram_write(tp, SRAM_10M_AMP2, 0x0208);
+}
+
+static void r8153_first_init(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ rxdy_gated_en(tp, true);
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data &= ~RCR_ACPT_ALL;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+
+ r8153_hw_phy_cfg(tp);
+
+ rtl8152_nic_reset(tp);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data &= ~NOW_IS_OOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
+ ocp_data &= ~MCU_BORW_EN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
+
+ rtl8152_reinit_ll(tp);
+
+ rtl_rx_vlan_en(tp, false);
+
+ ocp_data = RTL8153_RMS;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
+ ocp_data |= TCR0_AUTO_FIFO;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
+
+ rtl8152_nic_reset(tp);
+
+ /* rx share fifo credit full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
+ /* TX share fifo free credit full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
+
+ /* rx aggregation */
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
+
+ ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
+}
+
+static void r8153_enter_oob(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data &= ~NOW_IS_OOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ rtl_disable(tp);
+
+ rtl8152_reinit_ll(tp);
+
+ ocp_data = RTL8153_RMS;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
+ ocp_data &= ~TEREDO_WAKE_MASK;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
+
+ rtl_rx_vlan_en(tp, false);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
+ ocp_data |= ALDPS_PROXY_MODE;
+ ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ rxdy_gated_en(tp, false);
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data |= RCR_APM | RCR_AM | RCR_AB;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+}
+
+static void r8153_disable_aldps(struct r8152 *tp)
+{
+ u16 data;
+
+ data = ocp_reg_read(tp, OCP_POWER_CFG);
+ data &= ~EN_ALDPS;
+ ocp_reg_write(tp, OCP_POWER_CFG, data);
+ mdelay(20);
+}
+
+static void rtl8153_disable(struct r8152 *tp)
+{
+ r8153_disable_aldps(tp);
+ rtl_disable(tp);
+}
+
+static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
+{
+ u16 bmcr, anar, gbcr;
+
+ anar = r8152_mdio_read(tp, MII_ADVERTISE);
+ anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
+ ADVERTISE_100HALF | ADVERTISE_100FULL);
+ if (tp->supports_gmii) {
+ gbcr = r8152_mdio_read(tp, MII_CTRL1000);
+ gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
+ } else {
+ gbcr = 0;
+ }
+
+ if (autoneg == AUTONEG_DISABLE) {
+ if (speed == SPEED_10) {
+ bmcr = 0;
+ anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
+ } else if (speed == SPEED_100) {
+ bmcr = BMCR_SPEED100;
+ anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
+ } else if (speed == SPEED_1000 && tp->supports_gmii) {
+ bmcr = BMCR_SPEED1000;
+ gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
+ } else {
+ return -EINVAL;
+ }
+
+ if (duplex == DUPLEX_FULL)
+ bmcr |= BMCR_FULLDPLX;
+ } else {
+ if (speed == SPEED_10) {
+ if (duplex == DUPLEX_FULL)
+ anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
+ else
+ anar |= ADVERTISE_10HALF;
+ } else if (speed == SPEED_100) {
+ if (duplex == DUPLEX_FULL) {
+ anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
+ anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
+ } else {
+ anar |= ADVERTISE_10HALF;
+ anar |= ADVERTISE_100HALF;
+ }
+ } else if (speed == SPEED_1000 && tp->supports_gmii) {
+ if (duplex == DUPLEX_FULL) {
+ anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
+ anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
+ gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
+ } else {
+ anar |= ADVERTISE_10HALF;
+ anar |= ADVERTISE_100HALF;
+ gbcr |= ADVERTISE_1000HALF;
+ }
+ } else {
+ return -EINVAL;
+ }
+
+ bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
+ }
+
+ if (tp->supports_gmii)
+ r8152_mdio_write(tp, MII_CTRL1000, gbcr);
+
+ r8152_mdio_write(tp, MII_ADVERTISE, anar);
+ r8152_mdio_write(tp, MII_BMCR, bmcr);
+
+ return 0;
+}
+
+static void rtl8152_up(struct r8152 *tp)
+{
+ r8152b_disable_aldps(tp);
+ r8152b_exit_oob(tp);
+ r8152b_enable_aldps(tp);
+}
+
+static void rtl8152_down(struct r8152 *tp)
+{
+ r8152_power_cut_en(tp, false);
+ r8152b_disable_aldps(tp);
+ r8152b_enter_oob(tp);
+ r8152b_enable_aldps(tp);
+}
+
+static void rtl8153_up(struct r8152 *tp)
+{
+ r8153_u1u2en(tp, false);
+ r8153_disable_aldps(tp);
+ r8153_first_init(tp);
+ r8153_u2p3en(tp, false);
+}
+
+static void rtl8153_down(struct r8152 *tp)
+{
+ r8153_u1u2en(tp, false);
+ r8153_u2p3en(tp, false);
+ r8153_power_cut_en(tp, false);
+ r8153_disable_aldps(tp);
+ r8153_enter_oob(tp);
+}
+
+static void r8152b_get_version(struct r8152 *tp)
+{
+ u32 ocp_data;
+ u16 tcr;
+ int i;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
+ tcr = (u16)(ocp_data & VERSION_MASK);
+
+ for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
+ if (tcr == r8152_versions[i].tcr) {
+ /* Found a supported version */
+ tp->version = r8152_versions[i].version;
+ tp->supports_gmii = r8152_versions[i].gmii;
+ break;
+ }
+ }
+
+ if (tp->version == RTL_VER_UNKNOWN)
+ debug("r8152 Unknown tcr version 0x%04x\n", tcr);
+}
+
+static void r8152b_enable_fc(struct r8152 *tp)
+{
+ u16 anar;
+ anar = r8152_mdio_read(tp, MII_ADVERTISE);
+ anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
+ r8152_mdio_write(tp, MII_ADVERTISE, anar);
+}
+
+static void rtl_tally_reset(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
+ ocp_data |= TALLY_RESET;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
+}
+
+static void r8152b_init(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ r8152b_disable_aldps(tp);
+
+ if (tp->version == RTL_VER_01) {
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
+ ocp_data &= ~LED_MODE_MASK;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
+ }
+
+ r8152_power_cut_en(tp, false);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
+ ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
+ ocp_data &= ~MCU_CLK_RATIO_MASK;
+ ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
+ ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
+ SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
+ ocp_data |= BIT(15);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
+ ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
+ ocp_data &= ~BIT(15);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
+
+ r8152b_enable_fc(tp);
+ rtl_tally_reset(tp);
+
+ /* enable rx aggregation */
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
+
+ ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
+}
+
+static void r8153_init(struct r8152 *tp)
+{
+ int i;
+ u32 ocp_data;
+
+ r8153_disable_aldps(tp);
+ r8153_u1u2en(tp, false);
+
+ r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
+ AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
+
+ for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
+ ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
+ if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
+ break;
+
+ mdelay(1);
+ }
+
+ r8153_u2p3en(tp, false);
+
+ if (tp->version == RTL_VER_04) {
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
+ ocp_data &= ~pwd_dn_scale_mask;
+ ocp_data |= pwd_dn_scale(96);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
+ ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
+ } else if (tp->version == RTL_VER_05) {
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
+ ocp_data &= ~ECM_ALDPS;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
+ if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
+ ocp_data &= ~DYNAMIC_BURST;
+ else
+ ocp_data |= DYNAMIC_BURST;
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
+ } else if (tp->version == RTL_VER_06) {
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
+ if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
+ ocp_data &= ~DYNAMIC_BURST;
+ else
+ ocp_data |= DYNAMIC_BURST;
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
+ }
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
+ ocp_data |= EP4_FULL_FC;
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
+ ocp_data &= ~TIMER11_EN;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
+ ocp_data &= ~LED_MODE_MASK;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
+
+ ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
+ if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
+ ocp_data |= LPM_TIMER_500MS;
+ else
+ ocp_data |= LPM_TIMER_500US;
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
+ ocp_data &= ~SEN_VAL_MASK;
+ ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
+
+ r8153_power_cut_en(tp, false);
+
+ r8152b_enable_fc(tp);
+ rtl_tally_reset(tp);
+}
+
+static void rtl8152_unload(struct r8152 *tp)
+{
+ if (tp->version != RTL_VER_01)
+ r8152_power_cut_en(tp, true);
+}
+
+static void rtl8153_unload(struct r8152 *tp)
+{
+ r8153_power_cut_en(tp, false);
+}
+
+static int rtl_ops_init(struct r8152 *tp)
+{
+ struct rtl_ops *ops = &tp->rtl_ops;
+ int ret = 0;
+
+ switch (tp->version) {
+ case RTL_VER_01:
+ case RTL_VER_02:
+ case RTL_VER_07:
+ ops->init = r8152b_init;
+ ops->enable = rtl8152_enable;
+ ops->disable = rtl8152_disable;
+ ops->up = rtl8152_up;
+ ops->down = rtl8152_down;
+ ops->unload = rtl8152_unload;
+ break;
+
+ case RTL_VER_03:
+ case RTL_VER_04:
+ case RTL_VER_05:
+ case RTL_VER_06:
+ ops->init = r8153_init;
+ ops->enable = rtl8153_enable;
+ ops->disable = rtl8153_disable;
+ ops->up = rtl8153_up;
+ ops->down = rtl8153_down;
+ ops->unload = rtl8153_unload;
+ break;
+
+ default:
+ ret = -ENODEV;
+ printf("r8152 Unknown Device\n");
+ break;
+ }
+
+ return ret;
+}
+
+static int r8152_init(struct eth_device *eth, bd_t *bd)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct r8152 *tp = (struct r8152 *)dev->dev_priv;
+
+ u8 speed;
+ int timeout = 0;
+ int link_detected;
+
+ debug("** %s()\n", __func__);
+
+ do {
+ speed = rtl8152_get_speed(tp);
+
+ link_detected = speed & LINK_STATUS;
+ if (!link_detected) {
+ if (timeout == 0)
+ printf("Waiting for Ethernet connection... ");
+ mdelay(TIMEOUT_RESOLUTION);
+ timeout += TIMEOUT_RESOLUTION;
+ }
+ } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
+ if (link_detected) {
+ tp->rtl_ops.enable(tp);
+
+ if (timeout != 0)
+ printf("done.\n");
+ } else {
+ printf("unable to connect.\n");
+ }
+
+ return 0;
+}
+
+static int r8152_send(struct eth_device *eth, void *packet, int length)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+
+ u32 opts1, opts2 = 0;
+
+ int err;
+
+ int actual_len;
+ unsigned char msg[PKTSIZE + sizeof(struct tx_desc)];
+ struct tx_desc *tx_desc = (struct tx_desc *)msg;
+
+ debug("** %s(), len %d\n", __func__, length);
+
+ opts1 = length | TX_FS | TX_LS;
+
+ tx_desc->opts2 = cpu_to_le32(opts2);
+ tx_desc->opts1 = cpu_to_le32(opts1);
+
+ memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
+
+ err = usb_bulk_msg(dev->pusb_dev,
+ usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
+ (void *)msg,
+ length + sizeof(struct tx_desc),
+ &actual_len,
+ USB_BULK_SEND_TIMEOUT);
+ debug("Tx: len = %zu, actual = %u, err = %d\n",
+ length + sizeof(struct tx_desc), actual_len, err);
+
+ return err;
+}
+
+static int r8152_recv(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+
+ static unsigned char recv_buf[RTL8152_AGG_BUF_SZ];
+ unsigned char *pkt_ptr;
+ int err;
+ int actual_len;
+ u16 packet_len;
+
+ u32 bytes_process = 0;
+ struct rx_desc *rx_desc;
+
+ debug("** %s()\n", __func__);
+
+ err = usb_bulk_msg(dev->pusb_dev,
+ usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
+ (void *)recv_buf,
+ RTL8152_AGG_BUF_SZ,
+ &actual_len,
+ USB_BULK_RECV_TIMEOUT);
+ debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
+ actual_len, err);
+ if (err != 0) {
+ debug("Rx: failed to receive\n");
+ return -1;
+ }
+ if (actual_len > RTL8152_AGG_BUF_SZ) {
+ debug("Rx: received too many bytes %d\n", actual_len);
+ return -1;
+ }
+
+ while (bytes_process < actual_len) {
+ rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
+ pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
+
+ packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
+ packet_len -= CRC_SIZE;
+
+ net_process_received_packet(pkt_ptr, packet_len);
+
+ bytes_process +=
+ (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
+
+ if (bytes_process % 8)
+ bytes_process = bytes_process + 8 - (bytes_process % 8);
+ }
+
+ return 0;
+}
+
+static void r8152_halt(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct r8152 *tp = (struct r8152 *)dev->dev_priv;
+
+ debug("** %s()\n", __func__);
+
+ tp->rtl_ops.disable(tp);
+}
+
+static int r8152_write_hwaddr(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct r8152 *tp = (struct r8152 *)dev->dev_priv;
+
+ unsigned char enetaddr[8] = {0};
+
+ memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
+
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
+ pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
+
+ debug("MAC %pM\n", eth->enetaddr);
+ return 0;
+}
+
+void r8152_eth_before_probe(void)
+{
+ curr_eth_dev = 0;
+}
+
+/* Probe to see if a new device is actually an realtek device */
+int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
+ struct ueth_data *ss)
+{
+ struct usb_interface *iface;
+ struct usb_interface_descriptor *iface_desc;
+ int ep_in_found = 0, ep_out_found = 0;
+ int i;
+
+ struct r8152 *tp;
+
+ /* let's examine the device now */
+ iface = &dev->config.if_desc[ifnum];
+ iface_desc = &dev->config.if_desc[ifnum].desc;
+
+ for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
+ if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
+ dev->descriptor.idProduct == r8152_dongles[i].product)
+ /* Found a supported dongle */
+ break;
+ }
+
+ if (i == ARRAY_SIZE(r8152_dongles))
+ return 0;
+
+ memset(ss, 0, sizeof(struct ueth_data));
+
+ /* At this point, we know we've got a live one */
+ debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
+ dev->descriptor.idVendor, dev->descriptor.idProduct);
+
+ /* Initialize the ueth_data structure with some useful info */
+ ss->ifnum = ifnum;
+ ss->pusb_dev = dev;
+ ss->subclass = iface_desc->bInterfaceSubClass;
+ ss->protocol = iface_desc->bInterfaceProtocol;
+
+ /* alloc driver private */
+ ss->dev_priv = calloc(1, sizeof(struct r8152));
+
+ if (!ss->dev_priv)
+ return 0;
+
+ /*
+ * We are expecting a minimum of 3 endpoints - in, out (bulk), and
+ * int. We will ignore any others.
+ */
+ for (i = 0; i < iface_desc->bNumEndpoints; i++) {
+ /* is it an BULK endpoint? */
+ if ((iface->ep_desc[i].bmAttributes &
+ USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
+ u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
+ if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
+ ss->ep_in = ep_addr &
+ USB_ENDPOINT_NUMBER_MASK;
+ ep_in_found = 1;
+ } else {
+ if (!ep_out_found) {
+ ss->ep_out = ep_addr &
+ USB_ENDPOINT_NUMBER_MASK;
+ ep_out_found = 1;
+ }
+ }
+ }
+
+ /* is it an interrupt endpoint? */
+ if ((iface->ep_desc[i].bmAttributes &
+ USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
+ ss->ep_int = iface->ep_desc[i].bEndpointAddress &
+ USB_ENDPOINT_NUMBER_MASK;
+ ss->irqinterval = iface->ep_desc[i].bInterval;
+ }
+ }
+
+ debug("Endpoints In %d Out %d Int %d\n",
+ ss->ep_in, ss->ep_out, ss->ep_int);
+
+ /* Do some basic sanity checks, and bail if we find a problem */
+ if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
+ !ss->ep_in || !ss->ep_out || !ss->ep_int) {
+ debug("Problems with device\n");
+ return 0;
+ }
+
+ dev->privptr = (void *)ss;
+
+ tp = ss->dev_priv;
+ tp->udev = dev;
+ tp->intf = iface;
+
+ r8152b_get_version(tp);
+
+ if (rtl_ops_init(tp))
+ return 0;
+
+ tp->rtl_ops.init(tp);
+ tp->rtl_ops.up(tp);
+
+ rtl8152_set_speed(tp, AUTONEG_ENABLE,
+ tp->supports_gmii ? SPEED_1000 : SPEED_100,
+ DUPLEX_FULL);
+
+ return 1;
+}
+
+int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+ struct eth_device *eth)
+{
+ if (!eth) {
+ debug("%s: missing parameter.\n", __func__);
+ return 0;
+ }
+
+ sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
+ eth->init = r8152_init;
+ eth->send = r8152_send;
+ eth->recv = r8152_recv;
+ eth->halt = r8152_halt;
+ eth->write_hwaddr = r8152_write_hwaddr;
+ eth->priv = ss;
+
+ /* Get the MAC address */
+ if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
+ return 0;
+
+ debug("MAC %pM\n", eth->enetaddr);
+ return 1;
+}
diff --git a/drivers/usb/eth/r8152.h b/drivers/usb/eth/r8152.h
new file mode 100644
index 0000000..cd44da2
--- /dev/null
+++ b/drivers/usb/eth/r8152.h
@@ -0,0 +1,631 @@
+/*
+ * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#ifndef _RTL8152_ETH_H
+#define _RTL8152_ETH_H
+
+#define R8152_BASE_NAME "r8152"
+
+#define PLA_IDR 0xc000
+#define PLA_RCR 0xc010
+#define PLA_RMS 0xc016
+#define PLA_RXFIFO_CTRL0 0xc0a0
+#define PLA_RXFIFO_CTRL1 0xc0a4
+#define PLA_RXFIFO_CTRL2 0xc0a8
+#define PLA_DMY_REG0 0xc0b0
+#define PLA_FMC 0xc0b4
+#define PLA_CFG_WOL 0xc0b6
+#define PLA_TEREDO_CFG 0xc0bc
+#define PLA_MAR 0xcd00
+#define PLA_BACKUP 0xd000
+#define PAL_BDC_CR 0xd1a0
+#define PLA_TEREDO_TIMER 0xd2cc
+#define PLA_REALWOW_TIMER 0xd2e8
+#define PLA_LEDSEL 0xdd90
+#define PLA_LED_FEATURE 0xdd92
+#define PLA_PHYAR 0xde00
+#define PLA_BOOT_CTRL 0xe004
+#define PLA_GPHY_INTR_IMR 0xe022
+#define PLA_EEE_CR 0xe040
+#define PLA_EEEP_CR 0xe080
+#define PLA_MAC_PWR_CTRL 0xe0c0
+#define PLA_MAC_PWR_CTRL2 0xe0ca
+#define PLA_MAC_PWR_CTRL3 0xe0cc
+#define PLA_MAC_PWR_CTRL4 0xe0ce
+#define PLA_WDT6_CTRL 0xe428
+#define PLA_TCR0 0xe610
+#define PLA_TCR1 0xe612
+#define PLA_MTPS 0xe615
+#define PLA_TXFIFO_CTRL 0xe618
+#define PLA_RSTTALLY 0xe800
+#define BIST_CTRL 0xe810
+#define PLA_CR 0xe813
+#define PLA_CRWECR 0xe81c
+#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
+#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
+#define PLA_CONFIG5 0xe822
+#define PLA_PHY_PWR 0xe84c
+#define PLA_OOB_CTRL 0xe84f
+#define PLA_CPCR 0xe854
+#define PLA_MISC_0 0xe858
+#define PLA_MISC_1 0xe85a
+#define PLA_OCP_GPHY_BASE 0xe86c
+#define PLA_TALLYCNT 0xe890
+#define PLA_SFF_STS_7 0xe8de
+#define PLA_PHYSTATUS 0xe908
+#define PLA_BP_BA 0xfc26
+#define PLA_BP_0 0xfc28
+#define PLA_BP_1 0xfc2a
+#define PLA_BP_2 0xfc2c
+#define PLA_BP_3 0xfc2e
+#define PLA_BP_4 0xfc30
+#define PLA_BP_5 0xfc32
+#define PLA_BP_6 0xfc34
+#define PLA_BP_7 0xfc36
+#define PLA_BP_EN 0xfc38
+
+#define USB_USB2PHY 0xb41e
+#define USB_SSPHYLINK2 0xb428
+#define USB_U2P3_CTRL 0xb460
+#define USB_CSR_DUMMY1 0xb464
+#define USB_CSR_DUMMY2 0xb466
+#define USB_DEV_STAT 0xb808
+#define USB_CONNECT_TIMER 0xcbf8
+#define USB_BURST_SIZE 0xcfc0
+#define USB_USB_CTRL 0xd406
+#define USB_PHY_CTRL 0xd408
+#define USB_TX_AGG 0xd40a
+#define USB_RX_BUF_TH 0xd40c
+#define USB_USB_TIMER 0xd428
+#define USB_RX_EARLY_TIMEOUT 0xd42c
+#define USB_RX_EARLY_SIZE 0xd42e
+#define USB_PM_CTRL_STATUS 0xd432
+#define USB_TX_DMA 0xd434
+#define USB_TOLERANCE 0xd490
+#define USB_LPM_CTRL 0xd41a
+#define USB_UPS_CTRL 0xd800
+#define USB_MISC_0 0xd81a
+#define USB_POWER_CUT 0xd80a
+#define USB_AFE_CTRL2 0xd824
+#define USB_WDT11_CTRL 0xe43c
+#define USB_BP_BA 0xfc26
+#define USB_BP_0 0xfc28
+#define USB_BP_1 0xfc2a
+#define USB_BP_2 0xfc2c
+#define USB_BP_3 0xfc2e
+#define USB_BP_4 0xfc30
+#define USB_BP_5 0xfc32
+#define USB_BP_6 0xfc34
+#define USB_BP_7 0xfc36
+#define USB_BP_EN 0xfc38
+
+/* OCP Registers */
+#define OCP_ALDPS_CONFIG 0x2010
+#define OCP_EEE_CONFIG1 0x2080
+#define OCP_EEE_CONFIG2 0x2092
+#define OCP_EEE_CONFIG3 0x2094
+#define OCP_BASE_MII 0xa400
+#define OCP_EEE_AR 0xa41a
+#define OCP_EEE_DATA 0xa41c
+#define OCP_PHY_STATUS 0xa420
+#define OCP_POWER_CFG 0xa430
+#define OCP_EEE_CFG 0xa432
+#define OCP_SRAM_ADDR 0xa436
+#define OCP_SRAM_DATA 0xa438
+#define OCP_DOWN_SPEED 0xa442
+#define OCP_EEE_ABLE 0xa5c4
+#define OCP_EEE_ADV 0xa5d0
+#define OCP_EEE_LPABLE 0xa5d2
+#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
+#define OCP_ADC_CFG 0xbc06
+
+/* SRAM Register */
+#define SRAM_LPF_CFG 0x8012
+#define SRAM_10M_AMP1 0x8080
+#define SRAM_10M_AMP2 0x8082
+#define SRAM_IMPEDANCE 0x8084
+
+/* PLA_RCR */
+#define RCR_AAP 0x00000001
+#define RCR_APM 0x00000002
+#define RCR_AM 0x00000004
+#define RCR_AB 0x00000008
+#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
+
+/* PLA_RXFIFO_CTRL0 */
+#define RXFIFO_THR1_NORMAL 0x00080002
+#define RXFIFO_THR1_OOB 0x01800003
+
+/* PLA_RXFIFO_CTRL1 */
+#define RXFIFO_THR2_FULL 0x00000060
+#define RXFIFO_THR2_HIGH 0x00000038
+#define RXFIFO_THR2_OOB 0x0000004a
+#define RXFIFO_THR2_NORMAL 0x00a0
+
+/* PLA_RXFIFO_CTRL2 */
+#define RXFIFO_THR3_FULL 0x00000078
+#define RXFIFO_THR3_HIGH 0x00000048
+#define RXFIFO_THR3_OOB 0x0000005a
+#define RXFIFO_THR3_NORMAL 0x0110
+
+/* PLA_TXFIFO_CTRL */
+#define TXFIFO_THR_NORMAL 0x00400008
+#define TXFIFO_THR_NORMAL2 0x01000008
+
+/* PLA_DMY_REG0 */
+#define ECM_ALDPS 0x0002
+
+/* PLA_FMC */
+#define FMC_FCR_MCU_EN 0x0001
+
+/* PLA_EEEP_CR */
+#define EEEP_CR_EEEP_TX 0x0002
+
+/* PLA_WDT6_CTRL */
+#define WDT6_SET_MODE 0x0010
+
+/* PLA_TCR0 */
+#define TCR0_TX_EMPTY 0x0800
+#define TCR0_AUTO_FIFO 0x0080
+
+/* PLA_TCR1 */
+#define VERSION_MASK 0x7cf0
+
+/* PLA_MTPS */
+#define MTPS_JUMBO (12 * 1024 / 64)
+#define MTPS_DEFAULT (6 * 1024 / 64)
+
+/* PLA_RSTTALLY */
+#define TALLY_RESET 0x0001
+
+/* PLA_CR */
+#define PLA_CR_RST 0x10
+#define PLA_CR_RE 0x08
+#define PLA_CR_TE 0x04
+
+/* PLA_BIST_CTRL */
+#define BIST_CTRL_SW_RESET (0x10 << 24)
+
+/* PLA_CRWECR */
+#define CRWECR_NORAML 0x00
+#define CRWECR_CONFIG 0xc0
+
+/* PLA_OOB_CTRL */
+#define NOW_IS_OOB 0x80
+#define TXFIFO_EMPTY 0x20
+#define RXFIFO_EMPTY 0x10
+#define LINK_LIST_READY 0x02
+#define DIS_MCU_CLROOB 0x01
+#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
+
+/* PLA_PHY_PWR */
+#define PLA_PHY_PWR_LLR (LINK_LIST_READY << 24)
+#define PLA_PHY_PWR_TXEMP (TXFIFO_EMPTY << 24)
+
+/* PLA_MISC_1 */
+#define RXDY_GATED_EN 0x0008
+
+/* PLA_SFF_STS_7 */
+#define RE_INIT_LL 0x8000
+#define MCU_BORW_EN 0x4000
+
+/* PLA_CPCR */
+#define CPCR_RX_VLAN 0x0040
+
+/* PLA_CFG_WOL */
+#define MAGIC_EN 0x0001
+
+/* PLA_TEREDO_CFG */
+#define TEREDO_SEL 0x8000
+#define TEREDO_WAKE_MASK 0x7f00
+#define TEREDO_RS_EVENT_MASK 0x00fe
+#define OOB_TEREDO_EN 0x0001
+
+/* PAL_BDC_CR */
+#define ALDPS_PROXY_MODE 0x0001
+
+/* PLA_CONFIG34 */
+#define LINK_ON_WAKE_EN 0x0010
+#define LINK_OFF_WAKE_EN 0x0008
+
+/* PLA_CONFIG5 */
+#define BWF_EN 0x0040
+#define MWF_EN 0x0020
+#define UWF_EN 0x0010
+#define LAN_WAKE_EN 0x0002
+
+/* PLA_LED_FEATURE */
+#define LED_MODE_MASK 0x0700
+
+/* PLA_PHY_PWR */
+#define TX_10M_IDLE_EN 0x0080
+#define PFM_PWM_SWITCH 0x0040
+
+/* PLA_MAC_PWR_CTRL */
+#define D3_CLK_GATED_EN 0x00004000
+#define MCU_CLK_RATIO 0x07010f07
+#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
+#define ALDPS_SPDWN_RATIO 0x0f87
+
+/* PLA_MAC_PWR_CTRL2 */
+#define EEE_SPDWN_RATIO 0x8007
+
+/* PLA_MAC_PWR_CTRL3 */
+#define PKT_AVAIL_SPDWN_EN 0x0100
+#define SUSPEND_SPDWN_EN 0x0004
+#define U1U2_SPDWN_EN 0x0002
+#define L1_SPDWN_EN 0x0001
+
+/* PLA_MAC_PWR_CTRL4 */
+#define PWRSAVE_SPDWN_EN 0x1000
+#define RXDV_SPDWN_EN 0x0800
+#define TX10MIDLE_EN 0x0100
+#define TP100_SPDWN_EN 0x0020
+#define TP500_SPDWN_EN 0x0010
+#define TP1000_SPDWN_EN 0x0008
+#define EEE_SPDWN_EN 0x0001
+
+/* PLA_GPHY_INTR_IMR */
+#define GPHY_STS_MSK 0x0001
+#define SPEED_DOWN_MSK 0x0002
+#define SPDWN_RXDV_MSK 0x0004
+#define SPDWN_LINKCHG_MSK 0x0008
+
+/* PLA_PHYAR */
+#define PHYAR_FLAG 0x80000000
+
+/* PLA_EEE_CR */
+#define EEE_RX_EN 0x0001
+#define EEE_TX_EN 0x0002
+
+/* PLA_BOOT_CTRL */
+#define AUTOLOAD_DONE 0x0002
+
+/* USB_USB2PHY */
+#define USB2PHY_SUSPEND 0x0001
+#define USB2PHY_L1 0x0002
+
+/* USB_SSPHYLINK2 */
+#define pwd_dn_scale_mask 0x3ffe
+#define pwd_dn_scale(x) ((x) << 1)
+
+/* USB_CSR_DUMMY1 */
+#define DYNAMIC_BURST 0x0001
+
+/* USB_CSR_DUMMY2 */
+#define EP4_FULL_FC 0x0001
+
+/* USB_DEV_STAT */
+#define STAT_SPEED_MASK 0x0006
+#define STAT_SPEED_HIGH 0x0000
+#define STAT_SPEED_FULL 0x0002
+
+/* USB_TX_AGG */
+#define TX_AGG_MAX_THRESHOLD 0x03
+
+/* USB_RX_BUF_TH */
+#define RX_THR_SUPPER 0x0c350180
+#define RX_THR_HIGH 0x7a120180
+#define RX_THR_SLOW 0xffff0180
+
+/* USB_TX_DMA */
+#define TEST_MODE_DISABLE 0x00000001
+#define TX_SIZE_ADJUST1 0x00000100
+
+/* USB_UPS_CTRL */
+#define POWER_CUT 0x0100
+
+/* USB_PM_CTRL_STATUS */
+#define RESUME_INDICATE 0x0001
+
+/* USB_USB_CTRL */
+#define RX_AGG_DISABLE 0x0010
+#define RX_ZERO_EN 0x0080
+
+/* USB_U2P3_CTRL */
+#define U2P3_ENABLE 0x0001
+
+/* USB_POWER_CUT */
+#define PWR_EN 0x0001
+#define PHASE2_EN 0x0008
+
+/* USB_MISC_0 */
+#define PCUT_STATUS 0x0001
+
+/* USB_RX_EARLY_TIMEOUT */
+#define COALESCE_SUPER 85000U
+#define COALESCE_HIGH 250000U
+#define COALESCE_SLOW 524280U
+
+/* USB_WDT11_CTRL */
+#define TIMER11_EN 0x0001
+
+/* USB_LPM_CTRL */
+/* bit 4 ~ 5: fifo empty boundary */
+#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
+/* bit 2 ~ 3: LMP timer */
+#define LPM_TIMER_MASK 0x0c
+#define LPM_TIMER_500MS 0x04 /* 500 ms */
+#define LPM_TIMER_500US 0x0c /* 500 us */
+#define ROK_EXIT_LPM 0x02
+
+/* USB_AFE_CTRL2 */
+#define SEN_VAL_MASK 0xf800
+#define SEN_VAL_NORMAL 0xa000
+#define SEL_RXIDLE 0x0100
+
+/* OCP_ALDPS_CONFIG */
+#define ENPWRSAVE 0x8000
+#define ENPDNPS 0x0200
+#define LINKENA 0x0100
+#define DIS_SDSAVE 0x0010
+
+/* OCP_PHY_STATUS */
+#define PHY_STAT_MASK 0x0007
+#define PHY_STAT_LAN_ON 3
+#define PHY_STAT_PWRDN 5
+
+/* OCP_POWER_CFG */
+#define EEE_CLKDIV_EN 0x8000
+#define EN_ALDPS 0x0004
+#define EN_10M_PLLOFF 0x0001
+
+/* OCP_EEE_CONFIG1 */
+#define RG_TXLPI_MSK_HFDUP 0x8000
+#define RG_MATCLR_EN 0x4000
+#define EEE_10_CAP 0x2000
+#define EEE_NWAY_EN 0x1000
+#define TX_QUIET_EN 0x0200
+#define RX_QUIET_EN 0x0100
+#define sd_rise_time_mask 0x0070
+#define sd_rise_time(x) (min((x), 7) << 4) /* bit 4 ~ 6 */
+#define RG_RXLPI_MSK_HFDUP 0x0008
+#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
+
+/* OCP_EEE_CONFIG2 */
+#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
+#define RG_DACQUIET_EN 0x0400
+#define RG_LDVQUIET_EN 0x0200
+#define RG_CKRSEL 0x0020
+#define RG_EEEPRG_EN 0x0010
+
+/* OCP_EEE_CONFIG3 */
+#define fast_snr_mask 0xff80
+#define fast_snr(x) (min((x), 0x1ff) << 7) /* bit 7 ~ 15 */
+#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
+#define MSK_PH 0x0006 /* bit 0 ~ 3 */
+
+/* OCP_EEE_AR */
+/* bit[15:14] function */
+#define FUN_ADDR 0x0000
+#define FUN_DATA 0x4000
+/* bit[4:0] device addr */
+
+/* OCP_EEE_CFG */
+#define CTAP_SHORT_EN 0x0040
+#define EEE10_EN 0x0010
+
+/* OCP_DOWN_SPEED */
+#define EN_10M_BGOFF 0x0080
+
+/* OCP_PHY_STATE */
+#define TXDIS_STATE 0x01
+#define ABD_STATE 0x02
+
+/* OCP_ADC_CFG */
+#define CKADSEL_L 0x0100
+#define ADC_EN 0x0080
+#define EN_EMI_L 0x0040
+
+/* SRAM_LPF_CFG */
+#define LPF_AUTO_TUNE 0x8000
+
+/* SRAM_10M_AMP1 */
+#define GDAC_IB_UPALL 0x0008
+
+/* SRAM_10M_AMP2 */
+#define AMP_DN 0x0200
+
+/* SRAM_IMPEDANCE */
+#define RX_DRIVING_MASK 0x6000
+
+#define RTL8152_MAX_TX 4
+#define RTL8152_MAX_RX 10
+#define INTBUFSIZE 2
+#define CRC_SIZE 4
+#define TX_ALIGN 4
+#define RX_ALIGN 8
+
+#define INTR_LINK 0x0004
+
+#define RTL8152_REQT_READ 0xc0
+#define RTL8152_REQT_WRITE 0x40
+#define RTL8152_REQ_GET_REGS 0x05
+#define RTL8152_REQ_SET_REGS 0x05
+
+#define BYTE_EN_DWORD 0xff
+#define BYTE_EN_WORD 0x33
+#define BYTE_EN_BYTE 0x11
+#define BYTE_EN_SIX_BYTES 0x3f
+#define BYTE_EN_START_MASK 0x0f
+#define BYTE_EN_END_MASK 0xf0
+
+#define RTL8152_ETH_FRAME_LEN 1514
+#define RTL8152_AGG_BUF_SZ 2048
+
+#define RTL8152_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
+#define RTL8153_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
+#define RTL8152_TX_TIMEOUT (5 * HZ)
+
+#define MCU_TYPE_PLA 0x0100
+#define MCU_TYPE_USB 0x0000
+
+/* The forced speed, 10Mb, 100Mb, gigabit. */
+#define SPEED_10 10
+#define SPEED_100 100
+#define SPEED_1000 1000
+
+#define SPEED_UNKNOWN -1
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF 0x00
+#define DUPLEX_FULL 0x01
+#define DUPLEX_UNKNOWN 0xff
+
+/* Enable or disable autonegotiation. */
+#define AUTONEG_DISABLE 0x00
+#define AUTONEG_ENABLE 0x01
+
+/* Generic MII registers. */
+#define MII_BMCR 0x00 /* Basic mode control register */
+#define MII_BMSR 0x01 /* Basic mode status register */
+#define MII_PHYSID1 0x02 /* PHYS ID 1 */
+#define MII_PHYSID2 0x03 /* PHYS ID 2 */
+#define MII_ADVERTISE 0x04 /* Advertisement control reg */
+#define MII_LPA 0x05 /* Link partner ability reg */
+#define MII_EXPANSION 0x06 /* Expansion register */
+#define MII_CTRL1000 0x09 /* 1000BASE-T control */
+#define MII_STAT1000 0x0a /* 1000BASE-T status */
+#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
+#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
+#define MII_ESTATUS 0x0f /* Extended Status */
+#define MII_DCOUNTER 0x12 /* Disconnect counter */
+#define MII_FCSCOUNTER 0x13 /* False carrier counter */
+#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
+#define MII_RERRCOUNTER 0x15 /* Receive error counter */
+#define MII_SREVISION 0x16 /* Silicon revision */
+#define MII_RESV1 0x17 /* Reserved... */
+#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
+#define MII_PHYADDR 0x19 /* PHY address */
+#define MII_RESV2 0x1a /* Reserved... */
+#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
+#define MII_NCONFIG 0x1c /* Network interface config */
+
+#define TIMEOUT_RESOLUTION 50
+#define PHY_CONNECT_TIMEOUT 5000
+#define USB_BULK_SEND_TIMEOUT 5000
+#define USB_BULK_RECV_TIMEOUT 5000
+#define R8152_WAIT_TIMEOUT 2000
+
+struct rx_desc {
+ __le32 opts1;
+#define RD_CRC BIT(15)
+#define RX_LEN_MASK 0x7fff
+
+ __le32 opts2;
+#define RD_UDP_CS BIT(23)
+#define RD_TCP_CS BIT(22)
+#define RD_IPV6_CS BIT(20)
+#define RD_IPV4_CS BIT(19)
+
+ __le32 opts3;
+#define IPF BIT(23) /* IP checksum fail */
+#define UDPF BIT(22) /* UDP checksum fail */
+#define TCPF BIT(21) /* TCP checksum fail */
+#define RX_VLAN_TAG BIT(16)
+
+ __le32 opts4;
+ __le32 opts5;
+ __le32 opts6;
+};
+
+struct tx_desc {
+ __le32 opts1;
+#define TX_FS BIT(31) /* First segment of a packet */
+#define TX_LS BIT(30) /* Final segment of a packet */
+#define LGSEND BIT(29)
+#define GTSENDV4 BIT(28)
+#define GTSENDV6 BIT(27)
+#define GTTCPHO_SHIFT 18
+#define GTTCPHO_MAX 0x7fU
+#define TX_LEN_MAX 0x3ffffU
+
+ __le32 opts2;
+#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
+#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
+#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
+#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
+#define MSS_SHIFT 17
+#define MSS_MAX 0x7ffU
+#define TCPHO_SHIFT 17
+#define TCPHO_MAX 0x7ffU
+#define TX_VLAN_TAG BIT(16)
+};
+
+enum rtl_version {
+ RTL_VER_UNKNOWN = 0,
+ RTL_VER_01,
+ RTL_VER_02,
+ RTL_VER_03,
+ RTL_VER_04,
+ RTL_VER_05,
+ RTL_VER_06,
+ RTL_VER_07,
+ RTL_VER_MAX
+};
+
+enum rtl_register_content {
+ _1000bps = 0x10,
+ _100bps = 0x08,
+ _10bps = 0x04,
+ LINK_STATUS = 0x02,
+ FULL_DUP = 0x01,
+};
+
+struct r8152 {
+ struct usb_device *udev;
+ struct usb_interface *intf;
+ bool supports_gmii;
+
+ struct rtl_ops {
+ void (*init)(struct r8152 *);
+ int (*enable)(struct r8152 *);
+ void (*disable)(struct r8152 *);
+ void (*up)(struct r8152 *);
+ void (*down)(struct r8152 *);
+ void (*unload)(struct r8152 *);
+ } rtl_ops;
+
+ u32 coalesce;
+ u16 ocp_base;
+
+ u8 version;
+};
+
+int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
+ u16 size, void *data, u16 type);
+int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
+ void *data, u16 type);
+
+int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
+int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
+ u16 size, void *data);
+
+int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
+int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
+ u16 size, void *data);
+
+u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index);
+void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data);
+
+u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index);
+void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data);
+
+u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index);
+void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data);
+
+u16 ocp_reg_read(struct r8152 *tp, u16 addr);
+void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data);
+
+void sram_write(struct r8152 *tp, u16 addr, u16 data);
+
+int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
+ const u32 mask, bool set, unsigned int timeout);
+
+void r8152b_firmware(struct r8152 *tp);
+void r8153_firmware(struct r8152 *tp);
+#endif
diff --git a/drivers/usb/eth/r8152_fw.c b/drivers/usb/eth/r8152_fw.c
new file mode 100644
index 0000000..f820b16
--- /dev/null
+++ b/drivers/usb/eth/r8152_fw.c
@@ -0,0 +1,980 @@
+/*
+ * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include "r8152.h"
+
+static u8 r8152b_pla_patch_a[] = {
+ 0x08, 0xe0, 0x40, 0xe0, 0x78, 0xe0, 0x85, 0xe0,
+ 0x5d, 0xe1, 0xa1, 0xe1, 0xa3, 0xe1, 0xab, 0xe1,
+ 0x31, 0xc3, 0x60, 0x72, 0xa0, 0x49, 0x10, 0xf0,
+ 0xa4, 0x49, 0x0e, 0xf0, 0x2c, 0xc3, 0x62, 0x72,
+ 0x26, 0x70, 0x80, 0x49, 0x05, 0xf0, 0x2f, 0x48,
+ 0x62, 0x9a, 0x24, 0x70, 0x60, 0x98, 0x24, 0xc3,
+ 0x60, 0x99, 0x23, 0xc3, 0x00, 0xbb, 0x2c, 0x75,
+ 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13, 0x0a, 0xf0,
+ 0x03, 0x13, 0x08, 0xf0, 0x02, 0x13, 0x06, 0xf0,
+ 0x01, 0x13, 0x04, 0xf0, 0x08, 0x13, 0x02, 0xf0,
+ 0x03, 0xe0, 0xd4, 0x49, 0x04, 0xf1, 0x14, 0xc2,
+ 0x12, 0xc3, 0x00, 0xbb, 0x12, 0xc3, 0x60, 0x75,
+ 0xd0, 0x49, 0x05, 0xf1, 0x50, 0x48, 0x60, 0x9d,
+ 0x09, 0xc6, 0x00, 0xbe, 0xd0, 0x48, 0x60, 0x9d,
+ 0xf3, 0xe7, 0xc2, 0xc0, 0x38, 0xd2, 0xc6, 0xd2,
+ 0x84, 0x17, 0xa2, 0x13, 0x0c, 0x17, 0xbc, 0xc0,
+ 0xa2, 0xd1, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49,
+ 0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13,
+ 0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0,
+ 0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1,
+ 0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06,
+ 0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5,
+ 0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3,
+ 0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5,
+ 0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5,
+ 0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e,
+ 0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74,
+ 0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e,
+ 0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7,
+ 0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4,
+ 0x22, 0x02, 0xf0, 0xc0, 0x0b, 0xc0, 0x00, 0x71,
+ 0x0a, 0xc0, 0x00, 0x72, 0xa0, 0x49, 0x04, 0xf0,
+ 0xa4, 0x49, 0x02, 0xf0, 0x93, 0x48, 0x04, 0xc0,
+ 0x00, 0xb8, 0x00, 0xe4, 0xc2, 0xc0, 0x8c, 0x09,
+ 0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b,
+ 0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0,
+ 0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd,
+ 0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b,
+ 0x02, 0xc2, 0x00, 0xba, 0x82, 0x18, 0x00, 0xa0,
+ 0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8,
+ 0x00, 0x80, 0x00, 0x60, 0x2c, 0x75, 0xd4, 0x49,
+ 0x12, 0xf1, 0x29, 0xe0, 0xf8, 0xc2, 0x46, 0x71,
+ 0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1,
+ 0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30,
+ 0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72,
+ 0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f,
+ 0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75,
+ 0x32, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1,
+ 0xdc, 0x21, 0xbc, 0x25, 0x27, 0xc6, 0xc0, 0x77,
+ 0x04, 0x13, 0x18, 0xf0, 0x03, 0x13, 0x19, 0xf0,
+ 0x02, 0x13, 0x1a, 0xf0, 0x01, 0x13, 0x1b, 0xf0,
+ 0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5, 0x00, 0xbd,
+ 0xcd, 0xc6, 0xc6, 0x67, 0x2e, 0x75, 0xd7, 0x22,
+ 0xdd, 0x26, 0x05, 0x15, 0x1a, 0xf0, 0x14, 0xc6,
+ 0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd, 0x12, 0xc5,
+ 0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1, 0xef, 0xe7,
+ 0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7, 0xf3, 0x49,
+ 0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49, 0xf4, 0xf1,
+ 0xe6, 0xe7, 0xb6, 0xc0, 0x6a, 0x14, 0xac, 0x13,
+ 0xd6, 0x13, 0xfa, 0x14, 0xa0, 0xd1, 0x00, 0x00,
+ 0xc0, 0x75, 0xd0, 0x49, 0x46, 0xf0, 0x26, 0x72,
+ 0xa7, 0x49, 0x43, 0xf0, 0x22, 0x72, 0x25, 0x25,
+ 0x20, 0x1f, 0x97, 0x30, 0x91, 0x30, 0x40, 0x73,
+ 0xf3, 0xc4, 0x1c, 0x40, 0x04, 0xf0, 0xd7, 0x49,
+ 0x05, 0xf1, 0x37, 0xe0, 0x53, 0x48, 0xc0, 0x9d,
+ 0x08, 0x02, 0x40, 0x66, 0x64, 0x27, 0x06, 0x16,
+ 0x30, 0xf1, 0x46, 0x63, 0x3b, 0x13, 0x2d, 0xf1,
+ 0x34, 0x9b, 0x18, 0x1b, 0x93, 0x30, 0x2b, 0xc3,
+ 0x10, 0x1c, 0x2b, 0xe8, 0x01, 0x14, 0x25, 0xf1,
+ 0x00, 0x1d, 0x26, 0x1a, 0x8a, 0x30, 0x22, 0x73,
+ 0xb5, 0x25, 0x0e, 0x0b, 0x00, 0x1c, 0x2c, 0xe8,
+ 0x1f, 0xc7, 0x27, 0x40, 0x1a, 0xf1, 0x38, 0xe8,
+ 0x32, 0x1f, 0x8f, 0x30, 0x08, 0x1b, 0x24, 0xe8,
+ 0x36, 0x72, 0x46, 0x77, 0x00, 0x17, 0x0d, 0xf0,
+ 0x13, 0xc3, 0x1f, 0x40, 0x03, 0xf1, 0x00, 0x1f,
+ 0x46, 0x9f, 0x44, 0x77, 0x9f, 0x44, 0x5f, 0x44,
+ 0x17, 0xe8, 0x0a, 0xc7, 0x27, 0x40, 0x05, 0xf1,
+ 0x02, 0xc3, 0x00, 0xbb, 0x50, 0x1a, 0x06, 0x1a,
+ 0xff, 0xc7, 0x00, 0xbf, 0xb8, 0xcd, 0xff, 0xff,
+ 0x02, 0x0c, 0x54, 0xa5, 0xdc, 0xa5, 0x2f, 0x40,
+ 0x05, 0xf1, 0x00, 0x14, 0xfa, 0xf1, 0x01, 0x1c,
+ 0x02, 0xe0, 0x00, 0x1c, 0x80, 0xff, 0xb0, 0x49,
+ 0x04, 0xf0, 0x01, 0x0b, 0xd3, 0xa1, 0x03, 0xe0,
+ 0x02, 0x0b, 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37,
+ 0x02, 0x0b, 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37,
+ 0x00, 0x13, 0xfb, 0xf1, 0x80, 0xff, 0x22, 0x73,
+ 0xb5, 0x25, 0x18, 0x1e, 0xde, 0x30, 0xd9, 0x30,
+ 0x64, 0x72, 0x11, 0x1e, 0x68, 0x23, 0x16, 0x31,
+ 0x80, 0xff, 0xd4, 0x49, 0x28, 0xf0, 0x02, 0xb4,
+ 0x2a, 0xc4, 0x00, 0x1d, 0x2e, 0xe8, 0xe0, 0x73,
+ 0xb9, 0x21, 0xbd, 0x25, 0x04, 0x13, 0x02, 0xf0,
+ 0x1a, 0xe0, 0x22, 0xc4, 0x23, 0xc3, 0x2f, 0xe8,
+ 0x23, 0xc3, 0x2d, 0xe8, 0x00, 0x1d, 0x21, 0xe8,
+ 0xe2, 0x73, 0xbb, 0x49, 0xfc, 0xf0, 0xe0, 0x73,
+ 0xb7, 0x48, 0x03, 0xb4, 0x81, 0x1d, 0x19, 0xe8,
+ 0x40, 0x1a, 0x84, 0x1d, 0x16, 0xe8, 0x12, 0xc3,
+ 0x1e, 0xe8, 0x03, 0xb0, 0x81, 0x1d, 0x11, 0xe8,
+ 0x0e, 0xc3, 0x19, 0xe8, 0x02, 0xb0, 0x06, 0xc7,
+ 0x04, 0x1e, 0xe0, 0x9e, 0x02, 0xc6, 0x00, 0xbe,
+ 0x22, 0x02, 0x20, 0xe4, 0x04, 0xb8, 0x34, 0xb0,
+ 0x00, 0x02, 0x00, 0x03, 0x00, 0x0e, 0x00, 0x0c,
+ 0x09, 0xc7, 0xe0, 0x9b, 0xe2, 0x9a, 0xe4, 0x9c,
+ 0xe6, 0x8d, 0xe6, 0x76, 0xef, 0x49, 0xfe, 0xf1,
+ 0x80, 0xff, 0x08, 0xea, 0x82, 0x1d, 0xf5, 0xef,
+ 0x00, 0x1a, 0x88, 0x1d, 0xf2, 0xef, 0xed, 0xc2,
+ 0xf0, 0xef, 0x80, 0xff, 0x02, 0xc6, 0x00, 0xbe,
+ 0x46, 0x06, 0x08, 0xc2, 0x40, 0x73, 0x3a, 0x48,
+ 0x40, 0x9b, 0x06, 0xff, 0x02, 0xc6, 0x00, 0xbe,
+ 0x86, 0x17, 0x1e, 0xfc, 0x36, 0xf0, 0x08, 0x1c,
+ 0xea, 0x8c, 0xe3, 0x64, 0xc7, 0x49, 0x25, 0xf1,
+ 0xe0, 0x75, 0xff, 0x1b, 0xeb, 0x47, 0xff, 0x1b,
+ 0x6b, 0x47, 0xe0, 0x9d, 0x15, 0xc3, 0x60, 0x75,
+ 0xd8, 0x49, 0x04, 0xf0, 0x81, 0x1d, 0xe2, 0x8d,
+ 0x05, 0xe0, 0xe2, 0x63, 0x81, 0x1d, 0xdd, 0x47,
+ 0xe2, 0x8b, 0x0b, 0xc3, 0x00, 0x1d, 0x61, 0x8d,
+ 0x3c, 0x03, 0x60, 0x75, 0xd8, 0x49, 0x06, 0xf1,
+ 0xdf, 0x48, 0x61, 0x95, 0x16, 0xe0, 0x4e, 0xe8,
+ 0x12, 0xe8, 0x21, 0xc5, 0xa0, 0x73, 0xb0, 0x49,
+ 0x03, 0xf0, 0x31, 0x48, 0xa0, 0x9b, 0x0d, 0xe0,
+ 0xc0, 0x49, 0x0b, 0xf1, 0xe2, 0x63, 0x7e, 0x1d,
+ 0xdd, 0x46, 0xe2, 0x8b, 0xe0, 0x75, 0x83, 0x1b,
+ 0xeb, 0x46, 0xfe, 0x1b, 0x6b, 0x46, 0xe0, 0x9d,
+ 0xe4, 0x49, 0x11, 0xf0, 0x10, 0x1d, 0xea, 0x8d,
+ 0xe3, 0x64, 0xc6, 0x49, 0x09, 0xf1, 0x07, 0xc5,
+ 0xa0, 0x73, 0xb1, 0x48, 0xa0, 0x9b, 0x02, 0xc5,
+ 0x00, 0xbd, 0xe6, 0x04, 0xa0, 0xd1, 0x02, 0xc5,
+ 0x00, 0xbd, 0xfe, 0x04, 0x02, 0xc5, 0x00, 0xbd,
+ 0x30, 0x05, 0x00, 0x00 };
+
+static u16 r8152b_ram_code1[] = {
+ 0x9700, 0x7fe0, 0x4c00, 0x4007, 0x4400, 0x4800, 0x7c1f, 0x4c00,
+ 0x5310, 0x6000, 0x7c07, 0x6800, 0x673e, 0x0000, 0x0000, 0x571f,
+ 0x5ffb, 0xaa05, 0x5b58, 0x7d80, 0x6100, 0x3019, 0x5b64, 0x7d80,
+ 0x6080, 0xa6f8, 0xdcdb, 0x0015, 0xb915, 0xb511, 0xd16b, 0x000f,
+ 0xb40f, 0xd06b, 0x000d, 0xb206, 0x7c01, 0x5800, 0x7c04, 0x5c00,
+ 0x3011, 0x7c01, 0x5801, 0x7c04, 0x5c04, 0x3019, 0x30a5, 0x3127,
+ 0x31d5, 0x7fe0, 0x4c60, 0x7c07, 0x6803, 0x7d00, 0x6900, 0x65a0,
+ 0x0000, 0x0000, 0xaf03, 0x6015, 0x303e, 0x6017, 0x57e0, 0x580c,
+ 0x588c, 0x7fdd, 0x5fa2, 0x4827, 0x7c1f, 0x4c00, 0x7c1f, 0x4c10,
+ 0x8400, 0x7c30, 0x6020, 0x48bf, 0x7c1f, 0x4c00, 0x7c1f, 0x4c01,
+ 0x7c07, 0x6803, 0xb806, 0x7c08, 0x6800, 0x0000, 0x0000, 0x305c,
+ 0x7c08, 0x6808, 0x0000, 0x0000, 0xae06, 0x7c02, 0x5c02, 0x0000,
+ 0x0000, 0x3067, 0x8e05, 0x7c02, 0x5c00, 0x0000, 0x0000, 0xad06,
+ 0x7c20, 0x5c20, 0x0000, 0x0000, 0x3072, 0x8d05, 0x7c20, 0x5c00,
+ 0x0000, 0x0000, 0xa008, 0x7c07, 0x6800, 0xb8db, 0x7c07, 0x6803,
+ 0xd9b3, 0x00d7, 0x7fe0, 0x4c80, 0x7c08, 0x6800, 0x0000, 0x0000,
+ 0x7c23, 0x5c23, 0x481d, 0x7c1f, 0x4c00, 0x7c1f, 0x4c02, 0x5310,
+ 0x81ff, 0x30f5, 0x7fe0, 0x4d00, 0x4832, 0x7c1f, 0x4c00, 0x7c1f,
+ 0x4c10, 0x7c08, 0x6000, 0xa49e, 0x7c07, 0x6800, 0xb89b, 0x7c07,
+ 0x6803, 0xd9b3, 0x00f9, 0x7fe0, 0x4d20, 0x7e00, 0x6200, 0x3001,
+ 0x7fe0, 0x4dc0, 0xd09d, 0x0002, 0xb4fe, 0x7fe0, 0x4d80, 0x7c04,
+ 0x6004, 0x7c07, 0x6802, 0x6728, 0x0000, 0x0000, 0x7c08, 0x6000,
+ 0x486c, 0x7c1f, 0x4c00, 0x7c1f, 0x4c01, 0x9503, 0x7e00, 0x6200,
+ 0x571f, 0x5fbb, 0xaa05, 0x5b58, 0x7d80, 0x6100, 0x30c2, 0x5b64,
+ 0x7d80, 0x6080, 0xcdab, 0x0063, 0xcd8d, 0x0061, 0xd96b, 0x005f,
+ 0xd0a0, 0x00d7, 0xcba0, 0x0003, 0x80ec, 0x30cf, 0x30dc, 0x7fe0,
+ 0x4ce0, 0x4832, 0x7c1f, 0x4c00, 0x7c1f, 0x4c08, 0x7c08, 0x6008,
+ 0x8300, 0xb902, 0x30a5, 0x308a, 0x7fe0, 0x4da0, 0x65a8, 0x0000,
+ 0x0000, 0x56a0, 0x590c, 0x7ffd, 0x5fa2, 0xae06, 0x7c02, 0x5c02,
+ 0x0000, 0x0000, 0x30f0, 0x8e05, 0x7c02, 0x5c00, 0x0000, 0x0000,
+ 0xcba4, 0x0004, 0xcd8d, 0x0002, 0x80f1, 0x7fe0, 0x4ca0, 0x7c08,
+ 0x6408, 0x0000, 0x0000, 0x7d00, 0x6800, 0xb603, 0x7c10, 0x6010,
+ 0x7d1f, 0x551f, 0x5fb3, 0xaa07, 0x7c80, 0x5800, 0x5b58, 0x7d80,
+ 0x6100, 0x310f, 0x7c80, 0x5800, 0x5b64, 0x7d80, 0x6080, 0x4827,
+ 0x7c1f, 0x4c00, 0x7c1f, 0x4c10, 0x8400, 0x7c10, 0x6000, 0x7fe0,
+ 0x4cc0, 0x5fbb, 0x4824, 0x7c1f, 0x4c00, 0x7c1f, 0x4c04, 0x8200,
+ 0x7ce0, 0x5400, 0x6728, 0x0000, 0x0000, 0x30cf, 0x3001, 0x7fe0,
+ 0x4e00, 0x4007, 0x4400, 0x5310, 0x7c07, 0x6800, 0x673e, 0x0000,
+ 0x0000, 0x570f, 0x5fff, 0xaa05, 0x585b, 0x7d80, 0x6100, 0x313b,
+ 0x5867, 0x7d80, 0x6080, 0x9403, 0x7e00, 0x6200, 0xcda3, 0x00e7,
+ 0xcd85, 0x00e5, 0xd96b, 0x00e3, 0x96e3, 0x7c07, 0x6800, 0x673e,
+ 0x0000, 0x0000, 0x7fe0, 0x4e20, 0x96db, 0x8b04, 0x7c08, 0x5008,
+ 0xab03, 0x7c08, 0x5000, 0x7c07, 0x6801, 0x677e, 0x0000, 0x0000,
+ 0xdb7c, 0x00ec, 0x0000, 0x7fe1, 0x4f40, 0x4837, 0x4418, 0x41c7,
+ 0x7fe0, 0x4e40, 0x7c40, 0x5400, 0x7c1f, 0x4c01, 0x7c1f, 0x4c01,
+ 0x8fbf, 0xd2a0, 0x004b, 0x9204, 0xa042, 0x3168, 0x3127, 0x7fe1,
+ 0x4f60, 0x489c, 0x4628, 0x7fe0, 0x4e60, 0x7e28, 0x4628, 0x7c40,
+ 0x5400, 0x7c01, 0x5800, 0x7c04, 0x5c00, 0x41e8, 0x7c1f, 0x4c01,
+ 0x7c1f, 0x4c01, 0x8fa5, 0xb241, 0xa02a, 0x3182, 0x7fe0, 0x4ea0,
+ 0x7c02, 0x4402, 0x4448, 0x4894, 0x7c1f, 0x4c01, 0x7c1f, 0x4c03,
+ 0x4824, 0x7c1f, 0x4c07, 0x41ef, 0x41ff, 0x4891, 0x7c1f, 0x4c07,
+ 0x7c1f, 0x4c17, 0x8400, 0x8ef8, 0x41c7, 0x8f8a, 0x92d5, 0xa10f,
+ 0xd480, 0x0008, 0xd580, 0x00b8, 0xa202, 0x319d, 0x7c04, 0x4404,
+ 0x319d, 0xd484, 0x00f3, 0xd484, 0x00f1, 0x3127, 0x7fe0, 0x4ee0,
+ 0x7c40, 0x5400, 0x4488, 0x41cf, 0x3127, 0x7fe0, 0x4ec0, 0x48f3,
+ 0x7c1f, 0x4c01, 0x7c1f, 0x4c09, 0x4508, 0x41c7, 0x8fb0, 0xd218,
+ 0x00ae, 0xd2a4, 0x009e, 0x31be, 0x7fe0, 0x4e80, 0x4832, 0x7c1f,
+ 0x4c01, 0x7c1f, 0x4c11, 0x4428, 0x7c40, 0x5440, 0x7c01, 0x5801,
+ 0x7c04, 0x5c04, 0x41e8, 0xa4b3, 0x31d3, 0x7fe0, 0x4f20, 0x7c07,
+ 0x6800, 0x673e, 0x0000, 0x0000, 0x570f, 0x5fff, 0xaa04, 0x585b,
+ 0x6100, 0x31e4, 0x5867, 0x6080, 0xbcf1, 0x3001 };
+
+static u16 r8152b_pla_patch_a_bp[] = {
+ 0xfc26, 0x8000, 0xfc28, 0x170b, 0xfc2a, 0x01e1, 0xfc2c, 0x0989,
+ 0xfc2e, 0x1349, 0xfc30, 0x01b7, 0xfc32, 0x061d, 0xe422, 0x0020,
+ 0xe420, 0x0018, 0xfc34, 0x1785, 0xfc36, 0x047b };
+
+static u8 r8152b_pla_patch_a2[] = {
+ 0x08, 0xe0, 0x1a, 0xe0, 0xf2, 0xe0, 0xfa, 0xe0,
+ 0x32, 0xe1, 0x34, 0xe1, 0x36, 0xe1, 0x38, 0xe1,
+ 0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13,
+ 0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13,
+ 0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13,
+ 0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3,
+ 0x00, 0xbb, 0xd2, 0x17, 0xbc, 0x17, 0x14, 0xc2,
+ 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b, 0x11, 0xc2,
+ 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0, 0xbf, 0x49,
+ 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd, 0xb1, 0x49,
+ 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b, 0x02, 0xc2,
+ 0x00, 0xba, 0x4e, 0x19, 0x00, 0xa0, 0x1e, 0xfc,
+ 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8, 0x00, 0x80,
+ 0x00, 0x60, 0x2c, 0x75, 0xd4, 0x49, 0x12, 0xf1,
+ 0x29, 0xe0, 0xf8, 0xc2, 0x46, 0x71, 0xf7, 0xc2,
+ 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1, 0xf5, 0xc7,
+ 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30, 0x26, 0x62,
+ 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72, 0xa0, 0x49,
+ 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f, 0x97, 0x30,
+ 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75, 0x32, 0xc3,
+ 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1, 0xdc, 0x21,
+ 0xbc, 0x25, 0x27, 0xc6, 0xc0, 0x77, 0x04, 0x13,
+ 0x18, 0xf0, 0x03, 0x13, 0x19, 0xf0, 0x02, 0x13,
+ 0x1a, 0xf0, 0x01, 0x13, 0x1b, 0xf0, 0xd4, 0x49,
+ 0x03, 0xf1, 0x1c, 0xc5, 0x00, 0xbd, 0xcd, 0xc6,
+ 0xc6, 0x67, 0x2e, 0x75, 0xd7, 0x22, 0xdd, 0x26,
+ 0x05, 0x15, 0x1a, 0xf0, 0x14, 0xc6, 0x00, 0xbe,
+ 0x13, 0xc5, 0x00, 0xbd, 0x12, 0xc5, 0x00, 0xbd,
+ 0xf1, 0x49, 0xfb, 0xf1, 0xef, 0xe7, 0xf4, 0x49,
+ 0xfa, 0xf1, 0xec, 0xe7, 0xf3, 0x49, 0xf7, 0xf1,
+ 0xe9, 0xe7, 0xf2, 0x49, 0xf4, 0xf1, 0xe6, 0xe7,
+ 0xb6, 0xc0, 0xf6, 0x14, 0x36, 0x14, 0x62, 0x14,
+ 0x86, 0x15, 0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75,
+ 0xd0, 0x49, 0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49,
+ 0x43, 0xf0, 0x22, 0x72, 0x25, 0x25, 0x20, 0x1f,
+ 0x97, 0x30, 0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4,
+ 0x1c, 0x40, 0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1,
+ 0x37, 0xe0, 0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02,
+ 0x40, 0x66, 0x64, 0x27, 0x06, 0x16, 0x30, 0xf1,
+ 0x46, 0x63, 0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b,
+ 0x18, 0x1b, 0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c,
+ 0x2b, 0xe8, 0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d,
+ 0x26, 0x1a, 0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25,
+ 0x0e, 0x0b, 0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7,
+ 0x27, 0x40, 0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f,
+ 0x8f, 0x30, 0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72,
+ 0x46, 0x77, 0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3,
+ 0x1f, 0x40, 0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f,
+ 0x44, 0x77, 0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8,
+ 0x0a, 0xc7, 0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3,
+ 0x00, 0xbb, 0x1c, 0x1b, 0xd2, 0x1a, 0xff, 0xc7,
+ 0x00, 0xbf, 0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c,
+ 0x54, 0xa5, 0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1,
+ 0x00, 0x14, 0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0,
+ 0x00, 0x1c, 0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0,
+ 0x01, 0x0b, 0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b,
+ 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37, 0x02, 0x0b,
+ 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37, 0x00, 0x13,
+ 0xfb, 0xf1, 0x80, 0xff, 0x22, 0x73, 0xb5, 0x25,
+ 0x18, 0x1e, 0xde, 0x30, 0xd9, 0x30, 0x64, 0x72,
+ 0x11, 0x1e, 0x68, 0x23, 0x16, 0x31, 0x80, 0xff,
+ 0x08, 0xc2, 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b,
+ 0x06, 0xff, 0x02, 0xc6, 0x00, 0xbe, 0x4e, 0x18,
+ 0x1e, 0xfc, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49,
+ 0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13,
+ 0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0,
+ 0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1,
+ 0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06,
+ 0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5,
+ 0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3,
+ 0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5,
+ 0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5,
+ 0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e,
+ 0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74,
+ 0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e,
+ 0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7,
+ 0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4,
+ 0x22, 0x02, 0xf0, 0xc0, 0x02, 0xc6, 0x00, 0xbe,
+ 0x00, 0x00, 0x02, 0xc6, 0x00, 0xbe, 0x00, 0x00,
+ 0x02, 0xc6, 0x00, 0xbe, 0x00, 0x00, 0x02, 0xc6,
+ 0x00, 0xbe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+static u16 r8152b_pla_patch_a2_bp[] = {
+ 0xfc28, 0x8000, 0xfc28, 0x17a5, 0xfc2a, 0x13ad,
+ 0xfc2c, 0x184d, 0xfc2e, 0x01e1 };
+
+static u16 r8153_ram_code_a[] = {
+ 0xE86C, 0xA000, 0xB436, 0xB820, 0xB438, 0x0290, 0xB436, 0xA012,
+ 0xB438, 0x0000, 0xB436, 0xA014, 0xB438, 0x2c04, 0xB438, 0x2c18,
+ 0xB438, 0x2c45, 0xB438, 0x2c45, 0xB438, 0xd502, 0xB438, 0x8301,
+ 0xB438, 0x8306, 0xB438, 0xd500, 0xB438, 0x8208, 0xB438, 0xd501,
+ 0xB438, 0xe018, 0xB438, 0x0308, 0xB438, 0x60f2, 0xB438, 0x8404,
+ 0xB438, 0x607d, 0xB438, 0xc117, 0xB438, 0x2c16, 0xB438, 0xc116,
+ 0xB438, 0x2c16, 0xB438, 0x607d, 0xB438, 0xc117, 0xB438, 0xa404,
+ 0xB438, 0xd500, 0xB438, 0x0800, 0xB438, 0xd501, 0xB438, 0x62d2,
+ 0xB438, 0x615d, 0xB438, 0xc115, 0xB438, 0xa404, 0xB438, 0xc307,
+ 0xB438, 0xd502, 0xB438, 0x8301, 0xB438, 0x8306, 0xB438, 0xd500,
+ 0xB438, 0x8208, 0xB438, 0x2c42, 0xB438, 0xc114, 0xB438, 0x8404,
+ 0xB438, 0xc317, 0xB438, 0xd701, 0xB438, 0x435d, 0xB438, 0xd500,
+ 0xB438, 0xa208, 0xB438, 0xd502, 0xB438, 0xa306, 0xB438, 0xa301,
+ 0xB438, 0x2c42, 0xB438, 0x8404, 0xB438, 0x613d, 0xB438, 0xc115,
+ 0xB438, 0xc307, 0xB438, 0xd502, 0xB438, 0x8301, 0xB438, 0x8306,
+ 0xB438, 0xd500, 0xB438, 0x8208, 0xB438, 0x2c42, 0xB438, 0xc114,
+ 0xB438, 0xc317, 0xB438, 0xd701, 0xB438, 0x40dd, 0xB438, 0xd500,
+ 0xB438, 0xa208, 0xB438, 0xd502, 0xB438, 0xa306, 0xB438, 0xa301,
+ 0xB438, 0xd500, 0xB438, 0xd702, 0xB438, 0x0800, 0xB436, 0xA01A,
+ 0xB438, 0x0000, 0xB436, 0xA006, 0xB438, 0x0fff, 0xB436, 0xA004,
+ 0xB438, 0x0fff, 0xB436, 0xA002, 0xB438, 0x05a3, 0xB436, 0xA000,
+ 0xB438, 0x3591, 0xB436, 0xB820, 0xB438, 0x0210 };
+
+static u8 r8153_usb_patch_c[] = {
+ 0x08, 0xe0, 0x0a, 0xe0, 0x14, 0xe0, 0x2e, 0xe0,
+ 0x37, 0xe0, 0x3e, 0xe0, 0x6d, 0xe0, 0x78, 0xe0,
+ 0x02, 0xc5, 0x00, 0xbd, 0x38, 0x3b, 0xdb, 0x49,
+ 0x04, 0xf1, 0x06, 0xc3, 0x00, 0xbb, 0x5a, 0x02,
+ 0x05, 0xc4, 0x03, 0xc3, 0x00, 0xbb, 0xa4, 0x04,
+ 0x7e, 0x02, 0x30, 0xd4, 0x30, 0x18, 0x18, 0xc1,
+ 0x0c, 0xe8, 0x17, 0xc6, 0xc7, 0x65, 0xd0, 0x49,
+ 0x05, 0xf0, 0x32, 0x48, 0x02, 0xc2, 0x00, 0xba,
+ 0x3e, 0x16, 0x02, 0xc2, 0x00, 0xba, 0x48, 0x16,
+ 0x02, 0xb4, 0x09, 0xc2, 0x40, 0x99, 0x0e, 0x48,
+ 0x42, 0x98, 0x42, 0x70, 0x8e, 0x49, 0xfe, 0xf1,
+ 0x02, 0xb0, 0x80, 0xff, 0xc0, 0xd4, 0xe4, 0x40,
+ 0x20, 0xd4, 0xb0, 0x49, 0x04, 0xf0, 0x30, 0x18,
+ 0x06, 0xc1, 0xef, 0xef, 0xfa, 0xc7, 0x02, 0xc0,
+ 0x00, 0xb8, 0xd0, 0x10, 0xe4, 0x4b, 0x07, 0xc3,
+ 0x70, 0x61, 0x12, 0x48, 0x70, 0x89, 0x02, 0xc3,
+ 0x00, 0xbb, 0x9c, 0x15, 0x20, 0xd4, 0x2b, 0xc5,
+ 0xa0, 0x77, 0x00, 0x1c, 0xa0, 0x9c, 0x28, 0xc5,
+ 0xa0, 0x64, 0xc0, 0x48, 0xc1, 0x48, 0xc2, 0x48,
+ 0xa0, 0x8c, 0xb1, 0x64, 0xc0, 0x48, 0xb1, 0x8c,
+ 0x20, 0xc5, 0xa0, 0x64, 0x40, 0x48, 0x41, 0x48,
+ 0xc2, 0x48, 0xa0, 0x8c, 0x19, 0xc5, 0xa4, 0x64,
+ 0x44, 0x48, 0xa4, 0x8c, 0xb1, 0x64, 0x40, 0x48,
+ 0xb1, 0x8c, 0x14, 0xc4, 0x80, 0x73, 0x13, 0xc4,
+ 0x82, 0x9b, 0x11, 0x1b, 0x80, 0x9b, 0x0c, 0xc5,
+ 0xa0, 0x64, 0x40, 0x48, 0x41, 0x48, 0x42, 0x48,
+ 0xa0, 0x8c, 0x05, 0xc5, 0xa0, 0x9f, 0x02, 0xc5,
+ 0x00, 0xbd, 0x6c, 0x3a, 0x1e, 0xfc, 0x10, 0xd8,
+ 0x86, 0xd4, 0xf8, 0xcb, 0x20, 0xe4, 0x0a, 0xc0,
+ 0x16, 0x61, 0x91, 0x48, 0x16, 0x89, 0x07, 0xc0,
+ 0x11, 0x19, 0x0c, 0x89, 0x02, 0xc1, 0x00, 0xb9,
+ 0x02, 0x06, 0x00, 0xd4, 0x40, 0xb4, 0xfe, 0xc0,
+ 0x16, 0x61, 0x91, 0x48, 0x16, 0x89, 0xfb, 0xc0,
+ 0x11, 0x19, 0x0c, 0x89, 0x02, 0xc1, 0x00, 0xb9,
+ 0xd2, 0x05, 0x00, 0x00 };
+
+static u16 r8153_usb_patch_c_bp[] = {
+ 0xfc26, 0xa000, 0xfc28, 0x3b34, 0xfc2a, 0x027c, 0xfc2c, 0x162c,
+ 0xfc2e, 0x10ce, 0xfc30, 0x0000, 0xfc32, 0x3a28, 0xfc34, 0x05f8,
+ 0xfc36, 0x05c8 };
+
+static u8 r8153_pla_patch_c[] = {
+ 0x08, 0xe0, 0xea, 0xe0, 0xf2, 0xe0, 0x04, 0xe1,
+ 0x06, 0xe1, 0x08, 0xe1, 0x40, 0xe1, 0xf1, 0xe1,
+ 0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b,
+ 0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0,
+ 0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd,
+ 0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b,
+ 0x02, 0xc2, 0x00, 0xba, 0xde, 0x18, 0x00, 0xe0,
+ 0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8,
+ 0x00, 0x80, 0x00, 0x20, 0x2c, 0x75, 0xd4, 0x49,
+ 0x12, 0xf1, 0x32, 0xe0, 0xf8, 0xc2, 0x46, 0x71,
+ 0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1,
+ 0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30,
+ 0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72,
+ 0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f,
+ 0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75,
+ 0x3c, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1,
+ 0xdc, 0x21, 0xbc, 0x25, 0x30, 0xc6, 0xc0, 0x77,
+ 0x04, 0x13, 0x21, 0xf0, 0x03, 0x13, 0x22, 0xf0,
+ 0x02, 0x13, 0x23, 0xf0, 0x01, 0x13, 0x24, 0xf0,
+ 0x08, 0x13, 0x08, 0xf1, 0x2e, 0x73, 0xba, 0x21,
+ 0xbd, 0x25, 0x05, 0x13, 0x03, 0xf1, 0x24, 0xc5,
+ 0x00, 0xbd, 0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5,
+ 0x00, 0xbd, 0xc4, 0xc6, 0xc6, 0x67, 0x2e, 0x75,
+ 0xd7, 0x22, 0xdd, 0x26, 0x05, 0x15, 0x1b, 0xf0,
+ 0x14, 0xc6, 0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd,
+ 0x12, 0xc5, 0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1,
+ 0xef, 0xe7, 0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7,
+ 0xf3, 0x49, 0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49,
+ 0xf4, 0xf1, 0xe6, 0xe7, 0xb6, 0xc0, 0x50, 0x14,
+ 0x90, 0x13, 0xbc, 0x13, 0xf2, 0x14, 0x00, 0xa0,
+ 0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75, 0xd0, 0x49,
+ 0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49, 0x43, 0xf0,
+ 0x22, 0x72, 0x25, 0x25, 0x20, 0x1f, 0x97, 0x30,
+ 0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4, 0x1c, 0x40,
+ 0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1, 0x37, 0xe0,
+ 0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02, 0x40, 0x66,
+ 0x64, 0x27, 0x06, 0x16, 0x30, 0xf1, 0x46, 0x63,
+ 0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b, 0x18, 0x1b,
+ 0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c, 0x2b, 0xe8,
+ 0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d, 0x26, 0x1a,
+ 0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25, 0x0e, 0x0b,
+ 0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7, 0x27, 0x40,
+ 0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f, 0x8f, 0x30,
+ 0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72, 0x46, 0x77,
+ 0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3, 0x1f, 0x40,
+ 0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f, 0x44, 0x77,
+ 0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8, 0x0a, 0xc7,
+ 0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3, 0x00, 0xbb,
+ 0xbe, 0x1a, 0x74, 0x14, 0xff, 0xc7, 0x00, 0xbf,
+ 0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c, 0x54, 0xa5,
+ 0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1, 0x00, 0x14,
+ 0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0, 0x00, 0x1c,
+ 0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0, 0x01, 0x0b,
+ 0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b, 0xd3, 0xa5,
+ 0x27, 0x31, 0x20, 0x37, 0x02, 0x0b, 0xd3, 0xa5,
+ 0x27, 0x31, 0x20, 0x37, 0x00, 0x13, 0xfb, 0xf1,
+ 0x80, 0xff, 0x22, 0x73, 0xb5, 0x25, 0x18, 0x1e,
+ 0xde, 0x30, 0xd9, 0x30, 0x64, 0x72, 0x11, 0x1e,
+ 0x68, 0x23, 0x16, 0x31, 0x80, 0xff, 0x08, 0xc2,
+ 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b, 0x06, 0xff,
+ 0x02, 0xc6, 0x00, 0xbe, 0xcc, 0x17, 0x1e, 0xfc,
+ 0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13,
+ 0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13,
+ 0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13,
+ 0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3,
+ 0x00, 0xbb, 0x50, 0x17, 0x3a, 0x17, 0x02, 0xc6,
+ 0x00, 0xbe, 0x00, 0x00, 0x02, 0xc6, 0x00, 0xbe,
+ 0x00, 0x00, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49,
+ 0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13,
+ 0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0,
+ 0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1,
+ 0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06,
+ 0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5,
+ 0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3,
+ 0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5,
+ 0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5,
+ 0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e,
+ 0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74,
+ 0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e,
+ 0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7,
+ 0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4,
+ 0xfa, 0x01, 0xf0, 0xc0, 0x18, 0x89, 0x00, 0x1d,
+ 0x43, 0xc3, 0x62, 0x62, 0xa0, 0x49, 0x06, 0xf0,
+ 0x41, 0xc0, 0x02, 0x71, 0x60, 0x99, 0x3f, 0xc1,
+ 0x03, 0xe0, 0x3c, 0xc0, 0x3d, 0xc1, 0x02, 0x99,
+ 0x00, 0x61, 0x67, 0x11, 0x3d, 0xf1, 0x69, 0x33,
+ 0x34, 0xc0, 0x28, 0x40, 0xf7, 0xf1, 0x35, 0xc0,
+ 0x00, 0x19, 0x81, 0x1b, 0x89, 0xe8, 0x32, 0xc0,
+ 0x04, 0x1a, 0x84, 0x1b, 0x85, 0xe8, 0x7a, 0xe8,
+ 0xa3, 0x49, 0xfe, 0xf0, 0x2c, 0xc0, 0x76, 0xe8,
+ 0xa1, 0x48, 0x29, 0xc0, 0x84, 0x1b, 0x7c, 0xe8,
+ 0x00, 0x1d, 0x69, 0x33, 0x00, 0x1e, 0x01, 0x06,
+ 0xff, 0x18, 0x30, 0x40, 0xfd, 0xf1, 0x7f, 0xc0,
+ 0x00, 0x76, 0x2e, 0x40, 0xf7, 0xf1, 0x21, 0x48,
+ 0x1a, 0xc0, 0x84, 0x1b, 0x6d, 0xe8, 0x76, 0xc0,
+ 0x61, 0xe8, 0xa1, 0x49, 0xfd, 0xf0, 0x12, 0xc0,
+ 0x00, 0x1a, 0x84, 0x1b, 0x65, 0xe8, 0x5a, 0xe8,
+ 0xa5, 0x49, 0xfe, 0xf0, 0x0a, 0xc0, 0x01, 0x19,
+ 0x81, 0x1b, 0x5e, 0xe8, 0x48, 0xe0, 0x8c, 0xd3,
+ 0xb8, 0x0b, 0x50, 0xe8, 0x83, 0x00, 0x82, 0x00,
+ 0x20, 0xb4, 0x10, 0xd8, 0x84, 0xd4, 0xfa, 0xc0,
+ 0x00, 0x61, 0x9c, 0x20, 0x9c, 0x24, 0x06, 0x11,
+ 0x06, 0xf1, 0x5d, 0xc0, 0x00, 0x61, 0x11, 0x48,
+ 0x00, 0x89, 0x35, 0xe0, 0x00, 0x11, 0x02, 0xf1,
+ 0x03, 0xe0, 0x04, 0x11, 0x06, 0xf1, 0x53, 0xc0,
+ 0x00, 0x61, 0x92, 0x48, 0x00, 0x89, 0x2b, 0xe0,
+ 0x05, 0x11, 0x08, 0xf1, 0x4c, 0xc0, 0x00, 0x61,
+ 0x91, 0x49, 0x04, 0xf0, 0x91, 0x48, 0x00, 0x89,
+ 0x11, 0xe0, 0xdc, 0xc0, 0x00, 0x61, 0x98, 0x20,
+ 0x98, 0x24, 0x25, 0x11, 0x1c, 0xf1, 0x40, 0xc0,
+ 0x25, 0xe8, 0x95, 0x49, 0x18, 0xf0, 0xd2, 0xc0,
+ 0x00, 0x61, 0x98, 0x20, 0x98, 0x24, 0x25, 0x11,
+ 0x12, 0xf1, 0x35, 0xc0, 0x00, 0x61, 0x92, 0x49,
+ 0x0e, 0xf1, 0x12, 0x48, 0x00, 0x89, 0x2d, 0xc0,
+ 0x00, 0x19, 0x00, 0x89, 0x2b, 0xc0, 0x01, 0x89,
+ 0x27, 0xc0, 0x10, 0xe8, 0x25, 0xc0, 0x12, 0x48,
+ 0x81, 0x1b, 0x16, 0xe8, 0xb9, 0xc3, 0x62, 0x62,
+ 0xa0, 0x49, 0x05, 0xf0, 0xb5, 0xc3, 0x60, 0x71,
+ 0xb5, 0xc0, 0x02, 0x99, 0x02, 0xc0, 0x00, 0xb8,
+ 0xd6, 0x07, 0x13, 0xc4, 0x84, 0x98, 0x00, 0x1b,
+ 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1,
+ 0x80, 0x71, 0x82, 0x72, 0x80, 0xff, 0x09, 0xc4,
+ 0x84, 0x98, 0x80, 0x99, 0x82, 0x9a, 0x86, 0x8b,
+ 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0xff,
+ 0x08, 0xea, 0x10, 0xd4, 0x88, 0xd3, 0x30, 0xd4,
+ 0x10, 0xc0, 0x12, 0xe8, 0x8a, 0xd3, 0x00, 0xd8,
+ 0x02, 0xc0, 0x00, 0xb8, 0xe0, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+static u16 r8153_pla_patch_c_bp[] = {
+ 0xfc26, 0x8000, 0xfc28, 0x1306, 0xfc2a, 0x17ca, 0xfc2c, 0x171e,
+ 0xfc2e, 0x0000, 0xfc30, 0x0000, 0xfc32, 0x01b4, 0xfc34, 0x07d4,
+ 0xfc36, 0x0894, 0xfc38, 0x00e7 };
+
+static u16 r8153_ram_code_bc[] = {
+ 0xB436, 0xB820, 0xB438, 0x0290, 0xB436, 0xA012, 0xB438, 0x0000,
+ 0xB436, 0xA014, 0xB438, 0x2c04, 0xB438, 0x2c07, 0xB438, 0x2c0a,
+ 0xB438, 0x2c0d, 0xB438, 0xa240, 0xB438, 0xa104, 0xB438, 0x292d,
+ 0xB438, 0x8620, 0xB438, 0xa480, 0xB438, 0x2a2c, 0xB438, 0x8480,
+ 0xB438, 0xa101, 0xB438, 0x2a36, 0xB438, 0xd056, 0xB438, 0x2223,
+ 0xB436, 0xA01A, 0xB438, 0x0000, 0xB436, 0xA006, 0xB438, 0x0222,
+ 0xB436, 0xA004, 0xB438, 0x0a35, 0xB436, 0xA002, 0xB438, 0x0a2b,
+ 0xB436, 0xA000, 0xB438, 0xf92c, 0xB436, 0xB820, 0xB438, 0x0210 };
+
+static u8 r8153_usb_patch_b[] = {
+ 0x08, 0xe0, 0x0f, 0xe0, 0x18, 0xe0, 0x24, 0xe0,
+ 0x26, 0xe0, 0x3a, 0xe0, 0x84, 0xe0, 0x9c, 0xe0,
+ 0xc2, 0x49, 0x04, 0xf0, 0x02, 0xc0, 0x00, 0xb8,
+ 0x14, 0x18, 0x02, 0xc0, 0x00, 0xb8, 0x2e, 0x18,
+ 0x06, 0x89, 0x08, 0xc0, 0x0c, 0x61, 0x92, 0x48,
+ 0x93, 0x48, 0x0c, 0x89, 0x02, 0xc0, 0x00, 0xb8,
+ 0x08, 0x05, 0x40, 0xb4, 0x16, 0x89, 0x6d, 0xc0,
+ 0x00, 0x61, 0x95, 0x49, 0x06, 0xf0, 0xfa, 0xc0,
+ 0x0c, 0x61, 0x92, 0x48, 0x93, 0x48, 0x0c, 0x89,
+ 0x02, 0xc0, 0x00, 0xb8, 0xe2, 0x04, 0x02, 0xc2,
+ 0x00, 0xba, 0xec, 0x11, 0x60, 0x60, 0x85, 0x49,
+ 0x0d, 0xf1, 0x11, 0xc6, 0xd2, 0x61, 0x91, 0x49,
+ 0xfd, 0xf0, 0x74, 0x60, 0x04, 0x48, 0x74, 0x88,
+ 0x08, 0xc6, 0x08, 0xc0, 0xc4, 0x98, 0x01, 0x18,
+ 0xc0, 0x88, 0x02, 0xc0, 0x00, 0xb8, 0x6e, 0x12,
+ 0x04, 0xe4, 0x0d, 0x00, 0x00, 0xd4, 0xd1, 0x49,
+ 0x3c, 0xf1, 0xd2, 0x49, 0x16, 0xf1, 0xd3, 0x49,
+ 0x18, 0xf1, 0xd4, 0x49, 0x19, 0xf1, 0xd5, 0x49,
+ 0x1a, 0xf1, 0xd6, 0x49, 0x1b, 0xf1, 0xd7, 0x49,
+ 0x1c, 0xf1, 0xd8, 0x49, 0x1d, 0xf1, 0xd9, 0x49,
+ 0x20, 0xf1, 0xda, 0x49, 0x23, 0xf1, 0xdb, 0x49,
+ 0x24, 0xf1, 0x02, 0xc4, 0x00, 0xbc, 0x20, 0x04,
+ 0xe5, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x14, 0x02,
+ 0x02, 0xc4, 0x00, 0xbc, 0x16, 0x02, 0x02, 0xc4,
+ 0x00, 0xbc, 0x18, 0x02, 0x02, 0xc4, 0x00, 0xbc,
+ 0x1a, 0x02, 0x02, 0xc4, 0x00, 0xbc, 0x1c, 0x02,
+ 0x02, 0xc4, 0x00, 0xbc, 0x94, 0x02, 0x10, 0xc7,
+ 0xe0, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x8a, 0x02,
+ 0x0b, 0xc7, 0xe4, 0x8e, 0x02, 0xc4, 0x00, 0xbc,
+ 0x88, 0x02, 0x02, 0xc4, 0x00, 0xbc, 0x6e, 0x02,
+ 0x02, 0xc4, 0x00, 0xbc, 0x5a, 0x02, 0x30, 0xe4,
+ 0x0c, 0xc3, 0x60, 0x64, 0xc5, 0x49, 0x04, 0xf1,
+ 0x74, 0x64, 0xc4, 0x48, 0x74, 0x8c, 0x06, 0xc3,
+ 0x64, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x20, 0x04,
+ 0x00, 0xd8, 0x00, 0xe4, 0xb2, 0xc0, 0x00, 0x61,
+ 0x90, 0x49, 0x09, 0xf1, 0x8b, 0xc6, 0xca, 0x61,
+ 0x94, 0x49, 0x0e, 0xf1, 0xf6, 0xc6, 0xda, 0x60,
+ 0x81, 0x49, 0x0a, 0xf0, 0x65, 0x60, 0x03, 0x48,
+ 0x65, 0x88, 0xef, 0xc6, 0xdc, 0x60, 0x80, 0x48,
+ 0xdc, 0x88, 0x05, 0xc6, 0x00, 0xbe, 0x02, 0xc6,
+ 0x00, 0xbe, 0x36, 0x13, 0x4c, 0x17, 0x99, 0xc4,
+ 0x80, 0x65, 0xd0, 0x49, 0x04, 0xf1, 0xfa, 0x75,
+ 0x04, 0xc4, 0x00, 0xbc, 0x03, 0xc4, 0x00, 0xbc,
+ 0x9a, 0x00, 0xee, 0x01 };
+
+static u16 r8153_usb_patch_b_bp[] = {
+ 0xfc26, 0xa000, 0xfc28, 0x180c, 0xfc2a, 0x0506, 0xfc2c, 0x04E0,
+ 0xfc2e, 0x11E4, 0xfc30, 0x125C, 0xfc32, 0x0232, 0xfc34, 0x131E,
+ 0xfc36, 0x0098, 0xfc38, 0x00FF };
+
+static u8 r8153_pla_patch_b[] = {
+ 0x08, 0xe0, 0xea, 0xe0, 0xf2, 0xe0, 0x04, 0xe1,
+ 0x09, 0xe1, 0x0e, 0xe1, 0x46, 0xe1, 0xf3, 0xe1,
+ 0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b,
+ 0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0,
+ 0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd,
+ 0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b,
+ 0x02, 0xc2, 0x00, 0xba, 0x1a, 0x17, 0x00, 0xe0,
+ 0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8,
+ 0x00, 0x80, 0x00, 0x20, 0x2c, 0x75, 0xd4, 0x49,
+ 0x12, 0xf1, 0x32, 0xe0, 0xf8, 0xc2, 0x46, 0x71,
+ 0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1,
+ 0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30,
+ 0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72,
+ 0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f,
+ 0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75,
+ 0x3c, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1,
+ 0xdc, 0x21, 0xbc, 0x25, 0x30, 0xc6, 0xc0, 0x77,
+ 0x04, 0x13, 0x21, 0xf0, 0x03, 0x13, 0x22, 0xf0,
+ 0x02, 0x13, 0x23, 0xf0, 0x01, 0x13, 0x24, 0xf0,
+ 0x08, 0x13, 0x08, 0xf1, 0x2e, 0x73, 0xba, 0x21,
+ 0xbd, 0x25, 0x05, 0x13, 0x03, 0xf1, 0x24, 0xc5,
+ 0x00, 0xbd, 0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5,
+ 0x00, 0xbd, 0xc4, 0xc6, 0xc6, 0x67, 0x2e, 0x75,
+ 0xd7, 0x22, 0xdd, 0x26, 0x05, 0x15, 0x1b, 0xf0,
+ 0x14, 0xc6, 0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd,
+ 0x12, 0xc5, 0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1,
+ 0xef, 0xe7, 0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7,
+ 0xf3, 0x49, 0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49,
+ 0xf4, 0xf1, 0xe6, 0xe7, 0xb6, 0xc0, 0x9e, 0x12,
+ 0xde, 0x11, 0x0a, 0x12, 0x3c, 0x13, 0x00, 0xa0,
+ 0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75, 0xd0, 0x49,
+ 0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49, 0x43, 0xf0,
+ 0x22, 0x72, 0x25, 0x25, 0x20, 0x1f, 0x97, 0x30,
+ 0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4, 0x1c, 0x40,
+ 0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1, 0x37, 0xe0,
+ 0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02, 0x40, 0x66,
+ 0x64, 0x27, 0x06, 0x16, 0x30, 0xf1, 0x46, 0x63,
+ 0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b, 0x18, 0x1b,
+ 0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c, 0x2b, 0xe8,
+ 0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d, 0x26, 0x1a,
+ 0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25, 0x0e, 0x0b,
+ 0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7, 0x27, 0x40,
+ 0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f, 0x8f, 0x30,
+ 0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72, 0x46, 0x77,
+ 0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3, 0x1f, 0x40,
+ 0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f, 0x44, 0x77,
+ 0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8, 0x0a, 0xc7,
+ 0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3, 0x00, 0xbb,
+ 0xfa, 0x18, 0xb0, 0x18, 0xff, 0xc7, 0x00, 0xbf,
+ 0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c, 0x54, 0xa5,
+ 0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1, 0x00, 0x14,
+ 0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0, 0x00, 0x1c,
+ 0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0, 0x01, 0x0b,
+ 0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b, 0xd3, 0xa5,
+ 0x27, 0x31, 0x20, 0x37, 0x02, 0x0b, 0xd3, 0xa5,
+ 0x27, 0x31, 0x20, 0x37, 0x00, 0x13, 0xfb, 0xf1,
+ 0x80, 0xff, 0x22, 0x73, 0xb5, 0x25, 0x18, 0x1e,
+ 0xde, 0x30, 0xd9, 0x30, 0x64, 0x72, 0x11, 0x1e,
+ 0x68, 0x23, 0x16, 0x31, 0x80, 0xff, 0x08, 0xc2,
+ 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b, 0x06, 0xff,
+ 0x02, 0xc6, 0x00, 0xbe, 0x08, 0x16, 0x1e, 0xfc,
+ 0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13,
+ 0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13,
+ 0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13,
+ 0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3,
+ 0x00, 0xbb, 0x8c, 0x15, 0x76, 0x15, 0xa0, 0x64,
+ 0x40, 0x48, 0xa0, 0x8c, 0x02, 0xc4, 0x00, 0xbc,
+ 0x82, 0x00, 0xa0, 0x62, 0x21, 0x48, 0xa0, 0x8a,
+ 0x02, 0xc2, 0x00, 0xba, 0x40, 0x03, 0x33, 0xc5,
+ 0xa0, 0x74, 0xc0, 0x49, 0x1f, 0xf0, 0x30, 0xc5,
+ 0xa0, 0x73, 0x00, 0x13, 0x04, 0xf1, 0xa2, 0x73,
+ 0x00, 0x13, 0x14, 0xf0, 0x28, 0xc5, 0xa0, 0x74,
+ 0xc8, 0x49, 0x1b, 0xf1, 0x26, 0xc5, 0xa0, 0x76,
+ 0xa2, 0x74, 0x01, 0x06, 0x20, 0x37, 0xa0, 0x9e,
+ 0xa2, 0x9c, 0x1e, 0xc5, 0xa2, 0x73, 0x23, 0x40,
+ 0x10, 0xf8, 0x04, 0xf3, 0xa0, 0x73, 0x33, 0x40,
+ 0x0c, 0xf8, 0x15, 0xc5, 0xa0, 0x74, 0x41, 0x48,
+ 0xa0, 0x9c, 0x14, 0xc5, 0xa0, 0x76, 0x62, 0x48,
+ 0xe0, 0x48, 0xa0, 0x9e, 0x10, 0xc6, 0x00, 0xbe,
+ 0x0a, 0xc5, 0xa0, 0x74, 0x48, 0x48, 0xa0, 0x9c,
+ 0x0b, 0xc5, 0x20, 0x1e, 0xa0, 0x9e, 0xe5, 0x48,
+ 0xa0, 0x9e, 0xf0, 0xe7, 0xbc, 0xc0, 0xc8, 0xd2,
+ 0xcc, 0xd2, 0x28, 0xe4, 0xe6, 0x01, 0xf0, 0xc0,
+ 0x18, 0x89, 0x00, 0x1d, 0x3c, 0xc3, 0x60, 0x71,
+ 0x3c, 0xc0, 0x02, 0x99, 0x00, 0x61, 0x67, 0x11,
+ 0x3c, 0xf1, 0x69, 0x33, 0x35, 0xc0, 0x28, 0x40,
+ 0xf6, 0xf1, 0x34, 0xc0, 0x00, 0x19, 0x81, 0x1b,
+ 0x8c, 0xe8, 0x31, 0xc0, 0x04, 0x1a, 0x84, 0x1b,
+ 0x88, 0xe8, 0x7d, 0xe8, 0xa3, 0x49, 0xfe, 0xf0,
+ 0x2b, 0xc0, 0x79, 0xe8, 0xa1, 0x48, 0x28, 0xc0,
+ 0x84, 0x1b, 0x7f, 0xe8, 0x00, 0x1d, 0x69, 0x33,
+ 0x00, 0x1e, 0x01, 0x06, 0xff, 0x18, 0x30, 0x40,
+ 0xfd, 0xf1, 0x18, 0xc0, 0x00, 0x76, 0x2e, 0x40,
+ 0xf7, 0xf1, 0x21, 0x48, 0x19, 0xc0, 0x84, 0x1b,
+ 0x70, 0xe8, 0x79, 0xc0, 0x64, 0xe8, 0xa1, 0x49,
+ 0xfd, 0xf0, 0x11, 0xc0, 0x00, 0x1a, 0x84, 0x1b,
+ 0x68, 0xe8, 0x5d, 0xe8, 0xa5, 0x49, 0xfe, 0xf0,
+ 0x09, 0xc0, 0x01, 0x19, 0x81, 0x1b, 0x61, 0xe8,
+ 0x4f, 0xe0, 0x88, 0xd3, 0x8c, 0xd3, 0xb8, 0x0b,
+ 0x50, 0xe8, 0x20, 0xb4, 0x10, 0xd8, 0x84, 0xd4,
+ 0xfc, 0xc0, 0x00, 0x61, 0x9c, 0x20, 0x9c, 0x24,
+ 0x06, 0x11, 0x06, 0xf1, 0x60, 0xc0, 0x00, 0x61,
+ 0x11, 0x48, 0x00, 0x89, 0x3d, 0xe0, 0x00, 0x11,
+ 0x02, 0xf1, 0x03, 0xe0, 0x04, 0x11, 0x06, 0xf1,
+ 0x56, 0xc0, 0x00, 0x61, 0x92, 0x48, 0x00, 0x89,
+ 0x33, 0xe0, 0x05, 0x11, 0x08, 0xf1, 0x4f, 0xc0,
+ 0x00, 0x61, 0x91, 0x49, 0x04, 0xf0, 0x91, 0x48,
+ 0x00, 0x89, 0x11, 0xe0, 0xde, 0xc0, 0x00, 0x61,
+ 0x98, 0x20, 0x98, 0x24, 0x25, 0x11, 0x24, 0xf1,
+ 0x45, 0xc0, 0x29, 0xe8, 0x95, 0x49, 0x20, 0xf0,
+ 0xd4, 0xc0, 0x00, 0x61, 0x98, 0x20, 0x98, 0x24,
+ 0x25, 0x11, 0x1a, 0xf1, 0x38, 0xc0, 0x00, 0x61,
+ 0x92, 0x49, 0x16, 0xf1, 0x12, 0x48, 0x00, 0x89,
+ 0x30, 0xc0, 0x00, 0x19, 0x00, 0x89, 0x2e, 0xc0,
+ 0x01, 0x89, 0x2e, 0xc0, 0x04, 0x19, 0x81, 0x1b,
+ 0x1c, 0xe8, 0x2b, 0xc0, 0x14, 0x19, 0x81, 0x1b,
+ 0x18, 0xe8, 0x22, 0xc0, 0x0c, 0xe8, 0x20, 0xc0,
+ 0x12, 0x48, 0x81, 0x1b, 0x12, 0xe8, 0xb3, 0xc3,
+ 0x62, 0x71, 0xb3, 0xc0, 0x02, 0x99, 0x02, 0xc0,
+ 0x00, 0xb8, 0x96, 0x07, 0x13, 0xc4, 0x84, 0x98,
+ 0x00, 0x1b, 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49,
+ 0xfe, 0xf1, 0x80, 0x71, 0x82, 0x72, 0x80, 0xff,
+ 0x09, 0xc4, 0x84, 0x98, 0x80, 0x99, 0x82, 0x9a,
+ 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1,
+ 0x80, 0xff, 0x08, 0xea, 0x10, 0xd4, 0x30, 0xd4,
+ 0x10, 0xc0, 0x12, 0xe8, 0x8a, 0xd3, 0x28, 0xe4,
+ 0x2c, 0xe4, 0x00, 0xd8, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+static u16 r8153_pla_patch_b_bp[] = {
+ 0xfc26, 0x8000, 0xfc28, 0x1154, 0xfc2a, 0x1606, 0xfc2c, 0x155a,
+ 0xfc2e, 0x0080, 0xfc30, 0x033c, 0xfc32, 0x01a0, 0xfc34, 0x0794,
+ 0xfc36, 0x0000, 0xfc38, 0x007f };
+
+static u16 r8153_ram_code_d[] = {
+ 0xa436, 0xb820, 0xa438, 0x0290, 0xa436, 0xa012, 0xa438, 0x0000,
+ 0xa436, 0xa014, 0xa438, 0x2c04, 0xb438, 0x2c07, 0xb438, 0x2c07,
+ 0xb438, 0x2c07, 0xb438, 0xa240, 0xb438, 0xa104, 0xb438, 0x2944,
+ 0xa436, 0xa01a, 0xa438, 0x0000, 0xa436, 0xa006, 0xa438, 0x0fff,
+ 0xa436, 0xa004, 0xa438, 0x0fff, 0xa436, 0xa002, 0xa438, 0x0fff,
+ 0xa436, 0xa000, 0xa438, 0x1943, 0xa436, 0xb820, 0xa438, 0x0210 };
+
+static u8 usb_patch_d[] = {
+ 0x08, 0xe0, 0x0a, 0xe0, 0x0c, 0xe0, 0x1f, 0xe0,
+ 0x28, 0xe0, 0x2a, 0xe0, 0x2c, 0xe0, 0x2e, 0xe0,
+ 0x02, 0xc5, 0x00, 0xbd, 0x00, 0x00, 0x02, 0xc3,
+ 0x00, 0xbb, 0x00, 0x00, 0x30, 0x18, 0x11, 0xc1,
+ 0x05, 0xe8, 0x10, 0xc6, 0x02, 0xc2, 0x00, 0xba,
+ 0x94, 0x17, 0x02, 0xb4, 0x09, 0xc2, 0x40, 0x99,
+ 0x0e, 0x48, 0x42, 0x98, 0x42, 0x70, 0x8e, 0x49,
+ 0xfe, 0xf1, 0x02, 0xb0, 0x80, 0xff, 0xc0, 0xd4,
+ 0xe4, 0x40, 0x20, 0xd4, 0xb0, 0x49, 0x04, 0xf0,
+ 0x30, 0x18, 0x06, 0xc1, 0xef, 0xef, 0xfa, 0xc7,
+ 0x02, 0xc0, 0x00, 0xb8, 0x38, 0x12, 0xe4, 0x4b,
+ 0x02, 0xc3, 0x00, 0xbb, 0x00, 0x00, 0x02, 0xc5,
+ 0x00, 0xbd, 0x00, 0x00, 0x02, 0xc1, 0x00, 0xb9,
+ 0x00, 0x00, 0x02, 0xc1, 0x00, 0xb9, 0x00, 0x00 };
+
+static u16 r8153_usb_patch_d_bp[] = {
+ 0xfc26, 0xa000, 0xfc28, 0x0000, 0xfc2a, 0x0000, 0xfc2c, 0x1792,
+ 0xfc2e, 0x1236, 0xfc30, 0x0000, 0xfc32, 0x0000, 0xfc34, 0x0000,
+ 0xfc36, 0x0000, 0xfc38, 0x000c };
+
+static void rtl_clear_bp(struct r8152 *tp)
+{
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
+
+ mdelay(6);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
+}
+
+static void r8153_clear_bp(struct r8152 *tp)
+{
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
+ rtl_clear_bp(tp);
+}
+
+static void r8152b_set_dq_desc(struct r8152 *tp)
+{
+ u8 data;
+
+ data = ocp_read_byte(tp, MCU_TYPE_USB, 0xd429);
+ data |= 0x80;
+ ocp_write_byte(tp, MCU_TYPE_USB, 0xd429, data);
+ ocp_write_word(tp, MCU_TYPE_USB, 0xc0ce, 0x0210);
+ data = ocp_read_byte(tp, MCU_TYPE_USB, 0xd429);
+ data &= ~0x80;
+ ocp_write_byte(tp, MCU_TYPE_USB, 0xd429, data);
+}
+
+static int r8153_pre_ram_code(struct r8152 *tp, u16 patch_key)
+{
+ u16 data;
+ int i;
+
+ data = ocp_reg_read(tp, 0xb820);
+ data |= 0x0010;
+ ocp_reg_write(tp, 0xb820, data);
+
+ for (i = 0, data = 0; !data && i < 5000; i++) {
+ mdelay(2);
+ data = ocp_reg_read(tp, 0xb800) & 0x0040;
+ }
+
+ sram_write(tp, 0x8146, patch_key);
+ sram_write(tp, 0xb82e, 0x0001);
+
+ return -EBUSY;
+}
+
+static int r8153_post_ram_code(struct r8152 *tp)
+{
+ u16 data;
+
+ sram_write(tp, 0x0000, 0x0000);
+
+ data = ocp_reg_read(tp, 0xb82e);
+ data &= ~0x0001;
+ ocp_reg_write(tp, 0xb82e, data);
+
+ sram_write(tp, 0x8146, 0x0000);
+
+ data = ocp_reg_read(tp, 0xb820);
+ data &= ~0x0010;
+ ocp_reg_write(tp, 0xb820, data);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
+
+ return 0;
+}
+
+static void r8153_wdt1_end(struct r8152 *tp)
+{
+ int i;
+
+ for (i = 0; i < 104; i++) {
+ if (!(ocp_read_byte(tp, MCU_TYPE_USB, 0xe404) & 1))
+ break;
+ mdelay(2);
+ }
+}
+
+void r8152b_firmware(struct r8152 *tp)
+{
+ int i;
+
+ if (tp->version == RTL_VER_01) {
+ int i;
+
+ r8152b_set_dq_desc(tp);
+ rtl_clear_bp(tp);
+
+ generic_ocp_write(tp, 0xf800, 0x3f,
+ sizeof(r8152b_pla_patch_a),
+ r8152b_pla_patch_a, MCU_TYPE_PLA);
+
+ for (i = 0; i < ARRAY_SIZE(r8152b_pla_patch_a_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8152b_pla_patch_a_bp[i],
+ r8152b_pla_patch_a_bp[i+1]);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xb092, 0x7070);
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xb098, 0x0600);
+ for (i = 0; i < ARRAY_SIZE(r8152b_ram_code1); i++)
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xb09a,
+ r8152b_ram_code1[i]);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xb098, 0x0200);
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xb092, 0x7030);
+ } else if (tp->version == RTL_VER_02) {
+ rtl_clear_bp(tp);
+
+ generic_ocp_write(tp, 0xf800, 0xff,
+ sizeof(r8152b_pla_patch_a2),
+ r8152b_pla_patch_a2, MCU_TYPE_PLA);
+
+ for (i = 0; i < ARRAY_SIZE(r8152b_pla_patch_a2_bp);
+ i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8152b_pla_patch_a2_bp[i],
+ r8152b_pla_patch_a2_bp[i+1]);
+ }
+}
+
+void r8153_firmware(struct r8152 *tp)
+{
+ int i;
+
+ if (tp->version == RTL_VER_03) {
+ r8153_clear_bp(tp);
+
+ r8153_pre_ram_code(tp, 0x7000);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_ram_code_a); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_ram_code_a[i],
+ r8153_ram_code_a[i+1]);
+
+ r8153_post_ram_code(tp);
+ } else if (tp->version == RTL_VER_04) {
+ r8153_pre_ram_code(tp, 0x7001);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_ram_code_bc[i],
+ r8153_ram_code_bc[i+1]);
+
+ r8153_post_ram_code(tp);
+
+ r8153_wdt1_end(tp);
+ r8153_clear_bp(tp);
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000);
+ generic_ocp_write(tp, 0xf800, 0xff,
+ sizeof(r8153_usb_patch_b),
+ r8153_usb_patch_b, MCU_TYPE_USB);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_b_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_USB,
+ r8153_usb_patch_b_bp[i],
+ r8153_usb_patch_b_bp[i+1]);
+
+ if (!(ocp_read_word(tp, MCU_TYPE_PLA, 0xd38e) & BIT(0))) {
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xd38c, 0x0082);
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xd38e, 0x0082);
+ }
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, 0x0000);
+ generic_ocp_write(tp, 0xf800, 0xff,
+ sizeof(r8153_pla_patch_b),
+ r8153_pla_patch_b, MCU_TYPE_PLA);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_pla_patch_b_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_pla_patch_b_bp[i],
+ r8153_pla_patch_b_bp[i+1]);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xd388, 0x08ca);
+ } else if (tp->version == RTL_VER_05) {
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcfca);
+ ocp_data &= ~0x4000;
+ ocp_write_word(tp, MCU_TYPE_USB, 0xcfca, ocp_data);
+
+ r8153_pre_ram_code(tp, 0x7001);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_ram_code_bc[i],
+ r8153_ram_code_bc[i+1]);
+
+ r8153_post_ram_code(tp);
+
+ r8153_wdt1_end(tp);
+ r8153_clear_bp(tp);
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000);
+ generic_ocp_write(tp, 0xf800, 0xff,
+ sizeof(r8153_usb_patch_c),
+ r8153_usb_patch_c, MCU_TYPE_USB);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_c_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_USB,
+ r8153_usb_patch_c_bp[i],
+ r8153_usb_patch_c_bp[i+1]);
+
+ if (ocp_read_byte(tp, MCU_TYPE_USB, 0xcfef) & 1) {
+ ocp_write_word(tp, MCU_TYPE_USB, 0xfc30, 0x1578);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x00ff);
+ } else {
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x00ef);
+ }
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, 0x0000);
+ generic_ocp_write(tp, 0xf800, 0xff,
+ sizeof(r8153_pla_patch_c),
+ r8153_pla_patch_c, MCU_TYPE_PLA);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_pla_patch_c_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_pla_patch_c_bp[i],
+ r8153_pla_patch_c_bp[i+1]);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xd388, 0x08ca);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcfca);
+ ocp_data |= 0x4000;
+ ocp_write_word(tp, MCU_TYPE_USB, 0xcfca, ocp_data);
+ } else if (tp->version == RTL_VER_06) {
+ r8153_pre_ram_code(tp, 0x7002);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_ram_code_d); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_ram_code_d[i],
+ r8153_ram_code_d[i+1]);
+
+ r8153_post_ram_code(tp);
+
+ r8153_clear_bp(tp);
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000);
+ generic_ocp_write(tp, 0xf800, 0xff, sizeof(usb_patch_d),
+ usb_patch_d, MCU_TYPE_USB);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_d_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_USB,
+ r8153_usb_patch_d_bp[i],
+ r8153_usb_patch_d_bp[i+1]);
+ }
+}
diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c
index 62d20f0..b9c9a84 100644
--- a/drivers/usb/eth/usb_ether.c
+++ b/drivers/usb/eth/usb_ether.c
@@ -180,6 +180,13 @@
.get_info = smsc95xx_eth_get_info,
},
#endif
+#ifdef CONFIG_USB_ETHER_RTL8152
+ {
+ .before_probe = r8152_eth_before_probe,
+ .probe = r8152_eth_probe,
+ .get_info = r8152_eth_get_info,
+ },
+#endif
{ }, /* END */
};
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 5ef6deb..c6727c3 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -13,6 +13,7 @@
#include <memalign.h>
#include <phys2bus.h>
#include <usbroothubdes.h>
+#include <wait_bit.h>
#include <asm/io.h>
#include "dwc2.h"
@@ -34,7 +35,8 @@
uint8_t *aligned_buffer;
uint8_t *status_buffer;
#endif
- int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+ u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+ u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
struct dwc2_core_regs *regs;
int root_hub_devnum;
};
@@ -52,27 +54,6 @@
/*
* DWC2 IP interface
*/
-static int wait_for_bit(void *reg, const uint32_t mask, bool set)
-{
- unsigned int timeout = 1000000;
- uint32_t val;
-
- while (--timeout) {
- val = readl(reg);
- if (!set)
- val = ~val;
-
- if ((val & mask) == mask)
- return 0;
-
- udelay(1);
- }
-
- debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
- __func__, reg, mask, set);
-
- return -ETIMEDOUT;
-}
/*
* Initializes the FSLSPClkSel field of the HCFG register
@@ -117,7 +98,8 @@
writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
®s->grstctl);
- ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
+ ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
+ false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
@@ -135,7 +117,8 @@
int ret;
writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
- ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
+ ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
+ false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
@@ -152,13 +135,15 @@
int ret;
/* Wait for AHB master IDLE state. */
- ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
+ ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
+ true, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
/* Core Soft Reset */
writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
- ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
+ ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_CSFTRST,
+ false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
@@ -243,8 +228,8 @@
clrsetbits_le32(®s->hc_regs[i].hcchar,
DWC2_HCCHAR_EPDIR,
DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
- ret = wait_for_bit(®s->hc_regs[i].hcchar,
- DWC2_HCCHAR_CHEN, 0);
+ ret = wait_for_bit(__func__, ®s->hc_regs[i].hcchar,
+ DWC2_HCCHAR_CHEN, false, 1000, false);
if (ret)
printf("%s: Timeout!\n", __func__);
}
@@ -426,19 +411,29 @@
if (dev->speed == USB_SPEED_LOW)
hcchar |= DWC2_HCCHAR_LSPDDEV;
- /* Clear old interrupt conditions for this host channel. */
- writel(0x3fff, &hc_regs->hcint);
-
/*
* Program the HCCHARn register with the endpoint characteristics
* for the current transfer.
*/
writel(hcchar, &hc_regs->hcchar);
- /* Program the HCSPLIT register for SPLITs */
+ /* Program the HCSPLIT register, default to no SPLIT */
writel(0, &hc_regs->hcsplt);
}
+static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
+ uint8_t hub_devnum, uint8_t hub_port)
+{
+ uint32_t hcsplt = 0;
+
+ hcsplt = DWC2_HCSPLT_SPLTENA;
+ hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
+ hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
+
+ /* Program the HCSPLIT register for SPLITs */
+ writel(hcsplt, &hc_regs->hcsplt);
+}
+
/*
* DWC2 to USB API interface
*/
@@ -729,38 +724,33 @@
return stat;
}
-int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle,
- bool ignore_ack)
+int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
{
- uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
- struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
int ret;
uint32_t hcint, hctsiz;
- ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
+ ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
+ 1000, false);
if (ret)
return ret;
hcint = readl(&hc_regs->hcint);
- if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
- return -EAGAIN;
- if (ignore_ack)
- hcint &= ~DWC2_HCINT_ACK;
- else
- hcint_comp_hlt_ack |= DWC2_HCINT_ACK;
- if (hcint != hcint_comp_hlt_ack) {
- debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
- return -EINVAL;
- }
-
hctsiz = readl(&hc_regs->hctsiz);
*sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
DWC2_HCTSIZ_XFERSIZE_OFFSET;
*toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
- debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
+ debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
+ *toggle);
- return 0;
+ if (hcint & DWC2_HCINT_XFERCOMP)
+ return 0;
+
+ if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
+ return -EAGAIN;
+
+ debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
+ return -EINVAL;
}
static int dwc2_eptype[] = {
@@ -770,96 +760,176 @@
DWC2_HCCHAR_EPTYPE_BULK,
};
+static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
+ u8 *pid, int in, void *buffer, int num_packets,
+ int xfer_len, int *actual_len, int odd_frame)
+{
+ int ret = 0;
+ uint32_t sub;
+
+ debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
+ *pid, xfer_len, num_packets);
+
+ writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
+ (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+ (*pid << DWC2_HCTSIZ_PID_OFFSET),
+ &hc_regs->hctsiz);
+
+ if (!in && xfer_len) {
+ memcpy(aligned_buffer, buffer, xfer_len);
+
+ flush_dcache_range((unsigned long)aligned_buffer,
+ (unsigned long)aligned_buffer +
+ roundup(xfer_len, ARCH_DMA_MINALIGN));
+ }
+
+ writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
+
+ /* Clear old interrupt conditions for this host channel. */
+ writel(0x3fff, &hc_regs->hcint);
+
+ /* Set host channel enable after all other setup is complete. */
+ clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+ DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
+ DWC2_HCCHAR_ODDFRM,
+ (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
+ (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
+ DWC2_HCCHAR_CHEN);
+
+ ret = wait_for_chhltd(hc_regs, &sub, pid);
+ if (ret < 0)
+ return ret;
+
+ if (in) {
+ xfer_len -= sub;
+
+ invalidate_dcache_range((unsigned long)aligned_buffer,
+ (unsigned long)aligned_buffer +
+ roundup(xfer_len, ARCH_DMA_MINALIGN));
+
+ memcpy(buffer, aligned_buffer, xfer_len);
+ }
+ *actual_len = xfer_len;
+
+ return ret;
+}
+
int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
- unsigned long pipe, int *pid, int in, void *buffer, int len,
- bool ignore_ack)
+ unsigned long pipe, u8 *pid, int in, void *buffer, int len)
{
struct dwc2_core_regs *regs = priv->regs;
struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
+ struct dwc2_host_regs *host_regs = ®s->host_regs;
int devnum = usb_pipedevice(pipe);
int ep = usb_pipeendpoint(pipe);
int max = usb_maxpacket(dev, pipe);
int eptype = dwc2_eptype[usb_pipetype(pipe)];
int done = 0;
int ret = 0;
- uint32_t sub;
+ int do_split = 0;
+ int complete_split = 0;
uint32_t xfer_len;
uint32_t num_packets;
int stop_transfer = 0;
+ uint32_t max_xfer_len;
+ int ssplit_frame_num = 0;
debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
in, len);
- do {
- /* Initialize channel */
- dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
- eptype, max);
+ max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
+ if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
+ max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
+ if (max_xfer_len > DWC2_DATA_BUF_SIZE)
+ max_xfer_len = DWC2_DATA_BUF_SIZE;
- xfer_len = len - done;
- if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
- xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
- if (xfer_len > DWC2_DATA_BUF_SIZE)
- xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
+ /* Make sure that max_xfer_len is a multiple of max packet size. */
+ num_packets = max_xfer_len / max;
+ max_xfer_len = num_packets * max;
- /* Make sure that xfer_len is a multiple of max packet size. */
- if (xfer_len > 0) {
- num_packets = (xfer_len + max - 1) / max;
- if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
- num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
- xfer_len = num_packets * max;
- }
- } else {
+ /* Initialize channel */
+ dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
+ eptype, max);
+
+ /* Check if the target is a FS/LS device behind a HS hub */
+ if (dev->speed != USB_SPEED_HIGH) {
+ uint8_t hub_addr;
+ uint8_t hub_port;
+ uint32_t hprt0 = readl(®s->hprt0);
+ if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
+ DWC2_HPRT0_PRTSPD_HIGH) {
+ usb_find_usb2_hub_address_port(dev, &hub_addr,
+ &hub_port);
+ dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
+
+ do_split = 1;
num_packets = 1;
+ max_xfer_len = max;
+ }
+ }
+
+ do {
+ int actual_len = 0;
+ uint32_t hcint;
+ int odd_frame = 0;
+ xfer_len = len - done;
+
+ if (xfer_len > max_xfer_len)
+ xfer_len = max_xfer_len;
+ else if (xfer_len > max)
+ num_packets = (xfer_len + max - 1) / max;
+ else
+ num_packets = 1;
+
+ if (complete_split)
+ setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
+ else if (do_split)
+ clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
+
+ if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
+ int uframe_num = readl(&host_regs->hfnum);
+ if (!(uframe_num & 0x1))
+ odd_frame = 1;
}
- if (in)
- xfer_len = num_packets * max;
+ ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
+ in, (char *)buffer + done, num_packets,
+ xfer_len, &actual_len, odd_frame);
- debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
- *pid, xfer_len, num_packets);
-
- writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
- (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
- (*pid << DWC2_HCTSIZ_PID_OFFSET),
- &hc_regs->hctsiz);
-
- if (!in && xfer_len) {
- memcpy(priv->aligned_buffer, (char *)buffer + done,
- xfer_len);
-
- flush_dcache_range((unsigned long)priv->aligned_buffer,
- (unsigned long)((void *)priv->aligned_buffer +
- roundup(xfer_len, ARCH_DMA_MINALIGN)));
+ hcint = readl(&hc_regs->hcint);
+ if (complete_split) {
+ stop_transfer = 0;
+ if (hcint & DWC2_HCINT_NYET) {
+ ret = 0;
+ int frame_num = DWC2_HFNUM_MAX_FRNUM &
+ readl(&host_regs->hfnum);
+ if (((frame_num - ssplit_frame_num) &
+ DWC2_HFNUM_MAX_FRNUM) > 4)
+ ret = -EAGAIN;
+ } else
+ complete_split = 0;
+ } else if (do_split) {
+ if (hcint & DWC2_HCINT_ACK) {
+ ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
+ readl(&host_regs->hfnum);
+ ret = 0;
+ complete_split = 1;
+ }
}
- writel(phys_to_bus((unsigned long)priv->aligned_buffer),
- &hc_regs->hcdma);
-
- /* Set host channel enable after all other setup is complete. */
- clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
- DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
- (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
- DWC2_HCCHAR_CHEN);
-
- ret = wait_for_chhltd(regs, &sub, pid, ignore_ack);
if (ret)
break;
- if (in) {
- xfer_len -= sub;
+ if (actual_len < xfer_len)
+ stop_transfer = 1;
- invalidate_dcache_range((unsigned long)priv->aligned_buffer,
- (unsigned long)((void *)priv->aligned_buffer +
- roundup(xfer_len, ARCH_DMA_MINALIGN)));
+ done += actual_len;
- memcpy(buffer + done, priv->aligned_buffer, xfer_len);
- if (sub)
- stop_transfer = 1;
- }
-
- done += xfer_len;
-
- } while ((done < len) && !stop_transfer);
+ /* Transactions are done when when either all data is transferred or
+ * there is a short transfer. In case of a SPLIT make sure the CSPLIT
+ * is executed.
+ */
+ } while (((done < len) && !stop_transfer) || complete_split);
writel(0, &hc_regs->hcintmsk);
writel(0xFFFFFFFF, &hc_regs->hcint);
@@ -876,14 +946,19 @@
{
int devnum = usb_pipedevice(pipe);
int ep = usb_pipeendpoint(pipe);
+ u8* pid;
- if (devnum == priv->root_hub_devnum) {
+ if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
dev->status = 0;
return -EINVAL;
}
- return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep],
- usb_pipein(pipe), buffer, len, true);
+ if (usb_pipein(pipe))
+ pid = &priv->in_data_toggle[devnum][ep];
+ else
+ pid = &priv->out_data_toggle[devnum][ep];
+
+ return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
}
static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
@@ -891,7 +966,8 @@
struct devrequest *setup)
{
int devnum = usb_pipedevice(pipe);
- int pid, ret, act_len;
+ int ret, act_len;
+ u8 pid;
/* For CONTROL endpoint pid should start with DATA1 */
int status_direction;
@@ -902,31 +978,39 @@
setup);
}
+ /* SETUP stage */
pid = DWC2_HC_PID_SETUP;
- ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8, true);
+ do {
+ ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
+ } while (ret == -EAGAIN);
if (ret)
return ret;
+ /* DATA stage */
+ act_len = 0;
if (buffer) {
pid = DWC2_HC_PID_DATA1;
- ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), buffer,
- len, false);
+ do {
+ ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
+ buffer, len);
+ act_len += dev->act_len;
+ buffer += dev->act_len;
+ len -= dev->act_len;
+ } while (ret == -EAGAIN);
if (ret)
return ret;
- act_len = dev->act_len;
- } /* End of DATA stage */
- else
- act_len = 0;
+ status_direction = usb_pipeout(pipe);
+ } else {
+ /* No-data CONTROL always ends with an IN transaction */
+ status_direction = 1;
+ }
/* STATUS stage */
- if ((len == 0) || usb_pipeout(pipe))
- status_direction = 1;
- else
- status_direction = 0;
-
pid = DWC2_HC_PID_DATA1;
- ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
- priv->status_buffer, 0, false);
+ do {
+ ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
+ priv->status_buffer, 0);
+ } while (ret == -EAGAIN);
if (ret)
return ret;
@@ -983,8 +1067,10 @@
DWC2_HPRT0_PRTRST);
for (i = 0; i < MAX_DEVICE; i++) {
- for (j = 0; j < MAX_ENDPOINT; j++)
- priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+ for (j = 0; j < MAX_ENDPOINT; j++) {
+ priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+ priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+ }
}
return 0;
diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h
index f69372e..594757b 100644
--- a/drivers/usb/host/dwc2.h
+++ b/drivers/usb/host/dwc2.h
@@ -500,6 +500,7 @@
#define DWC2_HFNUM_FRNUM_OFFSET 0
#define DWC2_HFNUM_FRREM_MASK (0xFFFF << 16)
#define DWC2_HFNUM_FRREM_OFFSET 16
+#define DWC2_HFNUM_MAX_FRNUM 0x3FFF
#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK (0xFFFF << 0)
#define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET 0
#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK (0xFF << 16)
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index 1292caa..84114c5 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include "ehci.h"
@@ -21,6 +22,19 @@
{
struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
struct ehci_hcor *hcor;
+ int i;
+
+ for (i = 0; ; i++) {
+ struct udevice *clk_dev;
+ int clk_id;
+
+ clk_id = clk_get_by_index(dev, i, &clk_dev);
+ if (clk_id < 0)
+ break;
+ if (clk_enable(clk_dev, clk_id))
+ printf("failed to enable clock (dev=%s, id=%d)\n",
+ clk_dev->name, clk_id);
+ }
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 2666351..e1c67f7 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <usb.h>
#include <errno.h>
+#include <wait_bit.h>
#include <linux/compiler.h>
#include <usb/ehci-fsl.h>
#include <asm/io.h>
@@ -117,32 +118,6 @@
pll_480_ctrl_set);
}
-static int wait_for_bit(u32 *reg, const u32 mask, bool set)
-{
- u32 val;
- const unsigned int timeout = 10000;
- unsigned long start = get_timer(0);
-
- while(1) {
- val = readl(reg);
- if (!set)
- val = ~val;
-
- if ((val & mask) == mask)
- return 0;
-
- if (get_timer(start) > timeout)
- break;
-
- udelay(1);
- }
-
- debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
- __func__, reg, mask, set);
-
- return -ETIMEDOUT;
-}
-
/* Return 0 : host node, <>0 : device mode */
static int usb_phy_enable(int index, struct usb_ehci *ehci)
{
@@ -160,12 +135,13 @@
/* Stop then Reset */
clrbits_le32(usb_cmd, UCMD_RUN_STOP);
- ret = wait_for_bit(usb_cmd, UCMD_RUN_STOP, 0);
+ ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000,
+ false);
if (ret)
return ret;
setbits_le32(usb_cmd, UCMD_RESET);
- ret = wait_for_bit(usb_cmd, UCMD_RESET, 0);
+ ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false);
if (ret)
return ret;
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index cda1c6d..f21a1fa 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -137,11 +137,17 @@
return 0;
}
+static const struct udevice_id ehci_pci_ids[] = {
+ { .compatible = "ehci-pci" },
+ { }
+};
+
U_BOOT_DRIVER(ehci_pci) = {
.name = "ehci_pci",
.id = UCLASS_USB,
.probe = ehci_pci_probe,
.remove = ehci_pci_remove,
+ .of_match = ehci_pci_ids,
.ops = &ehci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
.priv_auto_alloc_size = sizeof(struct ehci_pci_priv),
diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index 48d338e..9245126 100644
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <errno.h>
+#include <wait_bit.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clk.h>
@@ -80,30 +81,6 @@
static struct otg_regs *otg = (struct otg_regs *)USB_BASE;
static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE;
-static int wait_for_bit(void *reg, const u32 mask, bool set)
-{
- u32 val;
- unsigned long start = get_timer(0);
-
- while (1) {
- val = readl(reg);
- if (!set)
- val = ~val;
-
- if ((val & mask) == mask)
- return 0;
-
- if (get_timer(start) > CONFIG_SYS_HZ)
- break;
-
- udelay(1);
- }
-
- error("Timeout (reg=%p mask=%08x wait_set=%i)\n", reg, mask, set);
-
- return -ETIMEDOUT;
-}
-
static int isp1301_set_value(int reg, u8 value)
{
return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1);
@@ -158,7 +135,8 @@
setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01));
setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP);
- ret = wait_for_bit(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS, 1);
+ ret = wait_for_bit(__func__, &clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS,
+ true, CONFIG_SYS_HZ, false);
if (ret)
return ret;
@@ -183,7 +161,8 @@
/* enable I2C clock */
writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl);
- ret = wait_for_bit(&otg->otg_clk_sts, OTG_CLK_I2C_EN, 1);
+ ret = wait_for_bit(__func__, &otg->otg_clk_sts, OTG_CLK_I2C_EN, true,
+ CONFIG_SYS_HZ, false);
if (ret)
return ret;
@@ -203,7 +182,8 @@
OTG_CLK_I2C_EN | OTG_CLK_HOST_EN;
writel(mask, &otg->otg_clk_ctrl);
- ret = wait_for_bit(&otg->otg_clk_sts, mask, 1);
+ ret = wait_for_bit(__func__, &otg->otg_clk_sts, mask, true,
+ CONFIG_SYS_HZ, false);
if (ret)
return ret;
diff --git a/dts/Makefile b/dts/Makefile
index dbde703..c4ac153 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -45,4 +45,4 @@
clean-files := dt.dtb.S
# Let clean descend into dts directories
-subdir- += ../arch/*/dts
+subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts
diff --git a/fs/ubifs/replay.c b/fs/ubifs/replay.c
index d0fcd83..176125e 100644
--- a/fs/ubifs/replay.c
+++ b/fs/ubifs/replay.c
@@ -26,6 +26,7 @@
#include <linux/err.h>
#endif
#include "ubifs.h"
+#include <linux/bug.h>
#include <linux/list_sort.h>
/**
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index abe861a..dcf3a47 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -31,6 +31,7 @@
#include <common.h>
#include <malloc.h>
#include <memalign.h>
+#include <linux/bug.h>
#include <linux/log2.h>
#include <linux/stat.h>
#include <linux/err.h>
diff --git a/include/bios_emul.h b/include/bios_emul.h
index 80979ed..7571263 100644
--- a/include/bios_emul.h
+++ b/include/bios_emul.h
@@ -31,7 +31,11 @@
int bus;
u32 VendorID;
u32 DeviceID;
+#ifdef CONFIG_DM_PCI
+ struct udevice *pcidev;
+#else
pci_dev_t pcidev;
+#endif
void *BIOSImage;
u32 BIOSImageLen;
u8 LowMem[1536];
@@ -39,7 +43,12 @@
struct vbe_mode_info;
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp);
+#ifdef CONFIG_DM_PCI
+int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
+ int clean_up);
+#else
+int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up);
+#endif
/* Run a BIOS ROM natively (only supported on x86 machines) */
void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
@@ -57,10 +66,18 @@
void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void));
+#ifdef CONFIG_DM_PCI
+int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **pVGAInfo);
+
+int biosemu_run(struct udevice *dev, uchar *bios_rom, int bios_len,
+ BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+ struct vbe_mode_info *mode_info);
+#else
int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo);
int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
struct vbe_mode_info *mode_info);
+#endif
#endif
diff --git a/include/common.h b/include/common.h
index 7bed0cc..1563d64 100644
--- a/include/common.h
+++ b/include/common.h
@@ -146,9 +146,6 @@
#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
#endif /* BUG */
-/* Force a compilation error if condition is true */
-#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
-
typedef void (interrupt_handler_t)(void *);
#include <asm/u-boot.h> /* boot information for Linux kernel */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 73279c8..4a17f41 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -606,6 +606,16 @@
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_IR36021_READ
+/* The lowest and highest voltage allowed for T4240RDB */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
/*
* eSPI - Enhanced SPI
*/
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 43ce7fe..68d3fd7 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -34,6 +34,7 @@
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
/* NAND support */
#if defined(CONFIG_SPL_NAND_SUPPORT)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 174ea08..179b4f9 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -25,6 +25,8 @@
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_BOOTM_LEN 0x1000000
+
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index c946176..4374c3a 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -156,7 +156,7 @@
/* Miscellaneous configurable options */
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
@@ -203,6 +203,7 @@
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SPI_FLASH_STMICRO
#define FSL_QSPI_FLASH_NUM 1
#define FSL_QSPI_FLASH_SIZE SZ_32M
#endif
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index d507fb4..fac7c3f 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -23,6 +23,8 @@
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_BOOTM_LEN 0x1000000
+
/* Enable iomux-lpsr support */
#define CONFIG_IOMUX_LPSR
#define CONFIG_IMX_FIXED_IVT_OFFSET
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 22e515c..d23e4f3 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -179,8 +179,33 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
+
+/*
+ * If want to use nand, define CONFIG_NAND_MXS and rework board
+ * to support nand, since emmc has pin conflicts with nand
+ */
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+#else
#define CONFIG_SYS_FSL_USDHC_NUM 2
+#endif
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 5da6cfd..5e33845 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -19,8 +19,6 @@
#include <configs/ti_omap3_common.h>
#include <asm/mach-types.h>
-#undef CONFIG_BOOTDELAY
-
/*
* Display CPU and Board information
*/
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 7b60f29..e9ce3f6 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -50,6 +50,9 @@
* Hardware drivers
*/
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
+
/*
* select serial console configuration
*/
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index 4258dcb..b0d2ffe 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -14,7 +14,6 @@
#include <configs/x86-common.h>
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-#define CONFIG_ARCH_MISC_INIT
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_PCI_PNP
diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
index 1b83eb3..927bae7 100644
--- a/include/configs/rpi-common.h
+++ b/include/configs/rpi-common.h
@@ -88,6 +88,9 @@
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_MISC_INIT_R
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_SYS_STDIO_DEREGISTER
#endif
/* Console UART */
@@ -111,6 +114,7 @@
#define CONFIG_SYS_LOAD_ADDR 0x1000000
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_PREBOOT "usb start"
/* Shell */
#define CONFIG_SYS_MAXARGS 8
@@ -133,7 +137,7 @@
/* Environment */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define ENV_DEVICE_SETTINGS \
- "stdin=serial,lcd\0" \
+ "stdin=serial,usbkbd\0" \
"stdout=serial,lcd\0" \
"stderr=serial,lcd\0"
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 8391e38..73cd3ac 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -29,6 +29,7 @@
UCLASS_CLK, /* Clock source, e.g. used by peripherals */
UCLASS_CPU, /* CPU, typically part of an SoC */
UCLASS_CROS_EC, /* Chrome OS EC */
+ UCLASS_DISK, /* Disk controller, e.g. SATA */
UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
UCLASS_RAM, /* RAM controller */
UCLASS_ETH, /* Ethernet device */
@@ -37,6 +38,7 @@
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
UCLASS_I2C_GENERIC, /* Generic I2C device */
UCLASS_I2C_MUX, /* I2C multiplexer */
+ UCLASS_IRQ, /* Interrupt controller */
UCLASS_KEYBOARD, /* Keyboard input device */
UCLASS_LED, /* Light-emitting diode (LED) */
UCLASS_LPC, /* x86 'low pin count' interface */
@@ -45,6 +47,7 @@
UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
UCLASS_MTD, /* Memory Technology Device (MTD) device */
+ UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */
UCLASS_PANEL, /* Display panel, such as an LCD */
UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */
UCLASS_PCH, /* x86 platform controller hub */
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 25e98c9..dd82916 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -163,7 +163,6 @@
COMPAT_INTEL_X86_PINCTRL, /* Intel ICH7/9 pin control */
COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */
COMPAT_INTEL_PCH, /* Intel PCH */
- COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */
COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */
diff --git a/include/linux/bug.h b/include/linux/bug.h
new file mode 100644
index 0000000..920e379
--- /dev/null
+++ b/include/linux/bug.h
@@ -0,0 +1,55 @@
+#ifndef _LINUX_BUG_H
+#define _LINUX_BUG_H
+
+#include <linux/compiler.h>
+
+#ifdef __CHECKER__
+#define BUILD_BUG_ON_NOT_POWER_OF_2(n) (0)
+#define BUILD_BUG_ON_ZERO(e) (0)
+#define BUILD_BUG_ON_NULL(e) ((void*)0)
+#define BUILD_BUG_ON_INVALID(e) (0)
+#define BUILD_BUG_ON(condition) (0)
+#define BUILD_BUG() (0)
+#else /* __CHECKER__ */
+
+/* Force a compilation error if a constant expression is not a power of 2 */
+#define BUILD_BUG_ON_NOT_POWER_OF_2(n) \
+ BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0))
+
+/* Force a compilation error if condition is true, but also produce a
+ result (of value 0 and type size_t), so the expression can be used
+ e.g. in a structure initializer (or where-ever else comma expressions
+ aren't permitted). */
+#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:-!!(e); }))
+#define BUILD_BUG_ON_NULL(e) ((void *)sizeof(struct { int:-!!(e); }))
+
+/*
+ * BUILD_BUG_ON_INVALID() permits the compiler to check the validity of the
+ * expression but avoids the generation of any code, even if that expression
+ * has side-effects.
+ */
+#define BUILD_BUG_ON_INVALID(e) ((void)(sizeof((__force long)(e))))
+
+/**
+ * BUILD_BUG_ON - break compile if a condition is true.
+ * @condition: the condition which the compiler should know is false.
+ *
+ * If you have some code which relies on certain constants being equal, or
+ * some other compile-time-evaluated condition, you should use BUILD_BUG_ON to
+ * detect if someone changes it.
+ *
+ * The implementation uses gcc's reluctance to create a negative array, but gcc
+ * (as of 4.4) only emits that error for obvious cases (e.g. not arguments to
+ * inline functions). Luckily, in 4.3 they added the "error" function
+ * attribute just for this type of case. Thus, we use a negative sized array
+ * (should always create an error on gcc versions older than 4.4) and then call
+ * an undefined function with the error attribute (should always create an
+ * error on gcc 4.3 and later). If for some reason, neither creates a
+ * compile-time error, we'll still have a link-time error, which is harder to
+ * track down.
+ */
+#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+
+#endif /* __CHECKER__ */
+
+#endif /* _LINUX_BUG_H */
diff --git a/include/part.h b/include/part.h
index 4d00e22..dc23949 100644
--- a/include/part.h
+++ b/include/part.h
@@ -10,8 +10,6 @@
#include <ide.h>
#include <common.h>
-typedef struct block_dev_desc block_dev_desc_t;
-
struct block_dev_desc {
int if_type; /* type of the interface */
int dev; /* device number */
diff --git a/include/pch.h b/include/pch.h
new file mode 100644
index 0000000..79f49bd
--- /dev/null
+++ b/include/pch.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __pch_h
+#define __pch_h
+
+enum pch_version {
+ PCHV_UNKNOWN,
+ PCHV_7,
+ PCHV_9,
+};
+
+#define PCH_RCBA 0xf0
+
+#define BIOS_CTRL_BIOSWE BIT(0)
+
+/* Operations for the Platform Controller Hub */
+struct pch_ops {
+ /**
+ * get_sbase() - get the address of SPI base
+ *
+ * @dev: PCH device to check
+ * @sbasep: Returns address of SPI base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no SPI base)
+ */
+ int (*get_sbase)(struct udevice *dev, ulong *sbasep);
+
+ /**
+ * get_version() - get the PCH version
+ *
+ * @return version, or -ENOSYS if unknown
+ */
+ enum pch_version (*get_version)(struct udevice *dev);
+
+ /**
+ * set_spi_protect() - set whether SPI flash is protected or not
+ *
+ * @dev: PCH device to adjust
+ * @protect: true to protect, false to unprotect
+ *
+ * @return 0 on success, -ENOSYS if not implemented
+ */
+ int (*set_spi_protect)(struct udevice *dev, bool protect);
+};
+
+#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
+
+/**
+ * pch_get_sbase() - get the address of SPI base
+ *
+ * @dev: PCH device to check
+ * @sbasep: Returns address of SPI base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no SPI base)
+ */
+int pch_get_sbase(struct udevice *dev, ulong *sbasep);
+
+/**
+ * pch_get_version() - get the PCH version
+ *
+ * @return version, or -ENOSYS if unknown
+ */
+enum pch_version pch_get_version(struct udevice *dev);
+
+/**
+ * set_spi_protect() - set whether SPI flash is protected or not
+ *
+ * @dev: PCH device to adjust
+ * @protect: true to protect, false to unprotect
+ *
+ * @return 0 on success, -ENOSYS if not implemented
+ */
+int pch_set_spi_protect(struct udevice *dev, bool protect);
+
+#endif
diff --git a/include/pci.h b/include/pci.h
index cb2562f..d0d152c 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -757,7 +757,9 @@
/**
* pci_write_bar32() - Write the address of a BAR including control bits
*
- * This writes a raw address (with control bits) to a bar
+ * This writes a raw address (with control bits) to a bar. This can be used
+ * with devices which require hard-coded addresses, not part of the normal
+ * PCI enumeration process.
*
* @hose: PCI hose to use
* @dev: PCI device to update
@@ -765,7 +767,7 @@
* @addr: BAR address with control bits
*/
void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
- u32 addr_and_ctrl);
+ u32 addr);
/**
* pci_read_bar32() - read the address of a bar
@@ -1167,6 +1169,17 @@
struct pci_region **memp, struct pci_region **prefp);
/**
+ * dm_pci_write_bar32() - Write the address of a BAR
+ *
+ * This writes a raw address to a bar
+ *
+ * @dev: PCI device to update
+ * @barnum: BAR number (0-5)
+ * @addr: BAR address
+ */
+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
+
+/**
* dm_pci_read_bar32() - read a base address register from a device
*
* @dev: Device to check
diff --git a/include/syscon.h b/include/syscon.h
index c62ccd6..4593b6e 100644
--- a/include/syscon.h
+++ b/include/syscon.h
@@ -37,6 +37,20 @@
*
* Each system controller can be accessed by its driver data, which is
* assumed to be unique through the scope of all system controllers that
+ * are in use. This function looks up the controller given this driver data.
+ *
+ * @driver_data: Driver data value to look up
+ * @devp: Returns the controller correponding to @driver_data
+ * @return 0 on success, -ENODEV if the ID was not found, or other -ve error
+ * code
+ */
+int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp);
+
+/**
+ * syscon_get_regmap_by_driver_data() - Look up a controller by its ID
+ *
+ * Each system controller can be accessed by its driver data, which is
+ * assumed to be unique through the scope of all system controllers that
* are in use. This function looks up the regmap given this driver data.
*
* @driver_data: Driver data value to look up
diff --git a/include/usb_ether.h b/include/usb_ether.h
index c6d1416..51fce4e 100644
--- a/include/usb_ether.h
+++ b/include/usb_ether.h
@@ -131,6 +131,12 @@
struct ueth_data *ss);
int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth);
+
+void r8152_eth_before_probe(void);
+int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
+ struct ueth_data *ss);
+int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+ struct eth_device *eth);
#endif
#endif /* __USB_ETHER_H__ */
diff --git a/include/wait_bit.h b/include/wait_bit.h
new file mode 100644
index 0000000..061a2db
--- /dev/null
+++ b/include/wait_bit.h
@@ -0,0 +1,71 @@
+/*
+ * Wait for bit with timeout and ctrlc
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __WAIT_BIT_H
+#define __WAIT_BIT_H
+
+#include <common.h>
+#include <console.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+/**
+ * wait_for_bit() waits for bit set/cleared in register
+ *
+ * Function polls register waiting for specific bit(s) change
+ * (either 0->1 or 1->0). It can fail under two conditions:
+ * - Timeout
+ * - User interaction (CTRL-C)
+ * Function succeeds only if all bits of masked register are set/cleared
+ * (depending on set option).
+ *
+ * @param prefix Prefix added to timeout messagge (message visible only
+ * with debug enabled)
+ * @param reg Register that will be read (using readl())
+ * @param mask Bit(s) of register that must be active
+ * @param set Selects wait condition (bit set or clear)
+ * @param timeout_ms Timeout (in miliseconds)
+ * @param breakable Enables CTRL-C interruption
+ * @return 0 on success, -ETIMEDOUT or -EINTR on failure
+ */
+static inline int wait_for_bit(const char *prefix, const u32 *reg,
+ const u32 mask, const bool set,
+ const unsigned int timeout_ms,
+ const bool breakable)
+{
+ u32 val;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ val = readl(reg);
+
+ if (!set)
+ val = ~val;
+
+ if ((val & mask) == mask)
+ return 0;
+
+ if (get_timer(start) > timeout_ms)
+ break;
+
+ if (breakable && ctrlc()) {
+ puts("Abort\n");
+ return -EINTR;
+ }
+
+ udelay(1);
+ }
+
+ debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", prefix, reg, mask,
+ set);
+
+ return -ETIMEDOUT;
+}
+
+
+#endif
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index d56e1b1..0eb56af 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -68,7 +68,6 @@
COMPAT(INTEL_X86_PINCTRL, "intel,x86-pinctrl"),
COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
- COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"),
COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 98e09ce..30e6e31 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -130,6 +130,10 @@
cc-disable-warning = $(call try-run,\
$(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1)))
+# cc-name
+# Expands to either gcc or clang
+cc-name = $(shell $(CC) -v 2>&1 | grep -q "clang version" && echo clang || echo gcc)
+
# cc-version
cc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CC))
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 96f414a..dff16b9 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -53,7 +53,7 @@
libs-$(CONFIG_SPL_FRAMEWORK) += common/spl/
libs-y += common/init/
-libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/
+libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ cmd/
libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/
libs-y += drivers/
libs-y += dts/
diff --git a/test/dm/syscon.c b/test/dm/syscon.c
index 3642481..c40f5fc 100644
--- a/test/dm/syscon.c
+++ b/test/dm/syscon.c
@@ -29,3 +29,20 @@
return 0;
}
DM_TEST(dm_test_syscon_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test system controller finding */
+static int dm_test_syscon_by_driver_data(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(syscon_get_by_driver_data(SYSCON0, &dev));
+ ut_asserteq(SYSCON0, dev->driver_data);
+
+ ut_assertok(syscon_get_by_driver_data(SYSCON1, &dev));
+ ut_asserteq(SYSCON1, dev->driver_data);
+
+ ut_asserteq(-ENODEV, syscon_get_by_driver_data(2, &dev));
+
+ return 0;
+}
+DM_TEST(dm_test_syscon_by_driver_data, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);