nds32: Support AE3XX platform.
Support Andestech AE3xx platform: serial, timer device tree flow.
Signed-off-by: rick <rick@andestech.com>
diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
index 7d5ae96..3a9ada1 100644
--- a/arch/nds32/cpu/n1213/Makefile
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -12,3 +12,4 @@
extra-y = start.o
obj-$(if $(filter ag101,$(SOC)),y) += ag101/
+obj-$(if $(filter ae3xx,$(SOC)),y) += ae3xx/
diff --git a/arch/nds32/cpu/n1213/ae3xx/Makefile b/arch/nds32/cpu/n1213/ae3xx/Makefile
new file mode 100644
index 0000000..07fa942
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ae3xx/Makefile
@@ -0,0 +1,18 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cpu.o timer.o
+obj-y += lowlevel_init.o
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+obj-y += watchdog.o
+endif
diff --git a/arch/nds32/cpu/n1213/ae3xx/cpu.c b/arch/nds32/cpu/n1213/ae3xx/cpu.c
new file mode 100644
index 0000000..26f878f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ae3xx/cpu.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ /* turn off I/D-cache */
+ cache_flush();
+ icache_disable();
+ dcache_disable();
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ disable_interrupts();
+ panic("AE3XX wdt not support yet.\n");
+}
diff --git a/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S b/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S
new file mode 100644
index 0000000..d4bc2bc
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.pic
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#include <asm/macro.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
+#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
+#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
+#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
+#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
+
+#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
+#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
+#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
+#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
+
+#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
+#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
+
+
+/*
+ * for Orca and Emerald
+ */
+#define BOARD_ID_REG 0x104
+#define BOARD_ID_FAMILY_MASK 0xfff000
+#define BOARD_ID_FAMILY_V5 0x556000
+#define BOARD_ID_FAMILY_K7 0x74b000
+
+/*
+ * parameters for the static memory controller
+ */
+#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
+#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
+
+#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
+#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
+
+/*
+ * for Orca and Emerald
+ */
+#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
+#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the pmu controoler
+ */
+#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+
+/*
+ * numeric 7 segment display
+ */
+.macro led, num
+ write32 CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro wait_sdram
+ li $r0, CONFIG_FTSDMC021_BASE
+1:
+ lwi $r1, [$r0+FTSDMC021_CR2]
+ bnez $r1, 1b
+.endm
+
+.globl mem_init
+mem_init:
+ move $r11, $lp
+ li $r0, SMC_BANK0_CR_A
+ lwi $r1, [$r0+#0x00]
+ ori $r1, $r1, 0x8f0
+ xori $r1, $r1, 0x8f0
+ /* 16-bit mode */
+ ori $r1, $r1, 0x60
+ li $r2, 0x00153153
+ swi $r1, [$r0+#0x00]
+ swi $r2, [$r0+#0x04]
+ move $lp, $r11
+ ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl lowlevel_init
+lowlevel_init:
+ move $r10, $lp
+ jal remap
+
+#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
+ jal enable_fpu
+#endif
+ ret $r10
+
+remap:
+ move $r11, $lp
+relo_base:
+ mfusr $r0, $pc
+
+#ifdef CONFIG_MEM_REMAP
+ li $r4, 0x00000000
+ li $r5, 0x80000000
+ la $r6, _end@GOTOFF
+1:
+ lmw.bim $r12, [$r5], $r19
+ smw.bim $r12, [$r4], $r19
+ blt $r5, $r6, 1b
+#endif /* #ifdef CONFIG_MEM_REMAP */
+ move $lp, $r11
+2:
+ ret
+
+ /*
+ * enable_fpu:
+ * Some of Andes CPU version support FPU coprocessor, if so,
+ * and toolchain support FPU instruction set, we should enable it.
+ */
+#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
+enable_fpu:
+ mfsr $r0, $CPU_VER /* enable FPU if it exists */
+ srli $r0, $r0, 3
+ andi $r0, $r0, 1
+ beqz $r0, 1f /* skip if no COP */
+ mfsr $r0, $FUCOP_EXIST
+ srli $r0, $r0, 31
+ beqz $r0, 1f /* skip if no FPU */
+ mfsr $r0, $FUCOP_CTL
+ ori $r0, $r0, 1
+ mtsr $r0, $FUCOP_CTL
+1:
+ ret
+#endif
+
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ae3xx/timer.c b/arch/nds32/cpu/n1213/ae3xx/timer.c
new file mode 100644
index 0000000..a284bf5
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ae3xx/timer.c
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef CONFIG_TIMER
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+#error "AE3XX timer only support DM flow"
+#endif /* CONFIG_TIMER */
diff --git a/arch/nds32/cpu/n1213/ae3xx/watchdog.S b/arch/nds32/cpu/n1213/ae3xx/watchdog.S
new file mode 100644
index 0000000..956c5f8
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ae3xx/watchdog.S
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch-ag101/ag101.h>
+#include <linux/linkage.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+ENTRY(turnoff_watchdog)
+#error "AE3XX not support wdt yet"
+ENDPROC(turnoff_watchdog)
+#endif
diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
index c21ce02..07fa942 100644
--- a/arch/nds32/cpu/n1213/ag101/Makefile
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -11,10 +11,7 @@
#
obj-y := cpu.o timer.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
obj-y += lowlevel_init.o
-endif
ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
obj-y += watchdog.o
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
index 31d7271..9da0b31 100644
--- a/arch/nds32/cpu/n1213/ag101/cpu.c
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -31,16 +31,10 @@
{
disable_interrupts();
-#ifdef CONFIG_MMU
/* turn off I/D-cache */
+ cache_flush();
icache_disable();
dcache_disable();
-
- /* flush I/D-cache */
- invalidate_icac();
- invalidate_dcac();
-#endif
-
return 0;
}
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
index abdd340..452d814 100644
--- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -86,25 +86,7 @@
bnez $r1, 1b
.endm
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-.globl lowlevel_init
-lowlevel_init:
- move $r10, $lp
-
- led 0x0
- jal mem_init
-
- led 0x10
- jal remap
-
-#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
- led 0x1f
- jal enable_fpu
-#endif
-
- led 0x20
- ret $r10
-
+.globl mem_init
mem_init:
move $r11, $lp
@@ -124,9 +106,7 @@
lwi $r1, [$r0+#0x00]
ori $r1, $r1, 0x8f0
xori $r1, $r1, 0x8f0
- /*
- * check board
- */
+ /* check board */
li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
lwi $r3, [$r3]
li $r4, BOARD_ID_FAMILY_MASK
@@ -134,29 +114,21 @@
li $r4, BOARD_ID_FAMILY_K7
xor $r4, $r3, $r4
beqz $r4, use_flash_16bit_boot
- /*
- * 32-bit mode
- */
+ /* 32-bit mode */
use_flash_32bit_boot:
ori $r1, $r1, 0x50
li $r2, 0x00151151
j sdram_b0_cr
- /*
- * 16-bit mode
- */
+ /* 16-bit mode */
use_flash_16bit_boot:
ori $r1, $r1, 0x60
li $r2, 0x00153153
- /*
- * SRAM bank0 config
- */
+ /* SRAM bank0 config */
sdram_b0_cr:
swi $r1, [$r0+#0x00]
swi $r2, [$r0+#0x04]
- /*
- * config AHB Controller
- */
+ /* config AHB Controller */
led 0x02
/*
@@ -192,6 +164,21 @@
move $lp, $r11
ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+.globl lowlevel_init
+lowlevel_init:
+ move $r10, $lp
+ led 0x10
+ jal remap
+#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
+ led 0x1f
+ jal enable_fpu
+#endif
+ led 0x20
+ ret $r10
+
remap:
move $r11, $lp
#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
@@ -203,9 +190,7 @@
mfusr $r0, $pc
#endif /* __NDS32_N1213_43U1H__ */
- /*
- * Remapping
- */
+ /* Remapping */
led 0x1a
write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800
write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index 7992fd9..f9f9999 100644
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -114,11 +114,39 @@
set_ivb:
li $r0, 0x0
-
/* turn on BTB */
mtsr $r0, $misc_ctl
/* set IVIC, vector size: 4 bytes, base: 0x0 */
mtsr $r0, $ivb
+/*
+ * MMU_CTL NTC0 Cacheable/Write-Back
+ */
+ li $r0, ~0x3
+ mfsr $r1, $mr8
+ and $r1, $r1, $r0
+ mtsr $r1, $mr8
+#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
+ li $r0, 0x4
+ mfsr $r1, $mr0
+ or $r1, $r1, $r0
+ mtsr $r1, $mr0
+#endif
+
+#if !defined(CONFIG_SYS_ICACHE_OFF)
+ li $r0, 0x1
+ mfsr $r1, $mr8
+ or $r1, $r1, $r0
+ mtsr $r1, $mr8
+#endif
+
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ li $r0, 0x2
+ mfsr $r1, $mr8
+ or $r1, $r1, $r0
+ mtsr $r1, $mr8
+#endif
+
+ jal mem_init
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
jal lowlevel_init
@@ -133,7 +161,6 @@
ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
add5.pc $gp
#endif
-
/*
* do critical initializations first (shall be in short time)
* do self_relocation ASAP.
@@ -169,7 +196,6 @@
bal debug_uart_init
#endif
li $r0, 0x00000000
-
#ifdef __PIC__
#ifdef __NDS32_N1213_43U1H__
/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
@@ -205,12 +231,10 @@
la $r1, _end@GOTOFF
move $r2, $r6 /* r2 <- scratch for copy_loop */
-
copy_loop:
- lwi.p $r7, [$r0], #4
- swi.p $r7, [$r2], #4
+ lmw.bim $r11, [$r0], $r18
+ smw.bim $r11, [$r2], $r18
blt $r0, $r1, copy_loop
-
/*
* fix relocations related issues
*/
@@ -250,6 +274,8 @@
* initialization, now running from RAM.
*/
call_board_init_r:
+ bal invalidate_icache_all
+ bal flush_dcache_all
la $r0, board_init_r@GOTOFF
move $lp, $r0 /* offset of board_init_r() */
add $lp, $lp, $r9 /* real address of board_init_r() */