powerpc: Migrate SYS_L3_SIZE to Kconfig
Introduce three options, one for each observed L3 cache size, and have
the size select'd as needed.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7abfe26..24d3f1f 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -165,6 +165,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select FSL_CORENET
select PHYS_64BIT
+ select SYS_L3_SIZE_1024KB
imply CMD_SATA
imply FSL_SATA
@@ -182,6 +183,7 @@
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
+ select SYS_L3_SIZE_256KB
imply CMD_EEPROM
imply PANIC_HANG
@@ -191,6 +193,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select SYS_L3_SIZE_256KB
config TARGET_T1042D4RDB
bool "Support T1042D4RDB"
@@ -198,6 +201,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select SYS_L3_SIZE_256KB
imply PANIC_HANG
config TARGET_T1042RDB_PI
@@ -206,6 +210,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select SYS_L3_SIZE_256KB
imply PANIC_HANG
config TARGET_T2080QDS
@@ -216,6 +221,7 @@
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
+ select SYS_L3_SIZE_512KB
imply CMD_SATA
config TARGET_T2080RDB
@@ -224,6 +230,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select SYS_L3_SIZE_512KB
imply CMD_SATA
imply PANIC_HANG
@@ -233,6 +240,7 @@
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ select SYS_L3_SIZE_512KB
imply CMD_SATA
imply PANIC_HANG
@@ -244,6 +252,7 @@
bool "Support kmcent2"
select VENDOR_KM
select FSL_CORENET
+ select SYS_L3_SIZE_256KB
endchoice
@@ -1296,6 +1305,21 @@
config BACKSIDE_L2_CACHE
bool
+config SYS_L3_SIZE_256KB
+ bool
+
+config SYS_L3_SIZE_512KB
+ bool
+
+config SYS_L3_SIZE_1024KB
+ bool
+
+config SYS_L3_SIZE
+ int
+ default 262144 if SYS_L3_SIZE_256KB
+ default 524288 if SYS_L3_SIZE_512KB
+ default 1048576 if SYS_L3_SIZE_512KB
+
config SYS_PPC64
bool
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index f4027ed..874910f 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -59,8 +59,6 @@
#else
#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
#endif
-#define CONFIG_SYS_L3_SIZE (1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR 0xf0000000
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 27bc387..72b98c5 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -104,7 +104,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (256 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index d91a13f..f8c9054 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -78,7 +78,6 @@
* (CONFIG_SYS_INIT_L3_VADDR) will be different.
*/
#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE 256 << 10
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 5d5d634..8d3b496 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -76,7 +76,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 407350c..86c92de 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -71,7 +71,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index c8875c8..05c4406 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -52,7 +52,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 3def001..e5cc62e 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -154,7 +154,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE 256 << 10
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull