commit b93ab2ee751a4a0231330a89e2f2f29963b434d0
author Peng Fan <Peng.Fan@freescale.com> Wed Dec 31 11:01:38 2014 +0800
committer Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Wed Dec 31 14:52:32 2014 +0530
tree ff1294c78d954dbe2ffcb006bcc9dc21552eb347
parent ed0c81c654209a2af71393e8756d94c7e944646b

arm:mx6sx add QSPI support

Add QSPI support for mx6solox.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

drivers/spi/fsl_qspi.c

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index eae2f3a..e9c45de 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,7 +14,11 @@
 #include "fsl_qspi.h"
 
 #define RX_BUFFER_SIZE		0x80
+#ifdef CONFIG_MX6SX
+#define TX_BUFFER_SIZE		0x200
+#else
 #define TX_BUFFER_SIZE		0x40
+#endif
 
 #define OFFSET_BITS_MASK	0x00ffffff
 
@@ -53,10 +57,16 @@
 
 static unsigned long spi_bases[] = {
 	QSPI0_BASE_ADDR,
+#ifdef CONFIG_MX6SX
+	QSPI1_BASE_ADDR,
+#endif
 };
 
 static unsigned long amba_bases[] = {
 	QSPI0_AMBA_BASE,
+#ifdef CONFIG_MX6SX
+	QSPI1_AMBA_BASE,
+#endif
 };
 
 struct fsl_qspi {
@@ -159,8 +169,17 @@
 		qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) |
 			PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 			PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+#ifdef CONFIG_MX6SX
+	/*
+	 * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
+	 * So, Use IDATSZ in IPCR to determine the size and here set 0.
+	 */
+	qspi_write32(&regs->lut[lut_base + 1], OPRND0(0) |
+		     PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+#else
 	qspi_write32(&regs->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
 		PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+#endif
 	qspi_write32(&regs->lut[lut_base + 2], 0);
 	qspi_write32(&regs->lut[lut_base + 3], 0);