Changed PPC405GPr version from A to B.
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 8aaffb1..8532d28 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -67,7 +67,7 @@
#if CONFIG_405GP
puts("IBM PowerPC 405GP");
- if (pvr == PVR_405GPR_RA) {
+ if (pvr == PVR_405GPR_RB) {
putc('r');
}
puts(" Rev. ");
@@ -77,6 +77,7 @@
#endif
switch (pvr) {
case PVR_405GP_RB:
+ case PVR_405GPR_RB:
putc('B');
break;
case PVR_405GP_RC:
@@ -94,7 +95,6 @@
break;
#endif
case PVR_405CR_RA:
- case PVR_405GPR_RA:
putc('A');
break;
case PVR_405CR_RB:
@@ -122,7 +122,7 @@
printf("external PCI arbiter enabled\n");
#endif
- if ((pvr | 0x00000001) == PVR_405GPR_RA) {
+ if ((pvr | 0x00000001) == PVR_405GPR_RB) {
printf(" 16 kB I-Cache 16 kB D-Cache");
} else {
printf(" 16 kB I-Cache 8 kB D-Cache");
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 9bf180f..1d149bc 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -149,7 +149,7 @@
* Set edge conditioning circuitry on PPC405GPr
* for compatibility to existing PPC405GP designs.
*/
- if ((pvr & 0xfffffff0) == (PVR_405GPR_RA & 0xfffffff0)) {
+ if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
mtdcr(ecr, 0x60606000);
}
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 4541529..f075e3a 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -87,7 +87,7 @@
/*
* Check if PPC405GPr used (mask minor revision field)
*/
- if ((pvr & 0xfffffff0) == (PVR_405GPR_RA & 0xfffffff0)) {
+ if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
/*
* Determine FWD_DIV B (only PPC405GPr with new mode strapping).
*/