| commit | bade208b5deb16120c6236e941c6e5f081e86c05 | [log] [tgz] |
|---|---|---|
| author | Samuel Holland <samuel@sholland.org> | Tue Oct 31 00:37:20 2023 -0500 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Thu Nov 02 15:15:54 2023 +0800 |
| tree | edd244a408ee39723cd49de76291b16d8c0aeb88 | |
| parent | 3b00fab616b1150da745bbb36f6644842a24624f [diff] |
riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>