commit bc493d911e8c4e59ddaf0def0d35f1e2db0899ab
author Siva Durga Prasad Paladugu <sivadur@xilinx.com> Mon Jul 01 12:19:25 2019 +0530
committer Michal Simek <michal.simek@xilinx.com> Tue Oct 08 09:41:27 2019 +0200
tree f374be8c2fc31e7477219d8a31313cbf330532ee
parent 95105089afe2a204883e9c0f4c2c694469ec31d1

net: zynq_gem: Remove check for Versal

This patch removes check for Versal platform
in gem driver as it now supports clock setting
through clock framework.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drivers/net/zynq_gem.c

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index a35ecab..a7a6ce9 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -463,7 +463,6 @@
 		break;
 	}
 
-#if !defined(CONFIG_ARCH_VERSAL)
 	ret = clk_set_rate(&priv->clk, clk_rate);
 	if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
 		dev_err(dev, "failed to set tx clock rate\n");
@@ -475,9 +474,6 @@
 		dev_err(dev, "failed to enable tx clock\n");
 		return ret;
 	}
-#else
-	debug("requested clk_rate %ld\n", clk_rate);
-#endif
 
 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 					ZYNQ_GEM_NWCTRL_TXEN_MASK);