arm: Show cache warnings in U-Boot proper only

Avoid bloating the SPL image size.

Signed-off-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 642a952..d330b09 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -61,8 +61,8 @@
 		ok = 0;
 
 	if (!ok) {
-		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
-		      start, stop);
+		warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			     start, stop);
 	}
 
 	return ok;