arm: stm32mp: protect DBGMCU_IDC access with BSEC
As debugger must be totally closed on Sec closed chip,
the DBGMCU_IDC register is no more accessible (self
hosted debug is disabled with OTP).
This patch adds a function bsec_dbgswenable() to check
if the DBGMCU registers are available before to access them:
BSEC_DENABLE.DBGSWENABLE = self hosted debug status.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 472b140..3820671 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -12,6 +12,7 @@
#include <misc.h>
#include <net.h>
#include <asm/io.h>
+#include <asm/arch/bsec.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
@@ -155,8 +156,13 @@
{
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
- /* Freeze IWDG2 if Cortex-A7 is in debug mode */
- setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
+ /*
+ * Freeze IWDG2 if Cortex-A7 is in debug mode
+ * done in TF-A for TRUSTED boot and
+ * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
+ */
+ if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable())
+ setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
}
#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
@@ -276,9 +282,17 @@
static u32 read_idc(void)
{
- setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+ /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
+ if (bsec_dbgswenable()) {
+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
- return readl(DBGMCU_IDC);
+ return readl(DBGMCU_IDC);
+ }
+
+ if (CONFIG_IS_ENABLED(STM32MP15x))
+ return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
+ else
+ return 0x0;
}
u32 get_cpu_dev(void)