| commit | bd6eb5ddd715e7441d804c67f434418e172a1423 | [log] [tgz] |
|---|---|---|
| author | Dario Binacchi <dario.binacchi@amarulasolutions.com> | Sat Nov 11 11:46:18 2023 +0100 |
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | Fri Dec 15 15:03:18 2023 +0100 |
| tree | 9878b23810c2287ba8f3578868f31c887c291de6 | |
| parent | 555cf4c49594fba017b88e913bae1cb0992ea553 [diff] |
clk: stm32f: fix setting of division factor for LCD_CLK
The value to be written to the register must be appropriately shifted,
as is correctly done in other parts of the code.
Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>