FSL DDR: Convert socrates to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/board/socrates/Makefile b/board/socrates/Makefile
index a41fead..6fae601 100644
--- a/board/socrates/Makefile
+++ b/board/socrates/Makefile
@@ -28,10 +28,15 @@
LIB = $(obj)lib$(BOARD).a
#
-COBJS := $(BOARD).o law.o tlb.o sdram.o nand.o
+COBJS-y += $(BOARD).o
+COBJS-y += law.o
+COBJS-y += tlb.o
+COBJS-y += nand.o
+COBJS-y += sdram.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c
new file mode 100644
index 0000000..bbb5ee2
--- /dev/null
+++ b/board/socrates/ddr.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+
+ if (ctrl_num) {
+ printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+ return;
+ }
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+ }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index 768fe05..12d1b8a 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -25,6 +25,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <spd_sdram.h>
@@ -80,7 +81,9 @@
{
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram ();
+ dram_size = fsl_ddr_sdram();
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#else
dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
#endif