rockchip: rk3036: Add core Soc start-up code
rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for chromebook_jerry, firefly-rk3288:
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288
diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig
new file mode 100644
index 0000000..d76d5e1
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3036/Kconfig
@@ -0,0 +1,3 @@
+if ROCKCHIP_RK3036
+
+endif