x86: cougarcanyon2: Add missing chipset interrupt information

Add Panther Point chipset interrupt pin/PIRQ information, and
enable the generation of PIRQ routing table and MP table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 98d9aa0..eeee252 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -6,6 +6,8 @@
 # CONFIG_HAVE_INTEL_ME is not set
 # CONFIG_ENABLE_MRC_CACHE is not set
 CONFIG_SMP=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y