* Some code cleanup
* Patch by Josef Baumgartner, 10 Feb 2004:
Fixes for Coldfire port
* Patch by Brad Kemp, 11 Feb 2004:
Fix CFI flash driver problems
diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h
new file mode 100644
index 0000000..3283714
--- /dev/null
+++ b/include/asm-m68k/bitops.h
@@ -0,0 +1,18 @@
+/*
+ * bitops.h: Bit string operations on the m68k
+ */
+
+#ifndef _M68K_BITOPS_H
+#define _M68K_BITOPS_H
+
+#include <linux/config.h>
+#include <asm/byteorder.h>
+
+extern void set_bit(int nr, volatile void *addr);
+extern void clear_bit(int nr, volatile void *addr);
+extern void change_bit(int nr, volatile void *addr);
+extern int test_and_set_bit(int nr, volatile void *addr);
+extern int test_and_clear_bit(int nr, volatile void *addr);
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+#endif /* _M68K_BITOPS_H */
diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h
new file mode 100644
index 0000000..ce613ac
--- /dev/null
+++ b/include/asm-m68k/byteorder.h
@@ -0,0 +1,7 @@
+#ifndef _M68K_BYTEORDER_H
+#define _M68K_BYTEORDER_H
+
+#include <asm/types.h>
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _M68K_BYTEORDER_H */
diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h
new file mode 100644
index 0000000..5bbbfb2
--- /dev/null
+++ b/include/asm-m68k/fec.h
@@ -0,0 +1,86 @@
+/*
+ * fec.h -- Fast Ethernet Controller definitions
+ *
+ * Some definitions copied from commproc.h for MPC8xx:
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef fec_h
+#define fec_h
+
+/* Buffer descriptors used FEC.
+*/
+typedef struct cpm_buf_desc {
+ ushort cbd_sc; /* Status and Control */
+ ushort cbd_datlen; /* Data length in buffer */
+ uint cbd_bufaddr; /* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
+#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
+#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
+#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
+#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
+#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
+#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
+#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
+#define BD_SC_BR ((ushort)0x0020) /* Break received */
+#define BD_SC_FR ((ushort)0x0010) /* Framing error */
+#define BD_SC_PR ((ushort)0x0008) /* Parity error */
+#define BD_SC_OV ((ushort)0x0002) /* Overrun */
+#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY ((ushort)0x8000)
+#define BD_ENET_RX_WRAP ((ushort)0x2000)
+#define BD_ENET_RX_INTR ((ushort)0x1000)
+#define BD_ENET_RX_LAST ((ushort)0x0800)
+#define BD_ENET_RX_FIRST ((ushort)0x0400)
+#define BD_ENET_RX_MISS ((ushort)0x0100)
+#define BD_ENET_RX_LG ((ushort)0x0020)
+#define BD_ENET_RX_NO ((ushort)0x0010)
+#define BD_ENET_RX_SH ((ushort)0x0008)
+#define BD_ENET_RX_CR ((ushort)0x0004)
+#define BD_ENET_RX_OV ((ushort)0x0002)
+#define BD_ENET_RX_CL ((ushort)0x0001)
+#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY ((ushort)0x8000)
+#define BD_ENET_TX_PAD ((ushort)0x4000)
+#define BD_ENET_TX_WRAP ((ushort)0x2000)
+#define BD_ENET_TX_INTR ((ushort)0x1000)
+#define BD_ENET_TX_LAST ((ushort)0x0800)
+#define BD_ENET_TX_TC ((ushort)0x0400)
+#define BD_ENET_TX_DEF ((ushort)0x0200)
+#define BD_ENET_TX_HB ((ushort)0x0100)
+#define BD_ENET_TX_LC ((ushort)0x0080)
+#define BD_ENET_TX_RL ((ushort)0x0040)
+#define BD_ENET_TX_RCMASK ((ushort)0x003c)
+#define BD_ENET_TX_UN ((ushort)0x0002)
+#define BD_ENET_TX_CSL ((ushort)0x0001)
+#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
+
+#endif /* fec_h */
diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h
index 89bc0ad..f8a3d88 100644
--- a/include/asm-m68k/global_data.h
+++ b/include/asm-m68k/global_data.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2002-2003
+ * (C) Copyright 2002 - 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -48,6 +48,7 @@
#ifdef CONFIG_BOARD_TYPES
unsigned long board_type;
#endif
+ void **jt; /* Standalone app jump table */
} gd_t;
/*
@@ -56,7 +57,11 @@
#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
+#if 0
extern gd_t *global_data;
#define DECLARE_GLOBAL_DATA_PTR gd_t *gd = global_data
+#else
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("d7")
+#endif
#endif /* __ASM_GBL_DATA_H */
diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h
new file mode 100644
index 0000000..ecb4906
--- /dev/null
+++ b/include/asm-m68k/immap_5272.h
@@ -0,0 +1,447 @@
+/*
+ * MCF5272 Internal Memory Map
+ *
+ * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5272__
+#define __IMMAP_5272__
+
+/* System configuration registers
+*/
+typedef struct sys_ctrl {
+ uint sc_mbar;
+ ushort sc_scr;
+ ushort sc_spr;
+ uint sc_pmr;
+ char res1[2];
+ ushort sc_alpr;
+ uint sc_dir;
+ char res2[12];
+} sysctrl_t;
+
+/* Interrupt module registers
+*/
+typedef struct int_ctrl {
+ uint int_icr1;
+ uint int_icr2;
+ uint int_icr3;
+ uint int_icr4;
+ uint int_isr;
+ uint int_pitr;
+ uint int_piwr;
+ uchar res1[3];
+ uchar int_pivr;
+} intctrl_t;
+
+/* Chip select module registers.
+*/
+typedef struct cs_ctlr {
+ uint cs_br0;
+ uint cs_or0;
+ uint cs_br1;
+ uint cs_or1;
+ uint cs_br2;
+ uint cs_or2;
+ uint cs_br3;
+ uint cs_or3;
+ uint cs_br4;
+ uint cs_or4;
+ uint cs_br5;
+ uint cs_or5;
+ uint cs_br6;
+ uint cs_or6;
+ uint cs_br7;
+ uint cs_or7;
+} csctrl_t;
+
+/* GPIO port registers
+*/
+typedef struct gpio_ctrl {
+ uint gpio_pacnt;
+ ushort gpio_paddr;
+ ushort gpio_padat;
+ uint gpio_pbcnt;
+ ushort gpio_pbddr;
+ ushort gpio_pbdat;
+ uchar res1[4];
+ ushort gpio_pcddr;
+ ushort gpio_pcdat;
+ uint gpio_pdcnt;
+ uchar res2[4];
+} gpio_t;
+
+/* QSPI module registers
+ */
+typedef struct qspi_ctrl {
+ ushort qspi_qmr;
+ uchar res1[2];
+ ushort qspi_qdlyr;
+ uchar res2[2];
+ ushort qspi_qwr;
+ uchar res3[2];
+ ushort qspi_qir;
+ uchar res4[2];
+ ushort qspi_qar;
+ uchar res5[2];
+ ushort qspi_qdr;
+ uchar res6[10];
+} qspi_t;
+
+/* PWM module registers
+ */
+typedef struct pwm_ctrl {
+ uchar pwm_pwcr0;
+ uchar res1[3];
+ uchar pwm_pwcr1;
+ uchar res2[3];
+ uchar pwm_pwcr2;
+ uchar res3[7];
+ uchar pwm_pwwd0;
+ uchar res4[3];
+ uchar pwm_pwwd1;
+ uchar res5[3];
+ uchar pwm_pwwd2;
+ uchar res6[7];
+} pwm_t;
+
+/* DMA module registers
+ */
+typedef struct dma_ctrl {
+ ulong dma_dmr;
+ uchar res1[2];
+ ushort dma_dir;
+ ulong dma_dbcr;
+ ulong dma_dsar;
+ ulong dma_ddar;
+ uchar res2[12];
+} dma_t;
+
+/* UART module registers
+ */
+typedef struct uart_ctrl {
+ uchar uart_umr;
+ uchar res1[3];
+ uchar uart_usr_ucsr;
+ uchar res2[3];
+ uchar uart_ucr;
+ uchar res3[3];
+ uchar uart_urb_utb;
+ uchar res4[3];
+ uchar uart_uipcr_uacr;
+ uchar res5[3];
+ uchar uart_uisr_uimr;
+ uchar res6[3];
+ uchar uart_udu;
+ uchar res7[3];
+ uchar uart_udl;
+ uchar res8[3];
+ uchar uart_uabu;
+ uchar res9[3];
+ uchar uart_uabl;
+ uchar res10[3];
+ uchar uart_utf;
+ uchar res11[3];
+ uchar uart_urf;
+ uchar res12[3];
+ uchar uart_ufpd;
+ uchar res13[3];
+ uchar uart_uip;
+ uchar res14[3];
+ uchar uart_uop1;
+ uchar res15[3];
+ uchar uart_uop0;
+ uchar res16[3];
+} uart_t;
+
+/* SDRAM controller registers, offset: 0x180
+ */
+typedef struct sdram_ctrl {
+ uchar res1[2];
+ ushort sdram_sdcr;
+ uchar res2[2];
+ ushort sdram_sdtr;
+ uchar res3[120];
+} sdramctrl_t;
+
+/* Timer module registers
+ */
+typedef struct timer_ctrl {
+ ushort timer_tmr;
+ ushort res1;
+ ushort timer_trr;
+ ushort res2;
+ ushort timer_tcap;
+ ushort res3;
+ ushort timer_tcn;
+ ushort res4;
+ ushort timer_ter;
+ uchar res5[14];
+} timer_t;
+
+/* Watchdog registers
+ */
+typedef struct wdog_ctrl {
+ ushort wdog_wrrr;
+ ushort res1;
+ ushort wdog_wirr;
+ ushort res2;
+ ushort wdog_wcr;
+ ushort res3;
+ ushort wdog_wer;
+ uchar res4[114];
+} wdog_t;
+
+/* PLIC module registers
+ */
+typedef struct plic_ctrl {
+ ulong plic_p0b1rr;
+ ulong plic_p1b1rr;
+ ulong plic_p2b1rr;
+ ulong plic_p3b1rr;
+ ulong plic_p0b2rr;
+ ulong plic_p1b2rr;
+ ulong plic_p2b2rr;
+ ulong plic_p3b2rr;
+ uchar plic_p0drr;
+ uchar plic_p1drr;
+ uchar plic_p2drr;
+ uchar plic_p3drr;
+ uchar res1[4];
+ ulong plic_p0b1tr;
+ ulong plic_p1b1tr;
+ ulong plic_p2b1tr;
+ ulong plic_p3b1tr;
+ ulong plic_p0b2tr;
+ ulong plic_p1b2tr;
+ ulong plic_p2b2tr;
+ ulong plic_p3b2tr;
+ uchar plic_p0dtr;
+ uchar plic_p1dtr;
+ uchar plic_p2dtr;
+ uchar plic_p3dtr;
+ uchar res2[4];
+ ushort plic_p0cr;
+ ushort plic_p1cr;
+ ushort plic_p2cr;
+ ushort plic_p3cr;
+ ushort plic_p0icr;
+ ushort plic_p1icr;
+ ushort plic_p2icr;
+ ushort plic_p3icr;
+ ushort plic_p0gmr;
+ ushort plic_p1gmr;
+ ushort plic_p2gmr;
+ ushort plic_p3gmr;
+ ushort plic_p0gmt;
+ ushort plic_p1gmt;
+ ushort plic_p2gmt;
+ ushort plic_p3gmt;
+ uchar res3;
+ uchar plic_pgmts;
+ uchar plic_pgmta;
+ uchar res4;
+ uchar plic_p0gcir;
+ uchar plic_p1gcir;
+ uchar plic_p2gcir;
+ uchar plic_p3gcir;
+ uchar plic_p0gcit;
+ uchar plic_p1gcit;
+ uchar plic_p2gcit;
+ uchar plic_p3gcit;
+ uchar res5[3];
+ uchar plic_pgcitsr;
+ uchar res6[3];
+ uchar plic_pdcsr;
+ ushort plic_p0psr;
+ ushort plic_p1psr;
+ ushort plic_p2psr;
+ ushort plic_p3psr;
+ ushort plic_pasr;
+ uchar res7;
+ uchar plic_plcr;
+ ushort res8;
+ ushort plic_pdrqr;
+ ushort plic_p0sdr;
+ ushort plic_p1sdr;
+ ushort plic_p2sdr;
+ ushort plic_p3sdr;
+ ushort res9;
+ ushort plic_pcsr;
+ uchar res10[1184];
+} plic_t;
+
+/* Fast ethernet controller registers
+ */
+typedef struct fec {
+ uint fec_ecntrl; /* ethernet control register */
+ uint fec_ievent; /* interrupt event register */
+ uint fec_imask; /* interrupt mask register */
+ uint fec_ivec; /* interrupt level and vector status */
+ uint fec_r_des_active; /* Rx ring updated flag */
+ uint fec_x_des_active; /* Tx ring updated flag */
+ uint res3[10]; /* reserved */
+ uint fec_mii_data; /* MII data register */
+ uint fec_mii_speed; /* MII speed control register */
+ uint res4[17]; /* reserved */
+ uint fec_r_bound; /* end of RAM (read-only) */
+ uint fec_r_fstart; /* Rx FIFO start address */
+ uint res5[6]; /* reserved */
+ uint fec_x_fstart; /* Tx FIFO start address */
+ uint res7[21]; /* reserved */
+ uint fec_r_cntrl; /* Rx control register */
+ uint fec_r_hash; /* Rx hash register */
+ uint res8[14]; /* reserved */
+ uint fec_x_cntrl; /* Tx control register */
+ uint res9[0x9e]; /* reserved */
+ uint fec_addr_low; /* lower 32 bits of station address */
+ uint fec_addr_high; /* upper 16 bits of station address */
+ uint fec_hash_table_high; /* upper 32-bits of hash table */
+ uint fec_hash_table_low; /* lower 32-bits of hash table */
+ uint fec_r_des_start; /* beginning of Rx descriptor ring */
+ uint fec_x_des_start; /* beginning of Tx descriptor ring */
+ uint fec_r_buff_size; /* Rx buffer size */
+ uint res2[9]; /* reserved */
+ uchar fec_fifo[960]; /* fifo RAM */
+} fec_t;
+
+/* USB module registers
+*/
+typedef struct usb {
+ ushort res1;
+ ushort usb_fnr;
+ ushort res2;
+ ushort usb_fnmr;
+ ushort res3;
+ ushort usb_rfmr;
+ ushort res4;
+ ushort usb_rfmmr;
+ uchar res5[3];
+ uchar usb_far;
+ ulong usb_asr;
+ ulong usb_drr1;
+ ulong usb_drr2;
+ ushort res6;
+ ushort usb_specr;
+ ushort res7;
+ ushort usb_ep0sr;
+ ulong usb_iep0cfg;
+ ulong usb_oep0cfg;
+ ulong usb_ep1cfg;
+ ulong usb_ep2cfg;
+ ulong usb_ep3cfg;
+ ulong usb_ep4cfg;
+ ulong usb_ep5cfg;
+ ulong usb_ep6cfg;
+ ulong usb_ep7cfg;
+ ulong usb_ep0ctl;
+ ushort res8;
+ ushort usb_ep1ctl;
+ ushort res9;
+ ushort usb_ep2ctl;
+ ushort res10;
+ ushort usb_ep3ctl;
+ ushort res11;
+ ushort usb_ep4ctl;
+ ushort res12;
+ ushort usb_ep5ctl;
+ ushort res13;
+ ushort usb_ep6ctl;
+ ushort res14;
+ ushort usb_ep7ctl;
+ ulong usb_ep0isr;
+ ushort res15;
+ ushort usb_ep1isr;
+ ushort res16;
+ ushort usb_ep2isr;
+ ushort res17;
+ ushort usb_ep3isr;
+ ushort res18;
+ ushort usb_ep4isr;
+ ushort res19;
+ ushort usb_ep5isr;
+ ushort res20;
+ ushort usb_ep6isr;
+ ushort res21;
+ ushort usb_ep7isr;
+ ulong usb_ep0imr;
+ ushort res22;
+ ushort usb_ep1imr;
+ ushort res23;
+ ushort usb_ep2imr;
+ ushort res24;
+ ushort usb_ep3imr;
+ ushort res25;
+ ushort usb_ep4imr;
+ ushort res26;
+ ushort usb_ep5imr;
+ ushort res27;
+ ushort usb_ep6imr;
+ ushort res28;
+ ushort usb_ep7imr;
+ ulong usb_ep0dr;
+ ulong usb_ep1dr;
+ ulong usb_ep2dr;
+ ulong usb_ep3dr;
+ ulong usb_ep4dr;
+ ulong usb_ep5dr;
+ ulong usb_ep6dr;
+ ulong usb_ep7dr;
+ ushort res29;
+ ushort usb_ep0dpr;
+ ushort res30;
+ ushort usb_ep1dpr;
+ ushort res31;
+ ushort usb_ep2dpr;
+ ushort res32;
+ ushort usb_ep3dpr;
+ ushort res33;
+ ushort usb_ep4dpr;
+ ushort res34;
+ ushort usb_ep5dpr;
+ ushort res35;
+ ushort usb_ep6dpr;
+ ushort res36;
+ ushort usb_ep7dpr;
+ uchar res37[788];
+ uchar usb_cfgram[1024];
+} usb_t;
+
+/* Internal memory map.
+*/
+typedef struct immap {
+ sysctrl_t sysctrl_reg; /* System configuration registers */
+ intctrl_t intctrl_reg; /* Interrupt controller registers */
+ csctrl_t csctrl_reg; /* Chip select controller registers */
+ gpio_t gpio_reg; /* GPIO controller registers */
+ qspi_t qspi_reg; /* QSPI controller registers */
+ pwm_t pwm_reg; /* Pulse width modulation registers */
+ dma_t dma_reg; /* DMA registers */
+ uart_t uart_reg[2]; /* UART registers */
+ sdramctrl_t sdram_reg; /* SDRAM controller registers */
+ timer_t timer_reg[4]; /* Timer registers */
+ wdog_t wdog_reg; /* Watchdog registers */
+ plic_t plic_reg; /* Physical layer interface registers */
+ fec_t fec_reg; /* Fast ethernet controller registers */
+ usb_t usb_reg; /* USB controller registers */
+} immap_t;
+
+#endif /* __IMMAP_5272__ */
diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h
new file mode 100644
index 0000000..f2b77db
--- /dev/null
+++ b/include/asm-m68k/immap_5282.h
@@ -0,0 +1,63 @@
+/*
+ * MCF5282 Internal Memory Map
+ *
+ * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5282__
+#define __IMMAP_5282__
+
+
+/* Fast ethernet controller registers
+ */
+typedef struct fec {
+ uint fec_ecntrl; /* ethernet control register */
+ uint fec_ievent; /* interrupt event register */
+ uint fec_imask; /* interrupt mask register */
+ uint fec_ivec; /* interrupt level and vector status */
+ uint fec_r_des_active; /* Rx ring updated flag */
+ uint fec_x_des_active; /* Tx ring updated flag */
+ uint res3[10]; /* reserved */
+ uint fec_mii_data; /* MII data register */
+ uint fec_mii_speed; /* MII speed control register */
+ uint res4[17]; /* reserved */
+ uint fec_r_bound; /* end of RAM (read-only) */
+ uint fec_r_fstart; /* Rx FIFO start address */
+ uint res5[6]; /* reserved */
+ uint fec_x_fstart; /* Tx FIFO start address */
+ uint res7[21]; /* reserved */
+ uint fec_r_cntrl; /* Rx control register */
+ uint fec_r_hash; /* Rx hash register */
+ uint res8[14]; /* reserved */
+ uint fec_x_cntrl; /* Tx control register */
+ uint res9[0x9e]; /* reserved */
+ uint fec_addr_low; /* lower 32 bits of station address */
+ uint fec_addr_high; /* upper 16 bits of station address */
+ uint fec_hash_table_high; /* upper 32-bits of hash table */
+ uint fec_hash_table_low; /* lower 32-bits of hash table */
+ uint fec_r_des_start; /* beginning of Rx descriptor ring */
+ uint fec_x_des_start; /* beginning of Tx descriptor ring */
+ uint fec_r_buff_size; /* Rx buffer size */
+ uint res2[9]; /* reserved */
+ uchar fec_fifo[960]; /* fifo RAM */
+} fec_t;
+
+#endif /* __IMMAP_5282__ */
diff --git a/include/asm-m68k/m5272.h b/include/asm-m68k/m5272.h
new file mode 100644
index 0000000..54d4a32
--- /dev/null
+++ b/include/asm-m68k/m5272.h
@@ -0,0 +1,99 @@
+/*
+ * mcf5272.h -- Definitions for Motorola Coldfire 5272
+ *
+ * Based on mcf5272sim.h of uCLinux distribution:
+ * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef mcf5272_h
+#define mcf5272_h
+/****************************************************************************/
+
+/*
+ * Size of internal RAM
+ */
+
+#define INT_RAM_SIZE 4096
+
+
+/*
+ * Define the 5272 SIM register set addresses.
+ */
+#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
+#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
+#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
+#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
+#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
+
+#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
+
+#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
+#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
+#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
+#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
+
+#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
+#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
+#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
+#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
+
+#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
+#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
+#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
+#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
+#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
+#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
+#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
+#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
+#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
+#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
+#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
+#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
+#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
+#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
+#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
+#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
+
+#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
+#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
+#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
+#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
+#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
+#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
+
+#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
+#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
+#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
+#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
+#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
+#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
+#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
+#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
+#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
+
+#endif /* mcf5272_h */
diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h
new file mode 100644
index 0000000..073b0bc
--- /dev/null
+++ b/include/asm-m68k/m5282.h
@@ -0,0 +1,60 @@
+/*
+ * mcf5282.h -- Definitions for Motorola Coldfire 5282
+ *
+ * Based on mcf5282sim.h of uCLinux distribution:
+ * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************/
+#ifndef m5282_h
+#define m5282_h
+/****************************************************************************/
+
+/*
+ * Size of internal RAM
+ */
+
+#define INT_RAM_SIZE 65536
+
+
+/*
+ * Define the 5282 SIM register set addresses.
+ */
+#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_IRLR 0x18 /* */
+#define MCFINTC_IACKL 0x19 /* */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+#define MCFINT_UART0 13 /* Interrupt number for UART0 */
+#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
+
+#define MCF5282_GPIO_PUAPAR 0x10005C
+
+
+/****************************************************************************/
+#endif /* m5282_h */
diff --git a/include/asm-m68k/mcftimer.h b/include/asm-m68k/mcftimer.h
new file mode 100644
index 0000000..047950b
--- /dev/null
+++ b/include/asm-m68k/mcftimer.h
@@ -0,0 +1,113 @@
+/*
+ * mcftimer.h -- ColdFire internal TIMER support defines.
+ *
+ * Based on mcftimer.h of uCLinux distribution:
+ * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************/
+#ifndef mcftimer_h
+#define mcftimer_h
+/****************************************************************************/
+
+#include <linux/config.h>
+
+/*
+ * Get address specific defines for this ColdFire member.
+ */
+#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
+#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
+#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
+#elif defined(CONFIG_M5272)
+#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
+#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
+#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
+#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
+#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
+#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
+#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
+#elif defined(CONFIG_M5282)
+#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */
+#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */
+#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */
+#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */
+#endif
+
+/*
+ * Define the TIMER register set addresses.
+ */
+#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
+#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */
+#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */
+#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */
+#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
+
+
+/*
+ * Define the TIMER register set addresses for 5282.
+ */
+#define MCFTIMER_PCSR 0
+#define MCFTIMER_PMR 1
+#define MCFTIMER_PCNTR 2
+
+/*
+ * Bit definitions for the Timer Mode Register (TMR).
+ * Register bit flags are common accross ColdFires.
+ */
+#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
+#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
+#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
+#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
+#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
+#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
+#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
+#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
+#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
+#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
+#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
+#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
+#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
+#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
+#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
+#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
+#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
+
+/*
+ * Bit definitions for the Timer Event Registers (TER).
+ */
+#define MCFTIMER_TER_CAP 0x01 /* Capture event */
+#define MCFTIMER_TER_REF 0x02 /* Refernece event */
+
+/*
+ * Bit definitions for the 5282 PIT Control and Status Register (PCSR).
+ */
+#define MCFTIMER_PCSR_EN 0x0001
+#define MCFTIMER_PCSR_RLD 0x0002
+#define MCFTIMER_PCSR_PIF 0x0004
+#define MCFTIMER_PCSR_PIE 0x0008
+#define MCFTIMER_PCSR_OVW 0x0010
+#define MCFTIMER_PCSR_HALTED 0x0020
+#define MCFTIMER_PCSR_DOZE 0x0040
+
+
+/****************************************************************************/
+#endif /* mcftimer_h */
diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h
new file mode 100644
index 0000000..7b80245
--- /dev/null
+++ b/include/asm-m68k/mcfuart.h
@@ -0,0 +1,217 @@
+/*
+ * mcfuart.h -- ColdFire internal UART support defines.
+ *
+ * File copied from mcfuart.h of uCLinux distribution:
+ * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************/
+#ifndef mcfuart_h
+#define mcfuart_h
+/****************************************************************************/
+
+#include <linux/config.h>
+
+/*
+ * Define the base address of the UARTS within the MBAR address
+ * space.
+ */
+#if defined(CONFIG_M5272)
+#define MCFUART_BASE1 0x100 /* Base address of UART1 */
+#define MCFUART_BASE2 0x140 /* Base address of UART2 */
+#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
+#if defined(CONFIG_NETtel)
+#define MCFUART_BASE1 0x180 /* Base address of UART1 */
+#define MCFUART_BASE2 0x140 /* Base address of UART2 */
+#else
+#define MCFUART_BASE1 0x140 /* Base address of UART1 */
+#define MCFUART_BASE2 0x180 /* Base address of UART2 */
+#endif
+#elif defined(CONFIG_M5282)
+#define MCFUART_BASE1 0x200 /* Base address of UART1 */
+#define MCFUART_BASE2 0x240 /* Base address of UART2 */
+#define MCFUART_BASE3 0x280 /* Base address of UART3 */
+#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
+#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
+#define MCFUART_BASE1 0x200 /* Base address of UART1 */
+#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
+#else
+#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
+#define MCFUART_BASE2 0x200 /* Base address of UART2 */
+#endif
+#endif
+
+
+/*
+ * Define the ColdFire UART register set addresses.
+ */
+#define MCFUART_UMR 0x00 /* Mode register (r/w) */
+#define MCFUART_USR 0x04 /* Status register (r) */
+#define MCFUART_UCSR 0x04 /* Clock Select (w) */
+#define MCFUART_UCR 0x08 /* Command register (w) */
+#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
+#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
+#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
+#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
+#define MCFUART_UISR 0x14 /* Interrup Status (r) */
+#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
+#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
+#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
+#ifdef CONFIG_M5272
+#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
+#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
+#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
+#else
+#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
+#endif
+#define MCFUART_UIPR 0x34 /* Input Port (r) */
+#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
+#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
+
+
+/*
+ * Define bit flags in Mode Register 1 (MR1).
+ */
+#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
+#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
+#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
+#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
+#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
+
+#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
+#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
+#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
+#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
+#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
+
+#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
+#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
+#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
+#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
+
+/*
+ * Define bit flags in Mode Register 2 (MR2).
+ */
+#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
+#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
+#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
+#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
+#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
+
+#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
+#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
+#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
+
+/*
+ * Define bit flags in Status Register (USR).
+ */
+#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
+#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
+#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
+#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
+#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
+#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
+#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
+#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
+
+#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
+ MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
+
+/*
+ * Define bit flags in Clock Select Register (UCSR).
+ */
+#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
+#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
+#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
+
+#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
+#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
+#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
+
+/*
+ * Define bit flags in Command Register (UCR).
+ */
+#define MCFUART_UCR_CMDNULL 0x00 /* No command */
+#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
+#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
+#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
+#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
+#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
+#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
+#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
+
+#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
+#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
+#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
+#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
+#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
+#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
+
+/*
+ * Define bit flags in Input Port Change Register (UIPCR).
+ */
+#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
+#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
+
+/*
+ * Define bit flags in Input Port Register (UIP).
+ */
+#define MCFUART_UIPR_CTS 0x01 /* CTS value */
+
+/*
+ * Define bit flags in Output Port Registers (UOP).
+ * Clear bit by writing to UOP0, set by writing to UOP1.
+ */
+#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
+
+/*
+ * Define bit flags in the Auxiliary Control Register (UACR).
+ */
+#define MCFUART_UACR_IEC 0x01 /* Input enable control */
+
+/*
+ * Define bit flags in Interrupt Status Register (UISR).
+ * These same bits are used for the Interrupt Mask Register (UIMR).
+ */
+#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
+#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
+#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
+#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
+
+#ifdef CONFIG_M5272
+/*
+ * Define bit flags in the Transmitter FIFO Register (UTF).
+ */
+#define MCFUART_UTF_TXB 0x1f /* transmitter data level */
+#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */
+#define MCFUART_UTF_TXS 0xc0 /* transmitter status */
+
+/*
+ * Define bit flags in the Receiver FIFO Register (URF).
+ */
+#define MCFUART_URF_RXB 0x1f /* receiver data level */
+#define MCFUART_URF_FULL 0x20 /* receiver fifo full */
+#define MCFUART_URF_RXS 0xc0 /* receiver status */
+#endif
+
+/****************************************************************************/
+#endif /* mcfuart_h */
diff --git a/include/asm-m68k/processor.h b/include/asm-m68k/processor.h
new file mode 100644
index 0000000..3fafa6f
--- /dev/null
+++ b/include/asm-m68k/processor.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_M68K_PROCESSOR_H
+#define __ASM_M68K_PROCESSOR_H
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+
+#define _GLOBAL(n)\
+ .globl n;\
+n:
+
+/* Macros for setting and retrieving special purpose registers */
+#define setvbr(v) asm volatile("movec %0,%%VBR" : : "r" (v))
+
+#ifndef __ASSEMBLY__
+
+#endif /* ifndef ASSEMBLY*/
+
+#endif /* __ASM_M68K_PROCESSOR_H */
diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h
index 8205518..a80ff90 100644
--- a/include/asm-m68k/ptrace.h
+++ b/include/asm-m68k/ptrace.h
@@ -1,107 +1,59 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
#ifndef _M68K_PTRACE_H
#define _M68K_PTRACE_H
/*
* This struct defines the way the registers are stored on the
- * kernel stack during a system call or other kernel entry.
- *
- * this should only contain volatile regs
- * since we can keep non-volatile in the thread_struct
- * should set this up when only volatiles are saved
- * by intr code.
- *
- * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
- * that the overall structure is a multiple of 16 bytes in length.
- *
- * Note that the offsets of the fields in this struct correspond with
- * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c.
+ * kernel stack during an exception.
*/
-
-#include <linux/config.h>
-
#ifndef __ASSEMBLY__
-#ifdef CONFIG_M68K64BRIDGE
-#define M68K_REG unsigned long /*long*/
-#else
-#define M68K_REG unsigned long
-#endif
+
struct pt_regs {
- M68K_REG gpr[32];
- M68K_REG nip;
- M68K_REG msr;
- M68K_REG orig_gpr3; /* Used for restarting system calls */
- M68K_REG ctr;
- M68K_REG link;
- M68K_REG xer;
- M68K_REG ccr;
- M68K_REG mq; /* 601 only (not used at present) */
- /* Used on APUS to hold IPL value. */
- M68K_REG trap; /* Reason for being here */
- M68K_REG dar; /* Fault registers */
- M68K_REG dsisr;
- M68K_REG result; /* Result of a system call */
+ ulong d0;
+ ulong d1;
+ ulong d2;
+ ulong d3;
+ ulong d4;
+ ulong d5;
+ ulong d6;
+ ulong d7;
+ ulong a0;
+ ulong a1;
+ ulong a2;
+ ulong a3;
+ ulong a4;
+ ulong a5;
+ ulong a6;
+#if defined(CONFIG_M5272) || defined(CONFIG_M5282)
+ unsigned format : 4; /* frame format specifier */
+ unsigned vector : 12; /* vector offset */
+ unsigned short sr;
+ unsigned long pc;
+#else
+ unsigned short sr;
+ unsigned long pc;
+#endif
};
-#endif
-#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
+#endif /* #ifndef __ASSEMBLY__ */
-/* Size of stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE 64
-
-#define instruction_pointer(regs) ((regs)->nip)
-#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
-
-/*
- * Offsets used by 'ptrace' system call interface.
- * These can't be changed without breaking binary compatibility
- * with MkLinux, etc.
- */
-#define PT_R0 0
-#define PT_R1 1
-#define PT_R2 2
-#define PT_R3 3
-#define PT_R4 4
-#define PT_R5 5
-#define PT_R6 6
-#define PT_R7 7
-#define PT_R8 8
-#define PT_R9 9
-#define PT_R10 10
-#define PT_R11 11
-#define PT_R12 12
-#define PT_R13 13
-#define PT_R14 14
-#define PT_R15 15
-#define PT_R16 16
-#define PT_R17 17
-#define PT_R18 18
-#define PT_R19 19
-#define PT_R20 20
-#define PT_R21 21
-#define PT_R22 22
-#define PT_R23 23
-#define PT_R24 24
-#define PT_R25 25
-#define PT_R26 26
-#define PT_R27 27
-#define PT_R28 28
-#define PT_R29 29
-#define PT_R30 30
-#define PT_R31 31
-
-#define PT_NIP 32
-#define PT_MSR 33
-#ifdef __KERNEL__
-#define PT_ORIG_R3 34
-#endif
-#define PT_CTR 35
-#define PT_LNK 36
-#define PT_XER 37
-#define PT_CCR 38
-#define PT_MQ 39
-
-#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
-#define PT_FPR31 (PT_FPR0 + 2*31)
-#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
-
-#endif
+#endif /* #ifndef _M68K_PTRACE_H */
diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h
index b414490..3a21fd2 100644
--- a/include/asm-m68k/u-boot.h
+++ b/include/asm-m68k/u-boot.h
@@ -38,10 +38,11 @@
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
+ unsigned long bi_mbar_base; /* base of internal registers */
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
- unsigned long bi_boot_params; /* where this board expects params */
+ unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_ip_addr; /* IP Address */
- unsigned char bi_enetaddr[6]; /* Ethernet adress */
+ unsigned char bi_enetaddr[6]; /* Ethernet adress */
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
@@ -49,21 +50,5 @@
} bd_t;
#endif /* __ASSEMBLY__ */
-/* The following data structure is placed in DPRAM to allow for a
- * minimum set of global variables during system initialization
- * (until we have set up the memory controller so that we can use
- * RAM).
- *
- * Keep it *SMALL* and remember to set CFG_INIT_DATA_SIZE > sizeof(init_data_t)
- */
-typedef struct init_data {
- unsigned long cpu_clk; /* VCOOUT = CPU clock in Hz! */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- unsigned long relocated; /* Relocat. offset when running in RAM */
- unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_LCD
- unsigned long lcd_base; /* Base address of LCD frambuffer mem */
-#endif
-} init_data_t;
+
#endif /* __U_BOOT_H__ */