| commit | 9087a6ae79e24ecbb98e3376fe4ef42705f9dd0c | [log] [tgz] |
|---|---|---|
| author | Yanhong Wang <yanhong.wang@starfivetech.com> | Wed Mar 29 11:42:21 2023 +0800 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Thu Apr 20 16:08:45 2023 +0800 |
| tree | 3f1ee409145908a214680aa79afd35205077f707 | |
| parent | 331ad93c1279d0eeb971f4830ae88dc9c8202642 [diff] |
riscv: dts: jh7110: Add initial StarFive JH7110 device tree Add initial device tree for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>