commit c3d6a357321570bf1eb94b8de601a7bb3d94de20
author Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Thu Jun 21 13:21:32 2012 +0900
committer Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Wed Aug 08 09:52:03 2012 +0900
tree b12745de2df01f261dc7fd73b9e45e34856f9aa2
parent d1858572674a4959b21fe0a0e33650814d8a6fbb

serial: sh: Add support Renesas SH73A0

The serial device of SH73A0 has the same structure as SH7372 of SH, etc.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

drivers/serial/serial_sh.h

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 601da43..96509e1 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -45,7 +45,8 @@
 	defined(CONFIG_CPU_SH7721) || \
 	defined(CONFIG_ARCH_SH7367) || \
 	defined(CONFIG_ARCH_SH7377) || \
-	defined(CONFIG_ARCH_SH7372)
+	defined(CONFIG_ARCH_SH7372) || \
+	defined(CONFIG_SH73A0)
 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
 # define PORT_PTCR	   0xA405011EUL
 # define PORT_PVCR	   0xA4050122UL
@@ -282,7 +283,8 @@
 	defined(CONFIG_CPU_SH7721) || \
 	defined(CONFIG_ARCH_SH7367) || \
 	defined(CONFIG_ARCH_SH7377) || \
-	defined(CONFIG_ARCH_SH7372)
+	defined(CONFIG_ARCH_SH7372) || \
+	defined(CONFIG_SH73A0)
 # define SCIF_ORER    0x0200
 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 # define SCIF_RFDC_MASK 0x007f
@@ -326,7 +328,8 @@
 	defined(CONFIG_CPU_SH7721) || \
 	defined(CONFIG_ARCH_SH7367) || \
 	defined(CONFIG_ARCH_SH7377) || \
-	defined(CONFIG_ARCH_SH7372)
+	defined(CONFIG_ARCH_SH7372) || \
+	defined(CONFIG_SH73A0)
 # define SCxSR_RDxF_CLEAR(port)	 (sci_in(port, SCxSR) & 0xfffc)
 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
 # define SCxSR_TDxE_CLEAR(port)	 (sci_in(port, SCxSR) & 0xffdf)
@@ -420,7 +423,8 @@
 #if defined(CONFIG_SH3) || \
 	defined(CONFIG_ARCH_SH7367) || \
 	defined(CONFIG_ARCH_SH7377) || \
-	defined(CONFIG_ARCH_SH7372)
+	defined(CONFIG_ARCH_SH7372) || \
+	defined(CONFIG_SH73A0)
 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
 				sh4_sci_offset, sh4_sci_size, \
@@ -436,7 +440,8 @@
 	defined(CONFIG_CPU_SH7720) || \
 	defined(CONFIG_CPU_SH7721) || \
 	defined(CONFIG_ARCH_SH7367) || \
-	defined(CONFIG_ARCH_SH7377)
+	defined(CONFIG_ARCH_SH7377) || \
+	defined(CONFIG_SH73A0)
 #define SCIF_FNS(name, scif_offset, scif_size) \
 	CPU_SCIF_FNS(name, scif_offset, scif_size)
 #elif defined(CONFIG_ARCH_SH7372)
@@ -492,7 +497,8 @@
 	defined(CONFIG_CPU_SH7720) || \
 	defined(CONFIG_CPU_SH7721) || \
 	defined(CONFIG_ARCH_SH7367) || \
-	defined(CONFIG_ARCH_SH7377)
+	defined(CONFIG_ARCH_SH7377) || \
+	defined(CONFIG_SH73A0)
 
 SCIF_FNS(SCSMR,  0x00, 16)
 SCIF_FNS(SCBRR,  0x04,  8)
@@ -692,7 +698,8 @@
 	defined(CONFIG_CPU_SH7721) || \
 	defined(CONFIG_ARCH_SH7367) || \
 	defined(CONFIG_ARCH_SH7377) || \
-	defined(CONFIG_ARCH_SH7372)
+	defined(CONFIG_ARCH_SH7372) || \
+	defined(CONFIG_SH73A0)
 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 #elif defined(CONFIG_CPU_SH7723) ||\
 	defined(CONFIG_CPU_SH7724)