dts: arm: socfpga: merge gen5 devicetrees from linux
Add -u-boot.dtsi files to keep the current U-Boot behaviour:
- add u-boot,dm-pre-reloc where required
- disable watchdog
- set uart clock frequency
- add gpio bank-name properties
where appropriate:
- make qspi work (add alias for spi0, fix compatible for flash)
- enable usb (status okay, add alias for udc0)
Adapt board dts files that are not in Linux to keep their old
behaviour.
Change licenses to SPDX.
(Patman warnings/errors are in 1:1 copied files from Linux)
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 9d8c4eb..2458d67 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Altera <www.altera.com>
+ * Copyright (C) 2012 Altera <www.altera.com>
*/
-#include "skeleton.dtsi"
#include <dt-bindings/reset/altr,rst-mgr.h>
/ {
@@ -11,34 +10,26 @@
#size-cells = <1>;
aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
serial0 = &uart0;
serial1 = &uart1;
timer0 = &timer0;
timer1 = &timer1;
timer2 = &timer2;
timer3 = &timer3;
- spi0 = &qspi;
- spi1 = &spi0;
- spi2 = &spi1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "altr,socfpga-smp";
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
@@ -46,6 +37,15 @@
};
};
+ pmu: pmu@ff111000 {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&intc>;
+ interrupts = <0 176 4>, <0 177 4>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ reg = <0xff111000 0x1000>,
+ <0xff113000 0x1000>;
+ };
+
intc: intc@fffed000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@@ -63,7 +63,7 @@
ranges;
amba {
- compatible = "arm,amba-bus";
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -87,6 +87,14 @@
};
};
+ base_fpga_region {
+ compatible = "fpga-region";
+ fpga-mgr = <&fpgamgr0>;
+
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ };
+
can0: can@ffc00000 {
compatible = "bosch,d_can";
reg = <0xffc00000 0x1000>;
@@ -131,7 +139,7 @@
compatible = "fixed-clock";
};
- main_pll: main_pll {
+ main_pll: main_pll@40 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -139,7 +147,7 @@
clocks = <&osc1>;
reg = <0x40>;
- mpuclk: mpuclk {
+ mpuclk: mpuclk@48 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
@@ -147,7 +155,7 @@
reg = <0x48>;
};
- mainclk: mainclk {
+ mainclk: mainclk@4c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
@@ -155,29 +163,29 @@
reg = <0x4C>;
};
- dbg_base_clk: dbg_base_clk {
+ dbg_base_clk: dbg_base_clk@50 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
+ clocks = <&main_pll>, <&osc1>;
div-reg = <0xe8 0 9>;
reg = <0x50>;
};
- main_qspi_clk: main_qspi_clk {
+ main_qspi_clk: main_qspi_clk@54 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
reg = <0x54>;
};
- main_nand_sdmmc_clk: main_nand_sdmmc_clk {
+ main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
reg = <0x58>;
};
- cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
+ cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
@@ -185,7 +193,7 @@
};
};
- periph_pll: periph_pll {
+ periph_pll: periph_pll@80 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -193,42 +201,42 @@
clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
reg = <0x80>;
- emac0_clk: emac0_clk {
+ emac0_clk: emac0_clk@88 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x88>;
};
- emac1_clk: emac1_clk {
+ emac1_clk: emac1_clk@8c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x8C>;
};
- per_qspi_clk: per_qsi_clk {
+ per_qspi_clk: per_qsi_clk@90 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x90>;
};
- per_nand_mmc_clk: per_nand_mmc_clk {
+ per_nand_mmc_clk: per_nand_mmc_clk@94 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x94>;
};
- per_base_clk: per_base_clk {
+ per_base_clk: per_base_clk@98 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x98>;
};
- h2f_usr1_clk: h2f_usr1_clk {
+ h2f_usr1_clk: h2f_usr1_clk@9c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
@@ -236,7 +244,7 @@
};
};
- sdram_pll: sdram_pll {
+ sdram_pll: sdram_pll@c0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -244,28 +252,28 @@
clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
reg = <0xC0>;
- ddr_dqs_clk: ddr_dqs_clk {
+ ddr_dqs_clk: ddr_dqs_clk@c8 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xC8>;
};
- ddr_2x_dqs_clk: ddr_2x_dqs_clk {
+ ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xCC>;
};
- ddr_dq_clk: ddr_dq_clk {
+ ddr_dq_clk: ddr_dq_clk@d0 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xD0>;
};
- h2f_usr2_clk: h2f_usr2_clk {
+ h2f_usr2_clk: h2f_usr2_clk@d4 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
@@ -312,7 +320,7 @@
l3_sp_clk: l3_sp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
+ clocks = <&l3_mp_clk>;
div-reg = <0x64 2 2>;
};
@@ -343,7 +351,7 @@
dbg_clk: dbg_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
+ clocks = <&dbg_at_clk>;
div-reg = <0x68 2 2>;
clk-gate = <0x60 5>;
};
@@ -446,6 +454,14 @@
clk-phase = <0 135>;
};
+ sdmmc_clk_divided: sdmmc_clk_divided {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&sdmmc_clk>;
+ clk-gate = <0xa0 8>;
+ fixed-divider = <4>;
+ };
+
nand_x_clk: nand_x_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
@@ -453,10 +469,17 @@
clk-gate = <0xa0 9>;
};
+ nand_ecc_clk: nand_ecc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&nand_x_clk>;
+ clk-gate = <0xa0 9>;
+ };
+
nand_clk: nand_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+ clocks = <&nand_x_clk>;
clk-gate = <0xa0 10>;
fixed-divider = <4>;
};
@@ -467,8 +490,58 @@
clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
clk-gate = <0xa0 11>;
};
+
+ ddr_dqs_clk_gate: ddr_dqs_clk_gate {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_dqs_clk>;
+ clk-gate = <0xd8 0>;
+ };
+
+ ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_2x_dqs_clk>;
+ clk-gate = <0xd8 1>;
+ };
+
+ ddr_dq_clk_gate: ddr_dq_clk_gate {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_dq_clk>;
+ clk-gate = <0xd8 2>;
+ };
+
+ h2f_user2_clk: h2f_user2_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&h2f_usr2_clk>;
+ clk-gate = <0xd8 3>;
+ };
+
};
- };
+ };
+
+ fpga_bridge0: fpga_bridge@ff400000 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ reg = <0xff400000 0x100000>;
+ resets = <&rst LWHPS2FPGA_RESET>;
+ clocks = <&l4_main_clk>;
+ };
+
+ fpga_bridge1: fpga_bridge@ff500000 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ reg = <0xff500000 0x10000>;
+ resets = <&rst HPS2FPGA_RESET>;
+ clocks = <&l4_main_clk>;
+ };
+
+ fpgamgr0: fpgamgr@ff706000 {
+ compatible = "altr,socfpga-fpga-mgr";
+ reg = <0xff706000 0x1000
+ 0xffb90000 0x4>;
+ interrupts = <0 175 4>;
+ };
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
@@ -477,12 +550,14 @@
interrupts = <0 115 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac0_clk>;
+ clocks = <&emac_0_clk>;
clock-names = "stmmaceth";
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <4096>;
status = "disabled";
};
@@ -493,60 +568,14 @@
interrupts = <0 120 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac1_clk>;
+ clocks = <&emac_1_clk>;
clock-names = "stmmaceth";
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
- status = "disabled";
- };
-
- i2c0: i2c@ffc04000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc04000 0x1000>;
- clocks = <&l4_sp_clk>;
- resets = <&rst I2C0_RESET>;
- reset-names = "i2c";
- interrupts = <0 158 0x4>;
- status = "disabled";
- };
-
- i2c1: i2c@ffc05000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc05000 0x1000>;
- clocks = <&l4_sp_clk>;
- resets = <&rst I2C1_RESET>;
- reset-names = "i2c";
- interrupts = <0 159 0x4>;
- status = "disabled";
- };
-
- i2c2: i2c@ffc06000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc06000 0x1000>;
- clocks = <&l4_sp_clk>;
- resets = <&rst I2C2_RESET>;
- reset-names = "i2c";
- interrupts = <0 160 0x4>;
- status = "disabled";
- };
-
- i2c3: i2c@ffc07000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc07000 0x1000>;
- clocks = <&l4_sp_clk>;
- resets = <&rst I2C3_RESET>;
- reset-names = "i2c";
- interrupts = <0 161 0x4>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <4096>;
status = "disabled";
};
@@ -555,12 +584,11 @@
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff708000 0x1000>;
- clocks = <&per_base_clk>;
+ clocks = <&l4_mp_clk>;
status = "disabled";
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
- bank-name = "porta";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
@@ -576,12 +604,11 @@
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff709000 0x1000>;
- clocks = <&per_base_clk>;
+ clocks = <&l4_mp_clk>;
status = "disabled";
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
- bank-name = "portb";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
@@ -597,12 +624,11 @@
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff70a000 0x1000>;
- clocks = <&per_base_clk>;
+ clocks = <&l4_mp_clk>;
status = "disabled";
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
- bank-name = "portc";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <27>;
@@ -613,15 +639,68 @@
};
};
- sdr: sdr@ffc25000 {
- compatible = "syscon";
- reg = <0xffc25000 0x1000>;
+ i2c0: i2c@ffc04000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc04000 0x1000>;
+ resets = <&rst I2C0_RESET>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 158 0x4>;
+ status = "disabled";
};
- sdramedac {
- compatible = "altr,sdram-edac";
- altr,sdr-syscon = <&sdr>;
- interrupts = <0 39 4>;
+ i2c1: i2c@ffc05000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc05000 0x1000>;
+ resets = <&rst I2C1_RESET>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 159 0x4>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ffc06000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc06000 0x1000>;
+ resets = <&rst I2C2_RESET>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 160 0x4>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ffc07000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc07000 0x1000>;
+ resets = <&rst I2C3_RESET>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 161 0x4>;
+ status = "disabled";
+ };
+
+ eccmgr: eccmgr {
+ compatible = "altr,socfpga-ecc-manager";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ l2-ecc@ffd08140 {
+ compatible = "altr,socfpga-l2-ecc";
+ reg = <0xffd08140 0x4>;
+ interrupts = <0 36 1>, <0 37 1>;
+ };
+
+ ocram-ecc@ffd08144 {
+ compatible = "altr,socfpga-ocram-ecc";
+ reg = <0xffd08144 0x4>;
+ iram = <&ocram>;
+ interrupts = <0 178 1>, <0 179 1>;
+ };
};
L2: l2-cache@fffef000 {
@@ -632,36 +711,89 @@
cache-level = <2>;
arm,tag-latency = <1 1 1>;
arm,data-latency = <2 1 1>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+ arm,shared-override;
+ arm,double-linefill = <1>;
+ arm,double-linefill-incr = <0>;
+ arm,double-linefill-wrap = <1>;
+ arm,prefetch-drop = <0>;
+ arm,prefetch-offset = <7>;
};
- mmc0: dwmmc0@ff704000 {
+ l3regs@0xff800000 {
+ compatible = "altr,l3regs", "syscon";
+ reg = <0xff800000 0x1000>;
+ };
+
+ mmc: dwmmc0@ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
interrupts = <0 139 4>;
fifo-depth = <0x400>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+ clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+
+ nand0: nand@ff900000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "altr,socfpga-denali-nand";
+ reg = <0xff900000 0x100000>,
+ <0xffb80000 0x10000>;
+ reg-names = "nand_data", "denali_reg";
+ interrupts = <0x0 0x90 0x4>;
+ dma-mask = <0xffffffff>;
+ clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
+ clock-names = "nand", "nand_x", "ecc";
+ status = "disabled";
+ };
+
+ ocram: sram@ffff0000 {
+ compatible = "mmio-sram";
+ reg = <0xffff0000 0x10000>;
};
qspi: spi@ff705000 {
compatible = "cdns,qspi-nor";
- #address-cells = <1>;
+ #address-cells = <1>;
#size-cells = <0>;
reg = <0xff705000 0x1000>,
- <0xffa00000 0x1000>;
+ <0xffa00000 0x1000>;
interrupts = <0 151 4>;
- clocks = <&qspi_clk>;
- ext-decoder = <0>; /* external decoder */
- num-cs = <4>;
cdns,fifo-depth = <128>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
- bus-num = <2>;
+ clocks = <&qspi_clk>;
status = "disabled";
};
+ rst: rstmgr@ffd05000 {
+ #reset-cells = <1>;
+ compatible = "altr,rst-mgr";
+ reg = <0xffd05000 0x1000>;
+ altr,modrst-offset = <0x10>;
+ };
+
+ scu: snoop-control-unit@fffec000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xfffec000 0x100>;
+ };
+
+ sdr: sdr@ffc25000 {
+ compatible = "altr,sdr-ctl", "syscon";
+ reg = <0xffc25000 0x1000>;
+ };
+
+ sdramedac {
+ compatible = "altr,sdram-edac";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <0 39 4>;
+ };
+
spi0: spi@fff00000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
@@ -669,10 +801,7 @@
reg = <0xfff00000 0x1000>;
interrupts = <0 154 4>;
num-cs = <4>;
- bus-num = <0>;
- tx-dma-channel = <&pdma 16>;
- rx-dma-channel = <&pdma 17>;
- clocks = <&per_base_clk>;
+ clocks = <&spi_m_clk>;
status = "disabled";
};
@@ -681,20 +810,22 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff01000 0x1000>;
- interrupts = <0 156 4>;
+ interrupts = <0 155 4>;
num-cs = <4>;
- bus-num = <1>;
- tx-dma-channel = <&pdma 20>;
- rx-dma-channel = <&pdma 21>;
- clocks = <&per_base_clk>;
+ clocks = <&spi_m_clk>;
status = "disabled";
};
+ sysmgr: sysmgr@ffd08000 {
+ compatible = "altr,sys-mgr", "syscon";
+ reg = <0xffd08000 0x4000>;
+ };
+
/* Local timer */
timer@fffec600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xfffec600 0x100>;
- interrupts = <1 13 0xf04>;
+ interrupts = <1 13 0xf01>;
clocks = <&mpu_periph_clk>;
};
@@ -704,6 +835,8 @@
reg = <0xffc08000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
+ resets = <&rst SPTIMER0_RESET>;
+ reset-names = "timer";
};
timer1: timer1@ffc09000 {
@@ -712,6 +845,8 @@
reg = <0xffc09000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
+ resets = <&rst SPTIMER1_RESET>;
+ reset-names = "timer";
};
timer2: timer2@ffd00000 {
@@ -720,6 +855,8 @@
reg = <0xffd00000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
+ resets = <&rst OSC1TIMER0_RESET>;
+ reset-names = "timer";
};
timer3: timer3@ffd01000 {
@@ -728,6 +865,8 @@
reg = <0xffd01000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
+ resets = <&rst OSC1TIMER1_RESET>;
+ reset-names = "timer";
};
uart0: serial0@ffc02000 {
@@ -737,7 +876,9 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
- clock-frequency = <100000000>;
+ dmas = <&pdma 28>,
+ <&pdma 29>;
+ dma-names = "tx", "rx";
};
uart1: serial1@ffc03000 {
@@ -747,16 +888,12 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
- clock-frequency = <100000000>;
+ dmas = <&pdma 30>,
+ <&pdma 31>;
+ dma-names = "tx", "rx";
};
- rst: rstmgr@ffd05000 {
- #reset-cells = <1>;
- compatible = "altr,rst-mgr";
- reg = <0xffd05000 0x1000>;
- };
-
- usbphy0: usbphy@0 {
+ usbphy0: usbphy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";
@@ -768,6 +905,8 @@
interrupts = <0 125 4>;
clocks = <&usb_mp_clk>;
clock-names = "otg";
+ resets = <&rst USB0_RESET>;
+ reset-names = "dwc2";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@@ -779,6 +918,8 @@
interrupts = <0 128 4>;
clocks = <&usb_mp_clk>;
clock-names = "otg";
+ resets = <&rst USB1_RESET>;
+ reset-names = "dwc2";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@@ -799,10 +940,5 @@
clocks = <&osc1>;
status = "disabled";
};
-
- sysmgr: sysmgr@ffd08000 {
- compatible = "altr,sys-mgr", "syscon";
- reg = <0xffd08000 0x4000>;
- };
};
};