rockchip: rk3066: add mk808_defconfig
This commit adds the default configuration file and
relevant description for a MK808 board.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
new file mode 100644
index 0000000..20bca75
--- /dev/null
+++ b/configs/mk808_defconfig
@@ -0,0 +1,102 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+# CONFIG_SPL_SYS_THUMB_BUILD is not set
+# CONFIG_TPL_SYS_THUMB_BUILD is not set
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x60408000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808"
+CONFIG_SPL_TEXT_BASE=0x60000000
+CONFIG_ROCKCHIP_RK3066=y
+# CONFIG_ROCKCHIP_STIMER is not set
+CONFIG_TPL_TEXT_BASE=0x10080C04
+CONFIG_TPL_MAX_SIZE=32764
+CONFIG_TPL_STACK=0x1008FFFF
+CONFIG_TARGET_MK808=y
+CONFIG_SPL_STACK_R_ADDR=0x70000000
+CONFIG_DEBUG_UART_BASE=0x20064000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SYS_LOAD_ADDR=0x70800800
+CONFIG_SPL_PAYLOAD="u-boot.bin"
+CONFIG_DEBUG_UART=y
+CONFIG_SD_BOOT=y
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="rk3066a-mk808.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2
+CONFIG_TPL_NEEDS_SEPARATE_STACK=y
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_DTB_PROPS_REMOVE=y
+CONFIG_SPL_OF_PLATDATA=y
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
+CONFIG_TPL_DM=y
+# CONFIG_DM_WARN is not set
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+# CONFIG_SIMPLE_BUS is not set
+# CONFIG_SPL_SIMPLE_BUS is not set
+# CONFIG_TPL_BLK is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+# CONFIG_SPL_DM_I2C is not set
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_TPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+# CONFIG_TPL_OF_LIBFDT is not set