ram: rockchip: Add rv1126 ddr3 support
Add DDR3 detection timings for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-528.inc b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-528.inc
new file mode 100644
index 0000000..9dbbb1a
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-528.inc
@@ -0,0 +1,72 @@
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xC,
+ .bk = 0x3,
+ .bw = 0x0,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x10,
+ .cs1_row = 0x10,
+ .cs0_high16bit_row = 0x10,
+ .cs1_high16bit_row = 0x10,
+ .ddrconfig = 0
+ },
+ {
+ {0x2c0f080e},
+ {0x0d030502},
+ {0x00000002},
+ {0x00001111},
+ {0x0000000c},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 528, /* clock rate(MHz) */
+ .dramtype = DDR3,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 0
+ },
+ {
+ {
+ {0x00000000, 0x43042001}, /* MSTR */
+ {0x00000064, 0x0040005d}, /* RFSHTMG */
+ {0x000000d0, 0x00020082}, /* INIT0 */
+ {0x000000d4, 0x00350000}, /* INIT1 */
+ {0x000000d8, 0x00000100}, /* INIT2 */
+ {0x000000dc, 0x09400000}, /* INIT3 */
+ {0x000000e0, 0x00080000}, /* INIT4 */
+ {0x000000e4, 0x00090000}, /* INIT5 */
+ {0x000000f4, 0x000f011f}, /* RANKCTL */
+ {0x00000100, 0x090e120a}, /* DRAMTMG0 */
+ {0x00000104, 0x0007020e}, /* DRAMTMG1 */
+ {0x00000108, 0x03040407}, /* DRAMTMG2 */
+ {0x0000010c, 0x00202006}, /* DRAMTMG3 */
+ {0x00000110, 0x04020305}, /* DRAMTMG4 */
+ {0x00000114, 0x03030302}, /* DRAMTMG5 */
+ {0x00000120, 0x00000904}, /* DRAMTMG8 */
+ {0x00000180, 0x00800020}, /* ZQCTL0 */
+ {0x00000184, 0x00000000}, /* ZQCTL1 */
+ {0x00000190, 0x07020001}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x06000608}, /* ODTCFG */
+ {0x00000244, 0x00000201}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008a}, /* PHYREG01 */
+ {0x00000014, 0x00000008}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000006}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},