Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi
This fixes the broken H5 Ethernet and updates the R40 and A64 DT files,
so nothing really critical.
diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
index 883f217..f7fe9fa 100644
--- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
@@ -36,18 +36,18 @@
leds {
compatible = "gpio-leds";
- pwr-led {
+ led-0 {
label = "bananapi-m64:red:pwr";
gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
default-state = "on";
};
- green {
+ led-1 {
label = "bananapi-m64:green:user";
gpios = <&pio 4 14 GPIO_ACTIVE_HIGH>; /* PE14 */
};
- blue {
+ led-2 {
label = "bananapi-m64:blue:user";
gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
};
@@ -105,7 +105,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <®_dc1sw>;
status = "okay";
@@ -331,10 +331,10 @@
"Microphone", "Microphone Jack",
"Microphone", "Onboard Microphone";
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right",
- "AIF1 Slot 0 Left ADC", "Left ADC",
- "AIF1 Slot 0 Right ADC", "Right ADC",
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
+ "ADCL", "Left ADC",
+ "ADCR", "Right ADC",
"Headphone Jack", "HP",
"MIC2", "Microphone Jack",
"Onboard Microphone", "MBIAS",
diff --git a/arch/arm/dts/sun50i-a64-nanopi-a64.dts b/arch/arm/dts/sun50i-a64-nanopi-a64.dts
index e58db8a..09b3c7f 100644
--- a/arch/arm/dts/sun50i-a64-nanopi-a64.dts
+++ b/arch/arm/dts/sun50i-a64-nanopi-a64.dts
@@ -35,7 +35,7 @@
leds {
compatible = "gpio-leds";
- blue {
+ led {
label = "nanopi-a64:blue:status";
gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
};
diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts
index fde9c7a..70e3174 100644
--- a/arch/arm/dts/sun50i-a64-orangepi-win.dts
+++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts
@@ -120,7 +120,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <®_gmac_3v3>;
status = "okay";
@@ -330,10 +330,10 @@
"Microphone", "Microphone Jack",
"Microphone", "Onboard Microphone";
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right",
- "AIF1 Slot 0 Left ADC", "Left ADC",
- "AIF1 Slot 0 Right ADC", "Right ADC",
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
+ "ADCL", "Left ADC",
+ "ADCR", "Right ADC",
"Headphone Jack", "HP",
"MIC2", "Microphone Jack",
"Onboard Microphone", "MBIAS",
diff --git a/arch/arm/dts/sun50i-a64-pine64-lts.dts b/arch/arm/dts/sun50i-a64-pine64-lts.dts
index 302e24b..596a259 100644
--- a/arch/arm/dts/sun50i-a64-pine64-lts.dts
+++ b/arch/arm/dts/sun50i-a64-pine64-lts.dts
@@ -1,10 +1,25 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2018 ARM Ltd.
+#include <dt-bindings/leds/common.h>
#include "sun50i-a64-sopine-baseboard.dts"
/ {
model = "Pine64 LTS";
compatible = "pine64,pine64-lts", "allwinner,sun50i-r18",
"allwinner,sun50i-a64";
+
+ leds {
+ compatible = "gpio-leds";
+
+ led {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ };
+ };
+};
+
+&mmc0 {
+ broken-cd; /* card detect is broken on *some* boards */
};
diff --git a/arch/arm/dts/sun50i-a64-pine64-plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts
index b26181c..b54099b 100644
--- a/arch/arm/dts/sun50i-a64-pine64-plus.dts
+++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts
@@ -13,7 +13,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-txid";
phy-handle = <&ext_rgmii_phy>;
status = "okay";
};
diff --git a/arch/arm/dts/sun50i-a64-pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts
index 2165f23..329cf27 100644
--- a/arch/arm/dts/sun50i-a64-pine64.dts
+++ b/arch/arm/dts/sun50i-a64-pine64.dts
@@ -261,11 +261,11 @@
simple-audio-card,widgets = "Microphone", "Microphone Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right",
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
"Headphone Jack", "HP",
- "AIF1 Slot 0 Left ADC", "Left ADC",
- "AIF1 Slot 0 Right ADC", "Right ADC",
+ "ADCL", "Left ADC",
+ "ADCR", "Right ADC",
"MIC2", "Microphone Jack";
status = "okay";
};
diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts
index 64b1c54..7ae1654 100644
--- a/arch/arm/dts/sun50i-a64-pinebook.dts
+++ b/arch/arm/dts/sun50i-a64-pinebook.dts
@@ -126,8 +126,6 @@
};
&ehci0 {
- phys = <&usbphy 0>;
- phy-names = "usb";
status = "okay";
};
@@ -169,6 +167,7 @@
pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
vmmc-supply = <®_dcdc1>;
vqmmc-supply = <®_eldo1>;
+ max-frequency = <200000000>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
@@ -177,8 +176,6 @@
};
&ohci0 {
- phys = <&usbphy 0>;
- phy-names = "usb";
status = "okay";
};
@@ -374,15 +371,15 @@
"Headphone", "Headphone Jack",
"Speaker", "Internal Speaker";
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right",
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
"Speaker Amp INL", "LINEOUT",
"Speaker Amp INR", "LINEOUT",
"Internal Speaker", "Speaker Amp OUTL",
"Internal Speaker", "Speaker Amp OUTR",
"Headphone Jack", "HP",
- "AIF1 Slot 0 Left ADC", "Left ADC",
- "AIF1 Slot 0 Right ADC", "Right ADC",
+ "ADCL", "Left ADC",
+ "ADCR", "Right ADC",
"Internal Microphone Left", "MBIAS",
"MIC1", "Internal Microphone Left",
"Internal Microphone Right", "HBIAS",
diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.0.dts b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts
index 0c42272..fb65319 100644
--- a/arch/arm/dts/sun50i-a64-pinephone-1.0.dts
+++ b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts
@@ -7,5 +7,10 @@
/ {
model = "Pine64 PinePhone Developer Batch (1.0)";
- compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64";
+ compatible = "pine64,pinephone-1.0", "pine64,pinephone", "allwinner,sun50i-a64";
+};
+
+&sgm3140 {
+ enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
};
diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.1.dts b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts
index 3e99a87..5e59d37 100644
--- a/arch/arm/dts/sun50i-a64-pinephone-1.1.dts
+++ b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts
@@ -7,7 +7,7 @@
/ {
model = "Pine64 PinePhone Braveheart (1.1)";
- compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64";
+ compatible = "pine64,pinephone-1.1", "pine64,pinephone", "allwinner,sun50i-a64";
};
&backlight {
@@ -28,3 +28,8 @@
num-interpolated-steps = <50>;
default-brightness-level = <400>;
};
+
+&sgm3140 {
+ enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+};
diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.2.dts b/arch/arm/dts/sun50i-a64-pinephone-1.2.dts
index a9f5b67..4e7e237 100644
--- a/arch/arm/dts/sun50i-a64-pinephone-1.2.dts
+++ b/arch/arm/dts/sun50i-a64-pinephone-1.2.dts
@@ -7,7 +7,12 @@
/ {
model = "Pine64 PinePhone (1.2)";
- compatible = "pine64,pinephone-1.2", "allwinner,sun50i-a64";
+ compatible = "pine64,pinephone-1.2", "pine64,pinephone", "allwinner,sun50i-a64";
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ };
};
&backlight {
@@ -38,3 +43,12 @@
interrupt-parent = <&pio>;
interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */
};
+
+&mmc1 {
+ mmc-pwrseq = <&wifi_pwrseq>;
+};
+
+&sgm3140 {
+ enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+};
diff --git a/arch/arm/dts/sun50i-a64-pinephone.dtsi b/arch/arm/dts/sun50i-a64-pinephone.dtsi
index 25150ab..9f69d48 100644
--- a/arch/arm/dts/sun50i-a64-pinephone.dtsi
+++ b/arch/arm/dts/sun50i-a64-pinephone.dtsi
@@ -13,6 +13,7 @@
/ {
aliases {
+ ethernet0 = &rtl8723cs;
serial0 = &uart0;
};
@@ -20,6 +21,7 @@
compatible = "pwm-backlight";
pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>;
enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+ power-supply = <®_ps>;
/* Backlight configuration differs per PinePhone revision. */
};
@@ -30,25 +32,51 @@
leds {
compatible = "gpio-leds";
- blue {
+ led-0 {
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_BLUE>;
gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
};
- green {
+ led-1 {
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
};
- red {
+ led-2 {
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_RED>;
gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
};
};
+ reg_ps: ps-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "ps";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+
+ reg_vbat_wifi: vbat-wifi {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vbat-wifi";
+ };
+
+ sgm3140: led-controller {
+ compatible = "sgmicro,sgm3140";
+ vin-supply = <®_dcdc1>;
+
+ sgm3140_flash: led {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ flash-max-timeout-us = <250000>;
+ };
+ };
+
speaker_amp: audio-amplifier {
compatible = "simple-audio-amplifier";
enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
@@ -142,15 +170,23 @@
status = "okay";
/* Magnetometer */
- lis3mdl: lis3mdl@1e {
+ lis3mdl: magnetometer@1e {
compatible = "st,lis3mdl-magn";
reg = <0x1e>;
vdd-supply = <®_dldo1>;
vddio-supply = <®_dldo1>;
};
+ /* Light/proximity sensor */
+ light-sensor@48 {
+ compatible = "sensortek,stk3311";
+ reg = <0x48>;
+ interrupt-parent = <&pio>;
+ interrupts = <1 0 IRQ_TYPE_EDGE_FALLING>; /* PB0 */
+ };
+
/* Accelerometer/gyroscope */
- mpu6050@68 {
+ accelerometer@68 {
compatible = "invensense,mpu6050";
reg = <0x68>;
interrupt-parent = <&pio>;
@@ -167,6 +203,7 @@
&lradc {
vref-supply = <®_aldo3>;
+ wakeup-source;
status = "okay";
button-200 {
@@ -195,6 +232,20 @@
status = "okay";
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <®_vbat_wifi>;
+ vqmmc-supply = <®_dldo4>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8723cs: wifi@1 {
+ reg = <1>;
+ };
+};
+
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
@@ -251,10 +302,6 @@
#include "axp803.dtsi"
-&ac_power_supply {
- status = "okay";
-};
-
&battery_power_supply {
status = "okay";
};
@@ -274,8 +321,8 @@
®_aldo3 {
regulator-always-on;
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pll-avcc";
};
@@ -392,10 +439,10 @@
"Internal Speaker", "Speaker Amp OUTR",
"Speaker Amp INL", "LINEOUT",
"Speaker Amp INR", "LINEOUT",
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right",
- "AIF1 Slot 0 Left ADC", "Left ADC",
- "AIF1 Slot 0 Right ADC", "Right ADC",
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
+ "ADCL", "Left ADC",
+ "ADCR", "Right ADC",
"Internal Microphone", "MBIAS",
"MIC1", "Internal Microphone",
"Headset Microphone", "HBIAS",
@@ -408,6 +455,19 @@
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723cs-bt";
+ device-wake-gpios = <&pio 7 6 GPIO_ACTIVE_LOW>; /* PH6 */
+ enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ host-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
+ };
+};
+
/* Connected to the modem (hardware flow control can't be used) */
&uart3 {
pinctrl-names = "default";
diff --git a/arch/arm/dts/sun50i-a64-pinetab-early-adopter.dts b/arch/arm/dts/sun50i-a64-pinetab-early-adopter.dts
new file mode 100644
index 0000000..6265360
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-pinetab-early-adopter.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Icenowy Zheng <icenowy@aosc.io>
+ *
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64-pinetab.dts"
+
+/ {
+ model = "PineTab, Early Adopter's version";
+ compatible = "pine64,pinetab-early-adopter", "allwinner,sun50i-a64";
+};
+
+&dsi {
+ /delete-node/ panel@0;
+
+ panel@0 {
+ compatible = "feixin,k101-im2byl02", "ilitek,ili9881c";
+ reg = <0>;
+ power-supply = <®_dc1sw>;
+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+ backlight = <&backlight>;
+ };
+};
diff --git a/arch/arm/dts/sun50i-a64-pinetab.dts b/arch/arm/dts/sun50i-a64-pinetab.dts
index dc4ab6b..422a850 100644
--- a/arch/arm/dts/sun50i-a64-pinetab.dts
+++ b/arch/arm/dts/sun50i-a64-pinetab.dts
@@ -14,7 +14,7 @@
#include <dt-bindings/pwm/pwm.h>
/ {
- model = "PineTab";
+ model = "PineTab, Development Sample";
compatible = "pine64,pinetab", "allwinner,sun50i-a64";
aliases {
@@ -122,9 +122,6 @@
status = "okay";
port {
- #address-cells = <1>;
- #size-cells = <0>;
-
csi_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
bus-width = <8>;
@@ -421,15 +418,15 @@
"Headphone", "Headphone Jack",
"Speaker", "Internal Speaker";
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right",
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
"Speaker Amp INL", "LINEOUT",
"Speaker Amp INR", "LINEOUT",
"Internal Speaker", "Speaker Amp OUTL",
"Internal Speaker", "Speaker Amp OUTR",
"Headphone Jack", "HP",
- "AIF1 Slot 0 Left ADC", "Left ADC",
- "AIF1 Slot 0 Right ADC", "Right ADC",
+ "ADCL", "Left ADC",
+ "ADCR", "Right ADC",
"Internal Microphone Left", "MBIAS",
"MIC1", "Internal Microphone Left",
"Internal Microphone Right", "HBIAS",
diff --git a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts
index 2f6ea9f..e22b94c 100644
--- a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts
@@ -79,7 +79,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <®_dc1sw>;
status = "okay";
@@ -111,6 +111,7 @@
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
status = "okay";
};
@@ -159,11 +160,11 @@
simple-audio-card,widgets = "Microphone", "Microphone Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right",
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
"Headphone Jack", "HP",
- "AIF1 Slot 0 Left ADC", "Left ADC",
- "AIF1 Slot 0 Right ADC", "Right ADC",
+ "ADCL", "Left ADC",
+ "ADCR", "Right ADC",
"MIC2", "Microphone Jack";
status = "okay";
};
diff --git a/arch/arm/dts/sun50i-a64-sopine.dtsi b/arch/arm/dts/sun50i-a64-sopine.dtsi
index c48692b..df62044 100644
--- a/arch/arm/dts/sun50i-a64-sopine.dtsi
+++ b/arch/arm/dts/sun50i-a64-sopine.dtsi
@@ -32,10 +32,9 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <®_dcdc1>;
- non-removable;
disable-wp;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 push-pull switch */
status = "okay";
};
diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts
index f5df5f7..f0a16f3 100644
--- a/arch/arm/dts/sun50i-a64-teres-i.dts
+++ b/arch/arm/dts/sun50i-a64-teres-i.dts
@@ -52,12 +52,12 @@
leds {
compatible = "gpio-leds";
- capslock {
+ led-0 {
label = "teres-i:green:capslock";
gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
};
- numlock {
+ led-1 {
label = "teres-i:green:numlock";
gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
};
@@ -340,10 +340,10 @@
"Microphone", "Internal Microphone",
"Speaker", "Internal Speaker";
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right",
- "AIF1 Slot 0 Left ADC", "Left ADC",
- "AIF1 Slot 0 Right ADC", "Right ADC",
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
+ "ADCL", "Left ADC",
+ "ADCR", "Right ADC",
"Headphone Jack", "HP",
"Speaker Amp INL", "LINEOUT",
"Speaker Amp INR", "LINEOUT",
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 8dfbcd1..57786fc 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -51,7 +51,7 @@
reg = <0>;
enable-method = "psci";
next-level-cache = <&L2>;
- clocks = <&ccu 21>;
+ clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
};
@@ -62,7 +62,7 @@
reg = <1>;
enable-method = "psci";
next-level-cache = <&L2>;
- clocks = <&ccu 21>;
+ clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
};
@@ -73,7 +73,7 @@
reg = <2>;
enable-method = "psci";
next-level-cache = <&L2>;
- clocks = <&ccu 21>;
+ clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
};
@@ -84,7 +84,7 @@
reg = <3>;
enable-method = "psci";
next-level-cache = <&L2>;
- clocks = <&ccu 21>;
+ clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
};
@@ -139,10 +139,10 @@
simple-audio-card,mclk-fs = <128>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right",
- "AIF1 Slot 0 Left ADC", "Left ADC",
- "AIF1 Slot 0 Right ADC", "Right ADC";
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
+ "ADCL", "Left ADC",
+ "ADCR", "Right ADC";
status = "disabled";
cpudai: simple-audio-card,cpu {
@@ -157,6 +157,7 @@
timer {
compatible = "arm,armv8-timer";
allwinner,erratum-unknown1;
+ arm,no-tick-in-suspend;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14
@@ -513,7 +514,7 @@
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- max-frequency = <200000000>;
+ max-frequency = <150000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -592,6 +593,8 @@
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>,
<&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
status = "disabled";
};
@@ -602,6 +605,8 @@
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
status = "disabled";
};
@@ -845,6 +850,20 @@
status = "disabled";
};
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-a64-i2s",
+ "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "rx", "tx";
+ dmas = <&dma 27>, <&dma 27>;
+ status = "disabled";
+ };
+
dai: dai@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-codec-i2s";
@@ -860,7 +879,8 @@
codec: codec@1c22e00 {
#sound-dai-cells = <0>;
- compatible = "allwinner,sun8i-a33-codec";
+ compatible = "allwinner,sun50i-a64-codec",
+ "allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x600>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
index c488aaa..a6a1087 100644
--- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -129,7 +129,7 @@
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy-handle = <&phy1>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-supply = <®_dc1sw>;
status = "okay";
};
@@ -164,6 +164,10 @@
#include "axp22x.dtsi"
+&ir0 {
+ status = "okay";
+};
+
&mmc0 {
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
@@ -201,10 +205,15 @@
&pio {
pinctrl-names = "default";
pinctrl-0 = <&clk_out_a_pin>;
+ vcc-pa-supply = <®_aldo2>;
+ vcc-pc-supply = <®_dcdc1>;
+ vcc-pd-supply = <®_dcdc1>;
+ vcc-pe-supply = <®_eldo1>;
+ vcc-pf-supply = <®_dcdc1>;
+ vcc-pg-supply = <®_dldo1>;
};
®_aldo2 {
- regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc-pa";
@@ -218,16 +227,16 @@
};
®_dc1sw {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-name = "vcc-gmac-phy";
};
®_dcdc1 {
regulator-always-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "vcc-3v0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
};
®_dcdc2 {
diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
index 06b6858..d5ad3b9 100644
--- a/arch/arm/dts/sun8i-r40.dtsi
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -44,8 +44,10 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
#include <dt-bindings/reset/sun8i-r40-ccu.h>
#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
#address-cells = <1>;
@@ -78,25 +80,25 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
@@ -109,6 +111,22 @@
status = "disabled";
};
+ thermal-zones {
+ cpu_thermal: cpu0-thermal {
+ /* milliseconds */
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 0>;
+ };
+
+ gpu_thermal: gpu-thermal {
+ /* milliseconds */
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 1>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -118,11 +136,11 @@
display_clocks: clock@1000000 {
compatible = "allwinner,sun8i-r40-de2-clk",
"allwinner,sun8i-h3-de2-clk";
- reg = <0x01000000 0x100000>;
- clocks = <&ccu CLK_DE>,
- <&ccu CLK_BUS_DE>;
- clock-names = "mod",
- "bus";
+ reg = <0x01000000 0x10000>;
+ clocks = <&ccu CLK_BUS_DE>,
+ <&ccu CLK_DE>;
+ clock-names = "bus",
+ "mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -172,6 +190,48 @@
};
};
+ deinterlace: deinterlace@1400000 {
+ compatible = "allwinner,sun8i-r40-deinterlace",
+ "allwinner,sun8i-h3-deinterlace";
+ reg = <0x01400000 0x20000>;
+ clocks = <&ccu CLK_BUS_DEINTERLACE>,
+ <&ccu CLK_DEINTERLACE>,
+ /*
+ * NOTE: Contrary to what datasheet claims,
+ * DRAM deinterlace gate doesn't exist and
+ * it's shared with CSI1.
+ */
+ <&ccu CLK_DRAM_CSI1>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_DEINTERLACE>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&mbus 9>;
+ interconnect-names = "dma-mem";
+ };
+
+ syscon: system-control@1c00000 {
+ compatible = "allwinner,sun8i-r40-system-control",
+ "allwinner,sun4i-a10-system-control";
+ reg = <0x01c00000 0x30>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram@1d00000 {
+ compatible = "mmio-sram";
+ reg = <0x01d00000 0xd0000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x01d00000 0xd0000>;
+
+ ve_sram: sram-section@0 {
+ compatible = "allwinner,sun8i-r40-sram-c1",
+ "allwinner,sun4i-a10-sram-c1";
+ reg = <0x000000 0x80000>;
+ };
+ };
+ };
+
nmi_intc: interrupt-controller@1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
@@ -180,6 +240,69 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
+ dma: dma-controller@1c02000 {
+ compatible = "allwinner,sun8i-r40-dma",
+ "allwinner,sun50i-a64-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>;
+ dma-channels = <16>;
+ dma-requests = <31>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
+ spi0: spi@1c05000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@1c06000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ csi0: csi@1c09000 {
+ compatible = "allwinner,sun8i-r40-csi0",
+ "allwinner,sun7i-a20-csi0";
+ reg = <0x01c09000 0x1000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI0>;
+ clock-names = "bus", "isp", "ram";
+ resets = <&ccu RST_BUS_CSI0>;
+ interconnects = <&mbus 5>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+ };
+
+ video-codec@1c0e000 {
+ compatible = "allwinner,sun8i-r40-video-engine";
+ reg = <0x01c0e000 0x1000>;
+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+ <&ccu CLK_DRAM_VE>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_BUS_VE>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ allwinner,sram = <&ve_sram 1>;
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun8i-r40-mmc",
"allwinner,sun50i-a64-mmc";
@@ -266,6 +389,38 @@
#phy-cells = <1>;
};
+ crypto: crypto@1c15000 {
+ compatible = "allwinner,sun8i-r40-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_CE>;
+ };
+
+ spi2: spi@1c17000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c17000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ahci: sata@1c18000 {
+ compatible = "allwinner,sun8i-r40-ahci";
+ reg = <0x01c18000 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
+ resets = <&ccu RST_BUS_SATA>;
+ reset-names = "ahci";
+ status = "disabled";
+ };
+
ehci1: usb@1c19000 {
compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
reg = <0x01c19000 0x100>;
@@ -312,6 +467,19 @@
status = "disabled";
};
+ spi3: spi@1c1f000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c1f000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c20000 0x400>;
@@ -322,8 +490,7 @@
};
rtc: rtc@1c20400 {
- compatible = "allwinner,sun8i-r40-rtc",
- "allwinner,sun8i-h3-rtc";
+ compatible = "allwinner,sun8i-r40-rtc";
reg = <0x01c20400 0x400>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "osc32k", "osc32k-out";
@@ -347,6 +514,20 @@
function = "clk_out_a";
};
+ /omit-if-no-ref/
+ csi0_8bits_pins: csi0-8bits-pins {
+ pins = "PE0", "PE2", "PE3", "PE4", "PE5",
+ "PE6", "PE7", "PE8", "PE9", "PE10",
+ "PE11";
+ function = "csi0";
+ };
+
+ /omit-if-no-ref/
+ csi0_mclk_pin: csi0-mclk-pin {
+ pins = "PE1";
+ function = "csi0";
+ };
+
gmac_rgmii_pins: gmac-rgmii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
@@ -365,6 +546,36 @@
function = "i2c0";
};
+ i2c1_pins: i2c1-pins {
+ pins = "PB18", "PB19";
+ function = "i2c1";
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins = "PB20", "PB21";
+ function = "i2c2";
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins = "PI0", "PI1";
+ function = "i2c3";
+ };
+
+ i2c4_pins: i2c4-pins {
+ pins = "PI2", "PI3";
+ function = "i2c4";
+ };
+
+ ir0_pins: ir0-pins {
+ pins = "PB4";
+ function = "ir0";
+ };
+
+ ir1_pins: ir1-pins {
+ pins = "PB23";
+ function = "ir1";
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
@@ -390,6 +601,36 @@
bias-pull-up;
};
+ /omit-if-no-ref/
+ spi0_pc_pins: spi0-pc-pins {
+ pins = "PC0", "PC1", "PC2";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi0_cs0_pc_pin: spi0-cs0-pc-pin {
+ pins = "PC23";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi1_pi_pins: spi1-pi-pins {
+ pins = "PI17", "PI18", "PI19";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
+ spi1_cs0_pi_pin: spi1-cs0-pi-pin {
+ pins = "PI16";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
+ spi1_cs1_pi_pin: spi1-cs1-pi-pin {
+ pins = "PI15";
+ function = "spi1";
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB22", "PB23";
function = "uart0";
@@ -409,6 +650,45 @@
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ ir0: ir@1c21800 {
+ compatible = "allwinner,sun8i-r40-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x01c21800 0x400>;
+ pinctrl-0 = <&ir0_pins>;
+ pinctrl-names = "default";
+ clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
+ clock-names = "apb", "ir";
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_IR0>;
+ status = "disabled";
+ };
+
+ ir1: ir@1c21c00 {
+ compatible = "allwinner,sun8i-r40-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x01c21c00 0x400>;
+ pinctrl-0 = <&ir1_pins>;
+ pinctrl-names = "default";
+ clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
+ clock-names = "apb", "ir";
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_IR1>;
+ status = "disabled";
+ };
+
+ ths: thermal-sensor@1c24c00 {
+ compatible = "allwinner,sun8i-r40-ths";
+ reg = <0x01c24c00 0x100>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "bus", "mod";
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_THS>;
+ /* TODO: add nvmem-cells for calibration */
+ #thermal-sensor-cells = <1>;
};
uart0: serial@1c28000 {
@@ -518,6 +798,8 @@
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -529,6 +811,8 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -540,6 +824,8 @@
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
resets = <&ccu RST_BUS_I2C3>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -551,22 +837,33 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C4>;
resets = <&ccu RST_BUS_I2C4>;
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- ahci: sata@1c18000 {
- compatible = "allwinner,sun8i-r40-ahci";
- reg = <0x01c18000 0x1000>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
- resets = <&ccu RST_BUS_SATA>;
- resets-name = "ahci";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
+ mali: gpu@1c40000 {
+ compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
};
gmac: ethernet@1c50000 {
@@ -588,6 +885,16 @@
};
};
+ mbus: dram-controller@1c62000 {
+ compatible = "allwinner,sun8i-r40-mbus";
+ reg = <0x01c62000 0x1000>;
+ clocks = <&ccu 155>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x00000000 0x40000000 0x80000000>;
+ #interconnect-cells = <1>;
+ };
+
tcon_top: tcon-top@1c70000 {
compatible = "allwinner,sun8i-r40-tcon-top";
reg = <0x01c70000 0x1000>;
@@ -614,12 +921,9 @@
#size-cells = <0>;
tcon_top_mixer0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- tcon_top_mixer0_in_mixer0: endpoint@0 {
- reg = <0>;
+ tcon_top_mixer0_in_mixer0: endpoint {
remote-endpoint = <&mixer0_out_tcon_top>;
};
};
@@ -713,7 +1017,7 @@
compatible = "allwinner,sun8i-r40-tcon-tv";
reg = <0x01c73000 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
+ clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON_TV0>;
reset-names = "lcd";
@@ -756,7 +1060,7 @@
compatible = "allwinner,sun8i-r40-tcon-tv";
reg = <0x01c74000 0x1000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
+ clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON_TV1>;
reset-names = "lcd";
@@ -798,7 +1102,7 @@
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
@@ -818,7 +1122,7 @@
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
- phy-names = "hdmi-phy";
+ phy-names = "phy";
status = "disabled";
ports {
@@ -843,7 +1147,7 @@
compatible = "allwinner,sun8i-r40-hdmi-phy";
reg = <0x01ef0000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
- <&ccu 7>, <&ccu 16>;
+ <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
clock-names = "bus", "mod", "pll-0", "pll-1";
resets = <&ccu RST_BUS_HDMI0>;
reset-names = "phy";
@@ -851,6 +1155,15 @@
};
};
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
index 15c22b0..4795455 100644
--- a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -120,7 +120,7 @@
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy-handle = <&phy1>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-supply = <®_dc1sw>;
status = "okay";
};
@@ -198,16 +198,16 @@
};
®_dc1sw {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-name = "vcc-gmac-phy";
};
®_dcdc1 {
regulator-always-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "vcc-3v0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
};
®_dcdc2 {
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index a6cdda8..5a1b38b 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -554,7 +554,7 @@
* The GPIO pinmux value is an integration choice, so depends on the
* SoC, not the EMAC variant.
*/
- if (IS_ENABLED(CONFIG_MACH_SUN8I_H3))
+ if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
iomux = SUN8I_IOMUX_H3;
else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
iomux = SUN8I_IOMUX_R40;
@@ -562,8 +562,12 @@
iomux = SUN8I_IOMUX_H6;
else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
iomux = SUN8I_IOMUX_H616;
- else
+ else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T))
iomux = SUN8I_IOMUX;
+ else if (IS_ENABLED(CONFIG_MACH_SUN50I))
+ iomux = SUN8I_IOMUX;
+ else
+ BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
for (i = 0; ; i++) {
int pin;
diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h
index 4fa5f69..d7337b5 100644
--- a/include/dt-bindings/clock/sun8i-r40-ccu.h
+++ b/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -43,6 +43,10 @@
#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
#define _DT_BINDINGS_CLK_SUN8I_R40_H_
+#define CLK_PLL_VIDEO0 7
+
+#define CLK_PLL_VIDEO1 16
+
#define CLK_CPU 24
#define CLK_BUS_MIPI_DSI 29
@@ -172,7 +176,7 @@
#define CLK_AVS 152
#define CLK_HDMI 153
#define CLK_HDMI_SLOW 154
-
+#define CLK_MBUS 155
#define CLK_DSI_DPHY 156
#define CLK_TVE0 157
#define CLK_TVE1 158
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
index 1ea1b70..35b6f69 100644
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ b/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* This header provides constants for the ARM GIC.
*/
@@ -7,14 +8,14 @@
#include <dt-bindings/interrupt-controller/irq.h>
-/* interrupt specific cell 0 */
+/* interrupt specifier cell 0 */
#define GIC_SPI 0
#define GIC_PPI 1
/*
* Interrupt specifier cell 2.
- * The flaggs in irq.h are valid, plus those below.
+ * The flags in irq.h are valid, plus those below.
*/
#define GIC_CPU_MASK_RAW(x) ((x) << 8)
#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h
index b5e6b00..bc7babb 100644
--- a/include/dt-bindings/thermal/thermal.h
+++ b/include/dt-bindings/thermal/thermal.h
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This header provides constants for most thermal bindings.
*
* Copyright (C) 2013 Texas Instruments
* Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * GPLv2 only
*/
#ifndef _DT_BINDINGS_THERMAL_THERMAL_H