| commit | d0edce4fa394325a0ccfd38a5d668fb5ee1af34d | [log] [tgz] |
|---|---|---|
| author | Tom Warren <twarren@nvidia.com> | Mon Mar 25 16:22:26 2013 -0700 |
| committer | Tom Warren <twarren@nvidia.com> | Mon Apr 15 11:01:38 2013 -0700 |
| tree | 5a7ea0c182d9b2c33699fcfff230f83ba7b4ff84 | |
| parent | 85434f9d7123c283b2233614178e7cfc968d329b [diff] |
Tegra: Configure L2 cache control reg properly. Without this change, kernel fails at calling function cache_clean_flush during kernel early boot. Aprocryphally, intended for T114 only, so I check for a T114 SoC. Works (i.e. dalmore 3.8 kernel now starts printing to console). Signed-off-by: Tom Warren <twarren@nvidia.com>