net: gmac_rockchip: Add support for the RK3228 GMAC
The GMAC in the RK3228 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3368-specific logic necessary to reuse this driver.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 551c230..683e820 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -15,6 +15,7 @@
#include <asm/arch/periph.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk322x.h>
#include <asm/arch/grf_rk3288.h>
#include <asm/arch/grf_rk3328.h>
#include <asm/arch/grf_rk3368.h>
@@ -69,6 +70,39 @@
return designware_eth_ofdata_to_platdata(dev);
}
+static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk322x_grf *grf;
+ int clk;
+ enum {
+ RK3228_GMAC_CLK_SEL_SHIFT = 8,
+ RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
+ RK3228_GMAC_CLK_SEL_125M = 0 << 8,
+ RK3228_GMAC_CLK_SEL_25M = 3 << 8,
+ RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3228_GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = RK3228_GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = RK3228_GMAC_CLK_SEL_125M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
+
+ return 0;
+}
+
static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
struct rk3288_grf *grf;
@@ -221,6 +255,50 @@
return 0;
}
+static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk322x_grf *grf;
+ enum {
+ RK3228_RMII_MODE_SHIFT = 10,
+ RK3228_RMII_MODE_MASK = BIT(10),
+
+ RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
+ RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+ RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+ RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+ RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+ RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+ };
+ enum {
+ RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+ RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1],
+ RK3228_RMII_MODE_MASK |
+ RK3228_GMAC_PHY_INTF_SEL_MASK |
+ RK3228_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3228_TXCLK_DLY_ENA_GMAC_MASK,
+ RK3228_GMAC_PHY_INTF_SEL_RGMII |
+ RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
+ RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+ rk_clrsetreg(&grf->mac_con[0],
+ RK3228_CLK_RX_DL_CFG_GMAC_MASK |
+ RK3228_CLK_TX_DL_CFG_GMAC_MASK,
+ pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
+ pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3288_grf *grf;
@@ -448,6 +526,11 @@
.write_hwaddr = designware_eth_write_hwaddr,
};
+const struct rk_gmac_ops rk3228_gmac_ops = {
+ .fix_mac_speed = rk3228_gmac_fix_mac_speed,
+ .set_to_rgmii = rk3228_gmac_set_to_rgmii,
+};
+
const struct rk_gmac_ops rk3288_gmac_ops = {
.fix_mac_speed = rk3288_gmac_fix_mac_speed,
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
@@ -474,6 +557,8 @@
};
static const struct udevice_id rockchip_gmac_ids[] = {
+ { .compatible = "rockchip,rk3228-gmac",
+ .data = (ulong)&rk3228_gmac_ops },
{ .compatible = "rockchip,rk3288-gmac",
.data = (ulong)&rk3288_gmac_ops },
{ .compatible = "rockchip,rk3328-gmac",