commit d18d06ac35229345a0af80977a408cfbe1d1015b
author Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Tue Aug 27 10:13:51 2019 +0000
committer Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Wed Aug 28 13:47:44 2019 +0530
tree 3c9093a90c7db01f1bd92ee38eaf3eb7755185d3
parent adc983b4d676e4ca958067f86bec1bb02cb17950

dm: pcie_fsl: Fix the Class Code fixup function

The Class Code fixup method was changed from PCIe block
revision 3.0, the current fixup is only valid for the
revision 3.0 and the later ones.

So add the Class Code fixup for the block revision < 3.0.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

drivers/pci/pcie_fsl.c

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 1879d81..1be5063 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -503,14 +503,23 @@
 static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
 {
 	ccsr_fsl_pci_t *regs = pcie->regs;
+	u32 classcode_reg;
 	u32 val;
 
-	setbits_be32(&regs->dbi_ro_wr_en, 0x01);
-	fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val);
+	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+		classcode_reg = PCI_CLASS_REVISION;
+		setbits_be32(&regs->dbi_ro_wr_en, 0x01);
+	} else {
+		classcode_reg = CSR_CLASSCODE;
+	}
+
+	fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
 	val &= 0xff;
 	val |= PCI_CLASS_BRIDGE_PCI << 16;
-	fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);
-	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
+	fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
+
+	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
+		clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
 
 	return 0;
 }