ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index c0a5824..1f75137 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -50,12 +50,12 @@
/*
* Read PLL Mode register
*/
- pllmr = mfdcr (pllmd);
+ pllmr = mfdcr (CPC0_PLLMR);
/*
* Read Pin Strapping register
*/
- psr = mfdcr (strap);
+ psr = mfdcr (CPC0_PSR);
/*
* Determine FWD_DIV.
@@ -280,8 +280,8 @@
unsigned long plbedv0;
/* Extract configured divisors */
- mfsdr(sdr_sdstp0, strp0);
- mfsdr(sdr_sdstp1, strp1);
+ mfsdr(SDR0_SDSTP0, strp0);
+ mfsdr(SDR0_SDSTP1, strp1);
temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4);
sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
@@ -342,7 +342,7 @@
*/
/* Decode CPR0_PLLD0 for divisors */
- mfcpr(clk_plld, reg);
+ mfcpr(CPR0_PLLD, reg);
temp = (reg & PLLD_FWDVA_MASK) >> 16;
sysInfo->pllFwdDivA = temp ? temp : 16;
temp = (reg & PLLD_FWDVB_MASK) >> 8;
@@ -351,28 +351,28 @@
sysInfo->pllFbkDiv = temp ? temp : 32;
lfdiv = reg & PLLD_LFBDV_MASK;
- mfcpr(clk_opbd, reg);
+ mfcpr(CPR0_OPBD, reg);
temp = (reg & OPBDDV_MASK) >> 24;
sysInfo->pllOpbDiv = temp ? temp : 4;
- mfcpr(clk_perd, reg);
+ mfcpr(CPR0_PERD, reg);
temp = (reg & PERDV_MASK) >> 24;
sysInfo->pllExtBusDiv = temp ? temp : 8;
- mfcpr(clk_primbd, reg);
+ mfcpr(CPR0_PRIMBD, reg);
temp = (reg & PRBDV_MASK) >> 24;
prbdv0 = temp ? temp : 8;
- mfcpr(clk_spcid, reg);
+ mfcpr(CPR0_SPCID, reg);
temp = (reg & SPCID_MASK) >> 24;
sysInfo->pllPciDiv = temp ? temp : 4;
/* Calculate 'M' based on feedback source */
- mfsdr(sdr_sdstp0, reg);
+ mfsdr(SDR0_SDSTP0, reg);
temp = (reg & PLLSYS0_SEL_MASK) >> 27;
if (temp == 0) { /* PLL output */
/* Figure which pll to use */
- mfcpr(clk_pllc, reg);
+ mfcpr(CPR0_PLLC, reg);
temp = (reg & PLLC_SRC_MASK) >> 29;
if (!temp) /* PLLOUTA */
m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
@@ -426,7 +426,7 @@
unsigned long m;
/* Extract configured divisors */
- strp0 = mfdcr( cpc0_strp0 );
+ strp0 = mfdcr( CPC0_STRP0 );
sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
@@ -484,8 +484,8 @@
#endif
/* Extract configured divisors */
- mfsdr( sdr_sdstp0,strp0 );
- mfsdr( sdr_sdstp1,strp1 );
+ mfsdr( SDR0_SDSTP0,strp0 );
+ mfsdr( SDR0_SDSTP1,strp1 );
temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
sysInfo->pllFwdDivA = temp ? temp : 16 ;
@@ -531,7 +531,7 @@
/* Determine PCI Clock Period */
pci_clock_per = determine_pci_clock_per();
sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
- mfsdr(sdr_ddr0, sdr_ddrpll);
+ mfsdr(SDR0_DDR0, sdr_ddrpll);
sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
#endif
@@ -794,8 +794,8 @@
/*
* Read PLL Mode registers
*/
- pllmr0 = mfdcr (cpc0_pllmr0);
- pllmr1 = mfdcr (cpc0_pllmr1);
+ pllmr0 = mfdcr (CPC0_PLLMR0);
+ pllmr1 = mfdcr (CPC0_PLLMR1);
/*
* Determine forward divider A
@@ -918,8 +918,8 @@
/*
* Read PLL Mode registers
*/
- mfcpr(cprplld, cpr_plld);
- mfcpr(cprpllc, cpr_pllc);
+ mfcpr(CPR0_PLLD, cpr_plld);
+ mfcpr(CPR0_PLLC, cpr_pllc);
/*
* Determine forward divider A
@@ -943,7 +943,7 @@
/*
* Read CPR_PRIMAD register
*/
- mfcpr(cprprimad, cpr_primad);
+ mfcpr(CPC0_PRIMAD, cpr_primad);
/*
* Determine PLB_DIV.
@@ -1074,7 +1074,7 @@
};
unsigned char sel, cpudv0, plb2xDiv;
- mfcpr(cpr0_plld, tmp);
+ mfcpr(CPR0_PLLD, tmp);
/*
* Determine forward divider A
@@ -1094,29 +1094,29 @@
/*
* Determine PERDV0
*/
- mfcpr(cpr0_perd, tmp);
+ mfcpr(CPR0_PERD, tmp);
tmp = (tmp >> 24) & 0x03;
sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp;
/*
* Determine OPBDV0
*/
- mfcpr(cpr0_opbd, tmp);
+ mfcpr(CPR0_OPBD, tmp);
tmp = (tmp >> 24) & 0x03;
sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp;
/* Determine PLB2XDV0 */
- mfcpr(cpr0_plbd, tmp);
+ mfcpr(CPR0_PLBD, tmp);
tmp = (tmp >> 16) & 0x07;
plb2xDiv = (tmp == 0) ? 8 : tmp;
/* Determine CPUDV0 */
- mfcpr(cpr0_cpud, tmp);
+ mfcpr(CPR0_CPUD, tmp);
tmp = (tmp >> 24) & 0x07;
cpudv0 = (tmp == 0) ? 8 : tmp;
/* Determine SEL(5:7) in CPR0_PLLC */
- mfcpr(cpr0_pllc, tmp);
+ mfcpr(CPR0_PLLC, tmp);
sel = (tmp >> 24) & 0x07;
/*