OMAP3: igep00x0: add SPL support for IGEP-based boards
This patch adds SPL support for IGEP-based boards.
Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
index 971e31b..a4d099a 100644
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep0020/igep0020.c
@@ -58,6 +58,46 @@
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: omap_rev_string
+ * Description: For SPL builds output board rev
+ */
+void omap_rev_string(void)
+{
+}
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
+ u32 *mr)
+{
+ *mr = MICRON_V_MR_165;
+#ifdef CONFIG_BOOT_NAND
+ *mcfg = MICRON_V_MCFG_200(512 << 20);
+ *ctrla = MICRON_V_ACTIMA_200;
+ *ctrlb = MICRON_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+#else
+ if (get_cpu_family() == CPU_OMAP34XX) {
+ *mcfg = NUMONYX_V_MCFG_165(512 << 20);
+ *ctrla = NUMONYX_V_ACTIMA_165;
+ *ctrlb = NUMONYX_V_ACTIMB_165;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+ } else {
+ *mcfg = NUMONYX_V_MCFG_200(512 << 20);
+ *ctrla = NUMONYX_V_ACTIMA_200;
+ *ctrlb = NUMONYX_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ }
+#endif
+}
+#endif
+
/*
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
@@ -91,7 +131,7 @@
}
#endif
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0, 0, 0);