imx: use generic name ele(EdgeLockSecure Enclave)
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 50b097b..cfc09e7 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/mu_hal.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
#include <asm/arch/rdc.h>
#include <div64.h>
@@ -203,12 +203,12 @@
int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x27020000UL;
- struct sentinel_msg msg;
+ struct ele_msg msg;
int ret;
u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
- msg.version = AHAB_VERSION;
- msg.tag = AHAB_CMD_TAG;
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
msg.size = 2;
msg.command = ELE_RELEASE_RDC_REQ;
msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
@@ -266,7 +266,7 @@
mrgd[4] |= ((access & 0xFFF) << 16);
}
- /* not handle other cases, since S400 only set ACCESS1 and 2 */
+ /* not handle other cases, since ELE only set ACCESS1 and 2 */
writel(mrgd[4], xrdc_base + off + 0x10);
return;
}
@@ -295,7 +295,7 @@
void xrdc_init_mrc(void)
{
- /* Re-config MRC3 for SRAM0 in case protected by S400 */
+ /* Re-config MRC3 for SRAM0 in case protected by ELE */
xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000);
xrdc_config_mrc_dx_perm(3, 0, 0, 1);
xrdc_config_mrc_dx_perm(3, 0, 1, 1);
@@ -320,7 +320,7 @@
xrdc_config_mrc_dx_perm(5, 0, 1, 1);
xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
- /* Set MRC6 for DDR access from Sentinel */
+ /* Set MRC6 for DDR access from ELE */
xrdc_config_mrc_w0_w1(6, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
xrdc_config_mrc_dx_perm(6, 0, 4, 1);
xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
@@ -404,7 +404,7 @@
val &= ~(0xFU << offset);
/* MBC0-3
- * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+ * Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
* So select MBC0_MEMN_GLBAC0
*/
if (sec_access) {
@@ -445,7 +445,7 @@
continue;
/* MRC0,1
- * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+ * Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
* So select MRCx_MEMN_GLBAC0
*/
if (sec_access) {
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 81eae02..e23cf60 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -14,7 +14,7 @@
#include <event.h>
#include <spl.h>
#include <asm/arch/rdc.h>
-#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/mu_hal.h>
#include <cpu_func.h>
#include <asm/setup.h>
@@ -70,7 +70,7 @@
}
#endif
-static void set_cpu_info(struct sentinel_get_info_data *info)
+static void set_cpu_info(struct ele_get_info_data *info)
{
gd->arch.soc_rev = info->soc;
gd->arch.lifecycle = info->lc;
@@ -582,9 +582,9 @@
u32 res;
int ret;
- ret = ahab_read_common_fuse(1, uid, 4, &res);
+ ret = ele_read_common_fuse(1, uid, 4, &res);
if (ret)
- printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+ printf("ele read fuse failed %d, 0x%x\n", ret, res);
else
printf("UID 0x%x,0x%x,0x%x,0x%x\n", uid[0], uid[1], uid[2], uid[3]);
@@ -783,7 +783,7 @@
struct udevice *devp;
int ret;
u32 res;
- struct sentinel_get_info_data *info = (struct sentinel_get_info_data *)SRAM0_BASE;
+ struct ele_get_info_data *info = (struct ele_get_info_data *)SRAM0_BASE;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8ulp_mu), &devp);
if (ret) {
@@ -791,11 +791,11 @@
return ret;
}
- ret = ahab_get_info(info, &res);
+ ret = ele_get_info(info, &res);
if (ret) {
- printf("ahab_get_info failed %d\n", ret);
+ printf("ele_get_info failed %d\n", ret);
/* fallback to A0.1 revision */
- memset((void *)info, 0, sizeof(struct sentinel_get_info_data));
+ memset((void *)info, 0, sizeof(struct ele_get_info_data));
info->soc = 0xa000084d;
}
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
index fcb02ed..b471a75 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
@@ -217,8 +217,8 @@
* CM33 Cache
* PowerQuad RAM
* ETF RAM
- * Sentinel PKC, Data RAM1, Inst RAM0/1
- * Sentinel ROM
+ * ELE PKC, Data RAM1, Inst RAM0/1
+ * ELE ROM
* uPower IRAM/DRAM
* uPower ROM
* CM33 ROM
@@ -230,7 +230,7 @@
* SSRAM Partition 7_a(128KB)
* SSRAM Partition 7_b(64KB)
* SSRAM Partition 7_c(64KB)
- * Sentinel Data RAM0, Inst RAM2
+ * ELE Data RAM0, Inst RAM2
*/
/* MIPI-CSI FIFO BIT28 not set */
memon = 0x3FFFFFEFFFFFFCUL;