* Cleanup lowboot code for MPC5200
* Minor code cleanup (coding style)
* Patch by Reinhard Meyer, 30 Dec 2003:
- cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
- added CONFIG_PHY_ADDR to include/configs/IceCube.h,
- turned debug print of PHY registers into a function (called in two places)
- added support for EMK MPC5200 based modules
* Fix MPC8xx PLPRCR_MFD_SHIFT typo
* Add support for TQM866M modules
* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)
* Fix a few compiler warnings
diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c
index a974e23..b8a3595 100644
--- a/board/tqm8xx/flash.c
+++ b/board/tqm8xx/flash.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -21,7 +21,9 @@
* MA 02111-1307 USA
*/
-/* #define DEBUG */
+#if 0
+#define DEBUG
+#endif
#include <common.h>
#include <mpc8xx.h>
@@ -214,6 +216,8 @@
break;
case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
break;
+ case FLASH_AMLV320B: printf ("AM29LV320MB (32Mbit, bottom boot sect)\n");
+ break;
# else /* ! TQM8xxM */
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
@@ -232,6 +236,8 @@
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
+ case FLASH_AMDL163B: printf ("AM29DL163B (16 Mbit, bottom boot sect)\n");
+ break;
default: printf ("Unknown Chip Type\n");
break;
}
@@ -280,12 +286,15 @@
switch (value) {
case AMD_MANUFACT:
+ debug ("Manufacturer: AMD\n");
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
+ debug ("Manufacturer: FUJITSU\n");
info->flash_id = FLASH_MAN_FUJ;
break;
default:
+ debug ("Manufacturer: *** unknown ***\n");
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
@@ -299,36 +308,53 @@
switch (value) {
#ifdef CONFIG_TQM8xxM /* mirror bit flash */
case AMD_ID_MIRROR:
+ debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
+ addr[14], addr[15]);
/* Special case for AMLV320MH/L */
if ((addr[14] & 0x00ff00ff) == 0x001d001d &&
- (addr[15] & 0x00ff00ff) == 0x00000000) {
+ (addr[15] & 0x00ff00ff) == 0x00000000) {
+ debug ("Chip: AMLV320MH/L\n");
info->flash_id += FLASH_AMLV320U;
info->sector_count = 64;
- info->size = 0x00800000; /* => 8 MB */
+ info->size = 0x00800000; /* => 8 MB */
break;
}
switch(addr[14]) {
case AMD_ID_LV128U_2:
if (addr[15] != AMD_ID_LV128U_3) {
+ debug ("Chip: AMLV128U -> unknown\n");
info->flash_id = FLASH_UNKNOWN;
- }
- else {
+ } else {
+ debug ("Chip: AMLV128U\n");
info->flash_id += FLASH_AMLV128U;
info->sector_count = 256;
info->size = 0x02000000;
}
- break; /* => 32 MB */
+ break; /* => 32 MB */
case AMD_ID_LV640U_2:
if (addr[15] != AMD_ID_LV640U_3) {
+ debug ("Chip: AMLV640U -> unknown\n");
info->flash_id = FLASH_UNKNOWN;
- }
- else {
+ } else {
+ debug ("Chip: AMLV640U\n");
info->flash_id += FLASH_AMLV640U;
info->sector_count = 128;
info->size = 0x01000000;
}
- break; /* => 16 MB */
+ break; /* => 16 MB */
+ case AMD_ID_LV320B_2:
+ if (addr[15] != AMD_ID_LV320B_3) {
+ debug ("Chip: AMLV320B -> unknown\n");
+ info->flash_id = FLASH_UNKNOWN;
+ } else {
+ debug ("Chip: AMLV320B\n");
+ info->flash_id += FLASH_AMLV320B;
+ info->sector_count = 71;
+ info->size = 0x00800000;
+ }
+ break; /* => 8 MB */
default:
+ debug ("Chip: *** unknown ***\n");
info->flash_id = FLASH_UNKNOWN;
break;
}
@@ -338,50 +364,56 @@
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00100000;
- break; /* => 1 MB */
+ break; /* => 1 MB */
case AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00100000;
- break; /* => 1 MB */
+ break; /* => 1 MB */
case AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00200000;
- break; /* => 2 MB */
+ break; /* => 2 MB */
case AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00200000;
- break; /* => 2 MB */
+ break; /* => 2 MB */
case AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 71;
info->size = 0x00800000;
- break; /* => 8 MB */
+ break; /* => 8 MB */
case AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 71;
info->size = 0x00800000;
- break; /* => 8 MB */
+ break; /* => 8 MB */
#endif /* TQM8xxM */
case AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00400000;
- break; /* => 4 MB */
+ break; /* => 4 MB */
case AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00400000;
- break; /* => 4 MB */
+ break; /* => 4 MB */
+
+ case AMD_ID_DL163B:
+ info->flash_id += FLASH_AMDL163B;
+ info->sector_count = 39;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
default:
info->flash_id = FLASH_UNKNOWN;
@@ -402,6 +434,18 @@
base += 0x20000;
}
break;
+ case FLASH_AMLV320B:
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base;
+ /*
+ * The first 8 sectors are 8 kB,
+ * all the other ones are 64 kB
+ */
+ base += (i < 8)
+ ? 2 * ( 8 << 10)
+ : 2 * (64 << 10);
+ }
+ break;
}
break;
# else /* ! TQM8xxM */
@@ -472,11 +516,24 @@
info->start[i] = base + i * 0x00020000;
}
break;
+ case AMD_ID_DL163B:
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base;
+ /*
+ * The first 8 sectors are 8 kB,
+ * all the other ones are 64 kB
+ */
+ base += (i < 8)
+ ? 2 * ( 8 << 10)
+ : 2 * (64 << 10);
+ }
+ break;
default:
return (0);
break;
}
+#if 0
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
@@ -484,6 +541,7 @@
addr = (volatile unsigned long *)(info->start[i]);
info->protect[i] = addr[2] & 1;
}
+#endif
/*
* Prevent writes to uninitialized FLASH.
diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
index 5f74650..c6b53ab 100644
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -21,6 +21,10 @@
* MA 02111-1307 USA
*/
+#if 0
+#define DEBUG
+#endif
+
#include <common.h>
#include <mpc8xx.h>
@@ -92,7 +96,7 @@
* If present, check for "L" type (no second DRAM bank),
* otherwise "L" type is assumed as default.
*
- * Set board_type to 'L' for "L" type, 0 else.
+ * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
*/
int checkboard (void)
@@ -112,6 +116,10 @@
gd->board_type = 'L';
}
+ if ((*(s + 6) == 'M')) { /* a TQM8xxM type */
+ gd->board_type = 'M';
+ }
+
for (; *s; ++s) {
if (*s == ' ')
break;
@@ -167,7 +175,8 @@
memctl->memc_br2 = CFG_BR2_PRELIM;
#ifndef CONFIG_CAN_DRIVER
- if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
+ if ((board_type != 'L') &&
+ (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
memctl->memc_or3 = CFG_OR3_PRELIM;
memctl->memc_br3 = CFG_BR3_PRELIM;
}
@@ -185,7 +194,8 @@
udelay (1);
#ifndef CONFIG_CAN_DRIVER
- if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
+ if ((board_type != 'L') &&
+ (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
udelay (1);
memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
@@ -204,6 +214,7 @@
*/
size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
+ debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
udelay (1000);
@@ -212,33 +223,33 @@
*/
size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
+ debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
-/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
udelay (500);
-/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
}
+ debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
#ifndef CONFIG_CAN_DRIVER
- if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
+ if ((board_type != 'L') &&
+ (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
/*
* Check Bank 1 Memory Size
* use current column settings
* [9 column SDRAM may also be used in 8 column mode,
* but then only half the real size will be used.]
*/
- size_b1 =
- dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
- SDRAM_MAX_SIZE);
-/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
+ size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
+ SDRAM_MAX_SIZE);
+ debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
} else {
size_b1 = 0;
}
-#endif /* CONFIG_CAN_DRIVER */
+#endif /* CONFIG_CAN_DRIVER */
udelay (1000);
@@ -383,8 +394,7 @@
* - short between data lines
*/
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;