imx9: imx93_evk: add low drive mode support on 11x11 EVK
Add a static u-boot config for i.MX93 low drive mode support. When
low drive mode is enabled, VDD_SOC is set to 0.75V. Bus clocks,
A55 core clock (900Mhz), DDR clock (1866MTS), and some peripherals
clocks (USDHC/FLEXSPI/PDM/DISP_PIX/CAM_PIX) must decrease to meet
max frequencies in low drive mode.
Also set standby voltage for buck1
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 1aa2977..352ad79 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -67,10 +67,23 @@
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
- /* 0.9v
- */
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
- pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
+ /* enable DVS control through PMIC_STBY_REQ */
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) {
+ /* 0.75v for Low drive mode
+ */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c);
+ } else {
+ /* 0.9v for Over drive mode
+ */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
+ }
+
+ /* set standby voltage to 0.65v */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
/* I2C_LT_EN*/
pmic_reg_write(dev, 0xa, 0x3);
@@ -103,10 +116,11 @@
printf("SOC: 0x%x\n", gd->arch.soc_rev);
printf("LC: 0x%x\n", gd->arch.lifecycle);
}
+
power_init_board();
- /* 1.7GHz */
- set_arm_clk(1700000000);
+ if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+ set_arm_clk(get_cpu_speed_grade_hz());
/* Init power of mix */
soc_power_init();