| commit | d5ce3574619d6814ea095a798702e342d45203d4 | [log] [tgz] |
|---|---|---|
| author | maxims@google.com <maxims@google.com> | Mon Jan 30 11:35:04 2017 -0800 |
| committer | Tom Rini <trini@konsulko.com> | Wed Feb 08 15:56:30 2017 -0500 |
| tree | 29505cad383e11e624d7fa6c94350344d29f3307 | |
| parent | e163a931af34ba06d11b98707b69b8819e353257 [diff] |
aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation Fix H-PLL and M-PLL rate calculation in ast2500 clock driver. Without this fix, valid setting can lead to division by zero when requesting the rate of H-PLL or M-PLL clocks. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>