Clean-up of cpu_arm920t and cpu_arm920t_s3c24x0 code
This patch re-formats the code in cpu/arm920t and cpu/arm920t/23c24x0 in
preparation for changes to add support for the Embest SBC2440-II Board.
The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports
It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009
Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no
new warnings or errors were found.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c
index db472bf..20cedd4 100644
--- a/cpu/arm920t/s3c24x0/timer.c
+++ b/cpu/arm920t/s3c24x0/timer.c
@@ -30,7 +30,11 @@
*/
#include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#if defined(CONFIG_S3C2400) || \
+ defined(CONFIG_S3C2410) || \
+ defined(CONFIG_TRAB)
+
+#include <asm/io.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
@@ -44,37 +48,40 @@
/* macro to read the 16 bit timer */
static inline ulong READ_TIMER(void)
{
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+ struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
- return (timers->TCNTO4 & 0xffff);
+ return readl(&timers->TCNTO4) & 0xffff;
}
static ulong timestamp;
static ulong lastdec;
-int timer_init (void)
+int timer_init(void)
{
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+ struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
+ ulong tmr;
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
- timers->TCFG0 = 0x0f00;
- if (timer_load_val == 0)
- {
+ writel(0x0f00, &timers->TCFG0);
+ if (timer_load_val == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz
*/
- timer_load_val = get_PCLK()/(2 * 16 * 100);
+ timer_load_val = get_PCLK() / (2 * 16 * 100);
timer_clk = get_PCLK() / (2 * 16);
}
/* load value for 10 ms timeout */
- lastdec = timers->TCNTB4 = timer_load_val;
+ lastdec = timer_load_val;
+ writel(timer_load_val, &timers->TCNTB4);
/* auto load, manual update of Timer 4 */
- timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
+ tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
+ writel(tmr, &timers->TCON);
/* auto load, start Timer 4 */
- timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
+ tmr = (tmr & ~0x0700000) | 0x0500000;
+ writel(tmr, &timers->TCON);
timestamp = 0;
return (0);
@@ -84,22 +91,22 @@
* timer without interrupts
*/
-void reset_timer (void)
+void reset_timer(void)
{
- reset_timer_masked ();
+ reset_timer_masked();
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
- return get_timer_masked () - base;
+ return get_timer_masked() - base;
}
-void set_timer (ulong t)
+void set_timer(ulong t)
{
timestamp = t;
}
-void udelay (unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo;
ulong start = get_ticks();
@@ -112,21 +119,21 @@
/*NOP*/;
}
-void reset_timer_masked (void)
+void reset_timer_masked(void)
{
/* reset time */
lastdec = READ_TIMER();
timestamp = 0;
}
-ulong get_timer_masked (void)
+ulong get_timer_masked(void)
{
ulong tmr = get_ticks();
return tmr / (timer_clk / CONFIG_SYS_HZ);
}
-void udelay_masked (unsigned long usec)
+void udelay_masked(unsigned long usec)
{
ulong tmo;
ulong endtime;
@@ -138,7 +145,7 @@
tmo /= 1000;
} else {
tmo = usec * (timer_load_val * 100);
- tmo /= (1000*1000);
+ tmo /= (1000 * 1000);
}
endtime = get_ticks() + tmo;
@@ -173,7 +180,7 @@
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
-ulong get_tbclk (void)
+ulong get_tbclk(void)
{
ulong tbclk;
@@ -193,30 +200,31 @@
/*
* reset the cpu by setting up the watchdog timer and let him time out
*/
-void reset_cpu (ulong ignored)
+void reset_cpu(ulong ignored)
{
- volatile S3C24X0_WATCHDOG * watchdog;
+ struct s3c24x0_watchdog *watchdog;
#ifdef CONFIG_TRAB
- extern void disable_vfd (void);
-
disable_vfd();
#endif
- watchdog = S3C24X0_GetBase_WATCHDOG();
+ watchdog = s3c24x0_get_base_watchdog();
/* Disable watchdog */
- watchdog->WTCON = 0x0000;
+ writel(0x0000, &watchdog->WTCON);
/* Initialize watchdog timer count register */
- watchdog->WTCNT = 0x0001;
+ writel(0x0001, &watchdog->WTCNT);
/* Enable watchdog timer; assert reset at timer timeout */
- watchdog->WTCON = 0x0021;
+ writel(0x0021, &watchdog->WTCON);
- while(1); /* loop forever and wait for reset to happen */
+ while (1)
+ /* loop forever and wait for reset to happen */;
/*NOTREACHED*/
}
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
+#endif /* defined(CONFIG_S3C2400) ||
+ defined (CONFIG_S3C2410) ||
+ defined (CONFIG_TRAB) */