Merge tag 'i2c-updates-for-v2023.04' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2023.04
- add new i2c driver ast2600 from Ryan Chen
- i2c-cdns: make read fifo-depth configurable through device tree
from Pei Yue Ho
- mxc i2c driver: print base address in hex, not in decimal
from Fabio
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d9b719f..9d647b9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -247,6 +247,8 @@
armada-385-atl-x530.dtb \
armada-385-atl-x530DP.dtb \
armada-385-db-88f6820-amc.dtb \
+ armada-385-synology-ds116.dtb \
+ armada-385-thecus-n2350.dtb \
armada-385-turris-omnia.dtb \
armada-388-clearfog.dtb \
armada-388-gp.dtb \
diff --git a/arch/arm/dts/armada-385-synology-ds116.dts b/arch/arm/dts/armada-385-synology-ds116.dts
new file mode 100644
index 0000000..82a0373
--- /dev/null
+++ b/arch/arm/dts/armada-385-synology-ds116.dts
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Device Tree file for Synology DS116 NAS
+ *
+ * Copyright (C) 2017 Willy Tarreau <w@1wt.eu>
+ */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Synology DS116";
+ compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>; /* 1 GB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+
+ internal-regs {
+ i2c@11000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ };
+ };
+
+ serial@12000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+ };
+
+ serial@12100 {
+ /* A PIC16F1829 is connected to uart1 at 9600 bps,
+ * and takes single-character orders :
+ * "1" : power off // already handled by the poweroff node
+ * "2" : short beep
+ * "3" : long beep
+ * "4" : turn the power LED ON
+ * "5" : flash the power LED
+ * "6" : turn the power LED OFF
+ * "7" : turn the status LED OFF
+ * "8" : turn the status LED ON
+ * "9" : flash the status LED
+ * "A" : flash the motherboard LED (D8)
+ * "B" : turn the motherboard LED OFF
+ * "C" : hard reset
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+ };
+
+ poweroff@12100 {
+ compatible = "synology,power-off";
+ reg = <0x12100 0x100>;
+ clocks = <&coreclk 0>;
+ };
+
+ ethernet@70000 {
+ pinctrl-names = "default";
+ phy = <&phy0>;
+ phy-mode = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ status = "okay";
+ };
+
+ mdio@72004 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+
+ sata@a8000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sata0_pins>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ target-supply = <®_5v_sata0>;
+ };
+ };
+
+ bm@c8000 {
+ status = "okay";
+ };
+
+ usb3@f0000 {
+ usb-phy = <&usb3_0_phy>;
+ status = "okay";
+ };
+
+ usb3@f8000 {
+ usb-phy = <&usb3_1_phy>;
+ status = "okay";
+ };
+ };
+
+ bm-bppi {
+ status = "okay";
+ };
+
+ gpio-fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>,
+ <&gpio1 17 GPIO_ACTIVE_HIGH>,
+ <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = < 0 0
+ 1500 1
+ 2500 2
+ 3000 3
+ 3400 4
+ 3700 5
+ 3900 6
+ 4000 7>;
+ #cooling-cells = <2>;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ /* The green part is on gpio0.20 which is also used by
+ * sata0, and accesses to SATA disk 0 make it blink so it
+ * doesn't need to be declared here.
+ */
+ orange {
+ gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+ label = "ds116:orange:disk";
+ default-state = "off";
+ };
+ };
+ };
+
+ usb3_0_phy: usb3_0_phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <®_usb3_0_vbus>;
+ #phy-cells = <0>;
+ };
+
+ usb3_1_phy: usb3_1_phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <®_usb3_1_vbus>;
+ #phy-cells = <0>;
+ };
+
+ reg_usb3_0_vbus: usb3-vbus0 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3-vbus0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&xhci0_vbus_pins>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_usb3_1_vbus: usb3-vbus1 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3-vbus1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&xhci1_vbus_pins>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_sata0: pwr-sata0 {
+ compatible = "regulator-fixed";
+ regulator-name = "pwr_en_sata0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ enable-active-high;
+ regulator-boot-on;
+ gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_5v_sata0: v5-sata0 {
+ compatible = "regulator-fixed";
+ regulator-name = "v5.0-sata0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_sata0>;
+ };
+
+ reg_12v_sata0: v12-sata0 {
+ compatible = "regulator-fixed";
+ regulator-name = "v12.0-sata0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <®_sata0>;
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "macronix,mx25l6405d", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+
+ /* Note: there is a redboot partition table despite u-boot
+ * being used. The names presented here are the same as those
+ * found in the FIS directory. There is also a small device
+ * tree in the last 64kB of the RedBoot partition which is not
+ * enumerated. The MAC address and the serial number are listed
+ * in the "vendor" partition.
+ */
+ partition@0 {
+ label = "RedBoot";
+ reg = <0x00000000 0x000f0000>;
+ read-only;
+ };
+
+ partition@c0000 {
+ label = "zImage";
+ reg = <0x000f0000 0x002d0000>;
+ };
+
+ partition@390000 {
+ label = "rd.gz";
+ reg = <0x003c0000 0x00410000>;
+ };
+
+ partition@7d0000 {
+ label = "vendor";
+ reg = <0x007d0000 0x00010000>;
+ read-only;
+ };
+
+ partition@7e0000 {
+ label = "RedBoot config";
+ reg = <0x007e0000 0x00010000>;
+ read-only;
+ };
+
+ partition@7f0000 {
+ label = "FIS directory";
+ reg = <0x007f0000 0x00010000>;
+ read-only;
+ };
+ };
+};
+
+&pinctrl {
+ /* use only one pin for UART1, as mpp20 is used by sata0 */
+ uart1_pins: uart-pins-1 {
+ marvell,pins = "mpp19";
+ marvell,function = "ua1";
+ };
+
+ xhci0_vbus_pins: xhci0_vbus_pins {
+ marvell,pins = "mpp58";
+ marvell,function = "gpio";
+ };
+ xhci1_vbus_pins: xhci1_vbus_pins {
+ marvell,pins = "mpp59";
+ marvell,function = "gpio";
+ };
+};
diff --git a/arch/arm/dts/armada-385-thecus-n2350.dts b/arch/arm/dts/armada-385-thecus-n2350.dts
new file mode 100644
index 0000000..fc29c4d
--- /dev/null
+++ b/arch/arm/dts/armada-385-thecus-n2350.dts
@@ -0,0 +1,446 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Device Tree file for Thecus N2350 board
+ *
+ * Copyright (C) 2018-2023 Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2018 Manuel Jung <manuel.jung@hotmail.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-385.dtsi"
+
+/ {
+ model = "Thecus N2350";
+ compatible = "thecus,n2350", "marvell,armada385";
+
+ aliases {
+ ethernet0 = ð0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>; /* 1GB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+
+ };
+
+ usb3_0_phy: usb3_0_phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&usb3_0_power>;
+ };
+
+ usb3_1_phy: usb3_1_phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&usb3_1_power>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_power_button &pmx_copy_button &pmx_reset_button>;
+ pinctrl-names = "default";
+
+ button@1 {
+ label = "Power Button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ };
+
+ button@2 {
+ label = "Copy Button";
+ linux,code = <KEY_COPY>;
+ gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ button@3 {
+ label = "Reset Button";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_sata1_white_led
+ &pmx_sata1_red_led
+ &pmx_sata2_white_led
+ &pmx_sata2_red_led
+ &pmx_sys_white_led
+ &pmx_sys_red_led
+ &pmx_pwr_blue_led
+ &pmx_pwr_red_led
+ &pmx_usb_white_led
+ &pmx_usb_red_led>;
+
+ pinctrl-names = "default";
+
+ white_sata1 {
+ label = "n2350:white:sata1";
+ gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "ide-disk1";
+ };
+
+ red_sata1 {
+ label = "n2350:red:sata1";
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ white-sata2 {
+ label = "n2350:white:sata2";
+ gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ red-sata2 {
+ label = "n2350:red:sata2";
+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ white-sys {
+ label = "n2350:white:sys";
+ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ red-sys {
+ label = "n2350:red:sys";
+ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue-pwr {
+ label = "n2350:blue:pwr";
+ gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ red-pwr {
+ label = "n2350:red:pwr";
+ gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+ };
+
+ white-usb {
+ label = "n2350:white:usb";
+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ };
+
+ red-usb {
+ label = "n2350:red:usb";
+ gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_0_power: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "USB3_0_Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ usb3_1_power: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "USB3_1_Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_sata0: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "pwr_en_sata0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_5v_sata0: v5-sata0 {
+ compatible = "regulator-fixed";
+ regulator-name = "v5.0-sata0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_sata0>;
+ };
+
+ reg_12v_sata0: v12-sata0 {
+ compatible = "regulator-fixed";
+ regulator-name = "v12.0-sata0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <®_sata0>;
+ };
+
+ reg_sata1: regulator@4 {
+ regulator-name = "pwr_en_sata1";
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_5v_sata1: v5-sata1 {
+ compatible = "regulator-fixed";
+ regulator-name = "v5.0-sata1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_sata1>;
+ };
+
+ reg_12v_sata1: v12-sata1 {
+ compatible = "regulator-fixed";
+ regulator-name = "v12.0-sata1";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <®_sata1>;
+ };
+
+ };
+
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-0 = <&pmx_pwr_off>;
+ pinctrl-names = "default";
+ gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ };
+
+};
+
+&ahci0 {
+ status = "okay";
+};
+
+&bm {
+ status = "okay";
+};
+
+&bm_bppi {
+ status = "okay";
+};
+
+ð0 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ };
+};
+
+&nand_controller {
+ status = "okay";
+
+ nand@0 {
+ status = "okay";
+ reg = <0>;
+ label = "pxa3xx_nand-0";
+ nand-rb = <0>;
+ marvell,nand-keep-config;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "rootfs";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ };
+ };
+};
+
+&pciec {
+ status = "okay";
+ /*
+ * The two PCIe units are accessible through
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+
+ pmx_power_button: pmx-power-button {
+ marvell,pins = "mpp49";
+ marvell,function = "gpio";
+ };
+
+ pmx_copy_button: pmx-copy-button {
+ marvell,pins = "mpp52";
+ marvell,function = "gpio";
+ };
+
+ pmx_reset_button: pmx-reset-button {
+ marvell,pins = "mpp50";
+ marvell,function = "gpio";
+ };
+
+ pmx_sata1_white_led: pmx-sata1-white-led {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+
+ pmx_sata1_red_led: pmx-sata1-red-led {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+
+ pmx_sata2_white_led: pmx-sata2-white-led {
+ marvell,pins = "mpp19";
+ marvell,function = "gpio";
+ };
+
+ pmx_sata2_red_led: pmx-sata2-red-led {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+
+ pmx_sys_white_led: pmx-sys-white-led {
+ marvell,pins = "mpp14";
+ marvell,function = "gpio";
+ };
+
+ pmx_sys_red_led: pmx-sys-red-led {
+ marvell,pins = "mpp15";
+ marvell,function = "gpio";
+ };
+
+ pmx_buzzer: pmx-buzzer {
+ marvell,pins = "mpp51";
+ marvell,function = "gpio";
+ };
+
+ pmx_pwr_off: pmx-pwr-off {
+ marvell,pins = "mpp54";
+ marvell,function = "gpio";
+ };
+
+ pmx_pwr_blue_led: pmx-pwr-blue-led {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+
+ pmx_pwr_red_led: pmx-pwr-red-led {
+ marvell,pins = "mpp18";
+ marvell,function = "gpio";
+ };
+
+ pmx_usb_white_led: pmx-usb-white-led {
+ marvell,pins = "mpp16";
+ marvell,function = "gpio";
+ };
+
+ pmx_usb_red_led: pmx-usb-red-led {
+ marvell,pins = "mpp17";
+ marvell,function = "gpio";
+ };
+};
+
+&sdhci {
+ broken-cd;
+ wp-inverted;
+ bus-width = <8>;
+ status = "okay";
+ no-1-8-v;
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ status = "okay";
+
+ /* spi: 4M Flash Macronix MX25L3205D */
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "macronix,mx25l3205d", "jedec,spi-nor";
+ reg = <0>;
+
+ spi-max-frequency = <108000000>;
+ spi-cpha;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x00000000 0x00100000>;
+ };
+
+ partition@100000 {
+ label = "u-boot-env";
+ reg = <0x00100000 0x00010000>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi b/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
new file mode 100644
index 0000000..f9e1272
--- /dev/null
+++ b/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
+ */
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 45cc932..b19ed2c 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -15,6 +15,7 @@
config KIRKWOOD_COMMON
bool
select DM_SERIAL
+ select SYS_NS16550
config HAS_CUSTOM_SYS_INIT_SP_ADDR
bool "Use a custom location for the initial stack pointer address"
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 594e9a0..16c5e72 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -97,6 +97,9 @@
config CUSTOMER_BOARD_SUPPORT
bool
+config DDR4
+ bool "Support Marvell DDR4 Training driver"
+
choice
prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
optional
@@ -166,6 +169,10 @@
select BOARD_ECC_SUPPORT
select MV78460
+config TARGET_DS116
+ bool "Support Synology DS116"
+ select 88F6820
+
config TARGET_DS414
bool "Support Synology DS414"
select MV78230
@@ -175,6 +182,11 @@
select BOARD_ECC_SUPPORT
select MV78460
+config TARGET_N2350
+ bool "Support Thecus N2350"
+ select 88F6820
+ select DDR4
+
config TARGET_THEADORABLE
bool "Support theadorable Armada XP"
select BOARD_LATE_INIT if USB
@@ -255,8 +267,10 @@
default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
default "octeontx2_cn913x" if TARGET_OCTEONTX2_CN913x
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
+ default "ds116" if TARGET_DS116
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
+ default "n2350" if TARGET_N2350
default "theadorable" if TARGET_THEADORABLE
default "a38x" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
@@ -274,8 +288,10 @@
default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
default "mvebu_armada-8k" if TARGET_OCTEONTX2_CN913x
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
+ default "ds116" if TARGET_DS116
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
+ default "n2350" if TARGET_N2350
default "theadorable" if TARGET_THEADORABLE
default "turris_omnia" if TARGET_TURRIS_OMNIA
default "turris_mox" if TARGET_TURRIS_MOX
@@ -297,7 +313,9 @@
default "Marvell" if TARGET_MVEBU_DB_88F7040
default "solidrun" if TARGET_CLEARFOG
default "kobol" if TARGET_HELIOS4
+ default "Synology" if TARGET_DS116
default "Synology" if TARGET_DS414
+ default "thecus" if TARGET_N2350
default "CZ.NIC" if TARGET_TURRIS_OMNIA
default "CZ.NIC" if TARGET_TURRIS_MOX
default "gdsys" if TARGET_CONTROLCENTERDC
diff --git a/board/Synology/ds116/MAINTAINERS b/board/Synology/ds116/MAINTAINERS
new file mode 100644
index 0000000..a5080b0
--- /dev/null
+++ b/board/Synology/ds116/MAINTAINERS
@@ -0,0 +1,7 @@
+DS116 BOARD
+M: Tony Dinh <mibodhi@gmail.com>
+S: Maintained
+F: arch/arm/dts/armada-385-synology-ds116.dts
+F: board/Synology/ds116/
+F: include/configs/ds116.h
+F: configs/ds116_defconfig
diff --git a/board/Synology/ds116/Makefile b/board/Synology/ds116/Makefile
new file mode 100644
index 0000000..952cc1b
--- /dev/null
+++ b/board/Synology/ds116/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
+#
+
+obj-y := ds116.o
diff --git a/board/Synology/ds116/ds116.c b/board/Synology/ds116/ds116.c
new file mode 100644
index 0000000..cf2575b
--- /dev/null
+++ b/board/Synology/ds116/ds116.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
+ *
+ */
+
+#include <i2c.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/bitops.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Those DS116_GPP_xx values and defines in board_serdes_map, and board_topology_map
+ * are taken from Marvell U-Boot version
+ * U-Boot 2013.01-g6cc0a6d (Marvell version: 2015_T1.0p16)
+ */
+#define DS116_GPP_OUT_ENA_LOW \
+ (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
+ BIT(10) | BIT(11) | BIT(15) | BIT(19) | BIT(22) | BIT(23) | \
+ BIT(25) | BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
+#define DS116_GPP_OUT_ENA_MID \
+ (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
+ BIT(16) | BIT(17) | BIT(18) | BIT(26) | BIT(27)))
+
+#define DS116_GPP_OUT_VAL_LOW BIT(15)
+#define DS116_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
+#define DS116_GPP_POL_LOW 0x0
+#define DS116_GPP_POL_MID 0x0
+
+static struct serdes_map board_serdes_map[] = {
+ {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+ *serdes_map_array = board_serdes_map;
+ *count = ARRAY_SIZE(board_serdes_map);
+ return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+ DEBUG_LEVEL_ERROR,
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1866L, /* speed_bin */
+ MV_DDR_DEV_WIDTH_16BIT, /* memory_width - 16 bits */
+ MV_DDR_DIE_CAP_4GBIT, /* mem_size - DS116 board has 2x512MB DRAM banks */
+ MV_DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_wl cas_l */
+ MV_DDR_TEMP_LOW, /* temperature */
+ MV_DDR_TIM_DEFAULT} }, /* timing */
+ BUS_MASK_32BIT, /* Busses mask */
+ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
+ { {0} }, /* raw spd data */
+ {0} /* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+ /* Return the board topology as defined in the board code */
+ return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * Those MPP values are taken from the Marvell U-Boot version
+ * U-Boot 2013.01-g6cc0a6d (Marvell version: 2015_T1.0p16)
+ */
+
+ /* Configure MPP */
+ writel(0x00111111, MVEBU_MPP_BASE + 0x00);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x04);
+ writel(0x11040330, MVEBU_MPP_BASE + 0x08);
+ writel(0x00000011, MVEBU_MPP_BASE + 0x0c);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x10);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x14);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x18);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
+
+ /* Set GPP Out value */
+ writel(DS116_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(DS116_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+ /* Set GPP Polarity */
+ writel(DS116_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ writel(DS116_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+ /* Set GPP Out Enable */
+ writel(DS116_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(DS116_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+ cpu_eth_init(bis); /* Built in controller(s) come first */
+ return pci_eth_init(bis);
+}
diff --git a/board/thecus/n2350/MAINTAINERS b/board/thecus/n2350/MAINTAINERS
new file mode 100644
index 0000000..2b8774f
--- /dev/null
+++ b/board/thecus/n2350/MAINTAINERS
@@ -0,0 +1,7 @@
+N2350 BOARD
+M: Tony Dinh <mibodhi@gmail.com>
+S: Maintained
+F: arch/arm/dts/armada-385-thecus-n2350.dts
+F: board/thecus/n2350/
+F: include/configs/n2350.h
+F: configs/n2350_defconfig
diff --git a/board/thecus/n2350/Makefile b/board/thecus/n2350/Makefile
new file mode 100644
index 0000000..b220bb1
--- /dev/null
+++ b/board/thecus/n2350/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
+#
+
+obj-y := n2350.o
diff --git a/board/thecus/n2350/n2350.c b/board/thecus/n2350/n2350.c
new file mode 100644
index 0000000..fd8f95f
--- /dev/null
+++ b/board/thecus/n2350/n2350.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
+ *
+ */
+
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/bitops.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Those N2350_GPP_xx values and defines in board_serdes_map, and board_topology_map
+ * are taken from the Marvell U-Boot version "u-boot-a38x-2015T1_p18_Thecus"
+ */
+
+#define N2350_GPP_OUT_ENA_LOW (~(BIT(20) | BIT(21) | BIT(24)))
+#define N2350_GPP_OUT_ENA_MID (~(BIT(12) | BIT(13) | BIT(16) | BIT(19) | BIT(22)))
+#define N2350_GPP_OUT_VAL_LOW (BIT(21) | BIT(24))
+#define N2350_GPP_OUT_VAL_MID (BIT(0) | BIT(12) | BIT(13))
+#define N2350_GPP_POL_LOW 0x0
+#define N2350_GPP_POL_MID 0x0
+
+static struct serdes_map board_serdes_map[] = {
+ { SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ { SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ { SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ { DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ { USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ { USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+ *serdes_map_array = board_serdes_map;
+ *count = ARRAY_SIZE(board_serdes_map);
+ return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR4 init code in the SPL U-Boot version to configure
+ * the DDR4 controller.
+ */
+
+static struct mv_ddr_topology_map board_topology_map = {
+ DEBUG_LEVEL_ERROR,
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1866L, /* speed_bin */
+ MV_DDR_DEV_WIDTH_16BIT, /* memory_width - 16 bits */
+ MV_DDR_DIE_CAP_4GBIT, /* mem_size - N2350 board has 2x512MB DRAM banks */
+ MV_DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_wl cas_l */
+ MV_DDR_TEMP_LOW, /* temperature */
+ MV_DDR_TIM_DEFAULT} }, /* timing */
+ BUS_MASK_32BIT, /* Busses mask */
+ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
+ { {0} }, /* raw spd data */
+ {0} /* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+ /* Return the board topology as defined in the board code */
+ return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+ /* Those MPP values are taken from the Marvell U-Boot version
+ * "u-boot-a38x-2015T1_p18_Thecus"
+ */
+
+ /* Configure MPP */
+ writel(0x50111111, MVEBU_MPP_BASE + 0x00); /* MPP0_7 */
+ writel(0x00555555, MVEBU_MPP_BASE + 0x04); /* MPP8_15 */
+ writel(0x55000000, MVEBU_MPP_BASE + 0x08); /* MPP16_23 */
+ writel(0x05050050, MVEBU_MPP_BASE + 0x0c); /* MPP24_31 */
+ writel(0x05555555, MVEBU_MPP_BASE + 0x10); /* MPP32_39 */
+ writel(0x00000565, MVEBU_MPP_BASE + 0x14); /* MPP40_47 */
+ writel(0x00000000, MVEBU_MPP_BASE + 0x18); /* MPP48_55 */
+ writel(0x00004444, MVEBU_MPP_BASE + 0x1c); /* MPP56_63 */
+
+ /* Set GPP Out value */
+ writel(N2350_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(N2350_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+ /* Set GPP Polarity */
+ writel(N2350_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ writel(N2350_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+ /* Set GPP Out Enable */
+ writel(N2350_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(N2350_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+ cpu_eth_init(bis); /* Built in controller(s) come first */
+ return pci_eth_init(bis);
+}
diff --git a/cmd/fdt.c b/cmd/fdt.c
index 8e51a43..1972490 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -208,19 +208,11 @@
}
return CMD_RET_SUCCESS;
- }
-
- if (!working_fdt) {
- puts("No FDT memory address configured. Please configure\n"
- "the FDT address via \"fdt addr <address>\" command.\n"
- "Aborting!\n");
- return CMD_RET_FAILURE;
- }
/*
* Move the working_fdt
*/
- if (strncmp(argv[1], "mo", 2) == 0) {
+ } else if (strncmp(argv[1], "mo", 2) == 0) {
struct fdt_header *newaddr;
int len;
int err;
@@ -231,11 +223,11 @@
/*
* Set the address and length of the fdt.
*/
- working_fdt = (struct fdt_header *)hextoul(argv[2], NULL);
+ working_fdt = map_sysmem(hextoul(argv[2], NULL), 0);
if (!fdt_valid(&working_fdt))
return 1;
- newaddr = (struct fdt_header *)hextoul(argv[3], NULL);
+ newaddr = map_sysmem(hextoul(argv[3], NULL), 0);
/*
* If the user specifies a length, use that. Otherwise use the
@@ -262,10 +254,21 @@
fdt_strerror(err));
return 1;
}
- set_working_fdt_addr((ulong)newaddr);
+ set_working_fdt_addr(map_to_sysmem(newaddr));
+
+ return CMD_RET_SUCCESS;
+ }
+
+ if (!working_fdt) {
+ puts("No FDT memory address configured. Please configure\n"
+ "the FDT address via \"fdt addr <address>\" command.\n"
+ "Aborting!\n");
+ return CMD_RET_FAILURE;
+ }
+
#ifdef CONFIG_OF_SYSTEM_SETUP
/* Call the board-specific fixup routine */
- } else if (strncmp(argv[1], "sys", 3) == 0) {
+ if (strncmp(argv[1], "sys", 3) == 0) {
int err = ft_system_setup(working_fdt, gd->bd);
if (err) {
@@ -273,11 +276,14 @@
fdt_strerror(err));
return CMD_RET_FAILURE;
}
+
+ return CMD_RET_SUCCESS;
+ }
#endif
/*
* Make a new node
*/
- } else if (strncmp(argv[1], "mk", 2) == 0) {
+ if (strncmp(argv[1], "mk", 2) == 0) {
char *pathp; /* path */
char *nodep; /* new node to add */
int nodeoffset; /* node offset from libfdt */
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
index bf8d453..4591ff3 100644
--- a/cmd/tlv_eeprom.c
+++ b/cmd/tlv_eeprom.c
@@ -479,17 +479,14 @@
show_tlv_devices();
break;
default:
- cmd_usage(cmdtp);
- break;
+ return CMD_RET_USAGE;
}
return 0;
}
// The set command takes one or two args.
- if (argc > 4) {
- cmd_usage(cmdtp);
- return 0;
- }
+ if (argc > 4)
+ return CMD_RET_USAGE;
// Set command. If the TLV exists in the EEPROM, delete it. Then if
// data was supplied for this TLV add the TLV with the new contents at
@@ -512,7 +509,7 @@
current_dev = devnum;
has_been_read = 0;
} else {
- cmd_usage(cmdtp);
+ return CMD_RET_USAGE;
}
return 0;
diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig
new file mode 100644
index 0000000..5546017
--- /dev/null
+++ b/configs/ds116_defconfig
@@ -0,0 +1,92 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x00800000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_DS116=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x7E0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="armada-385-synology-ds116"
+CONFIG_SPL_TEXT_BASE=0x40000030
+CONFIG_SYS_PROMPT="DS116> "
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xf1012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_IDENT_STRING="\nSynology DS116"
+CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
+CONFIG_BOOTDELAY=10
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x22fd0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x40023000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL_I2C=y
+CONFIG_SYS_MAXARGS=32
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPIO_READ=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:1m(u-boot),7040k(kernel),64k(u-boot-env),-(data)"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_ARP_TIMEOUT=200
+CONFIG_NET_RETRY_COUNT=50
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_LBA48=y
+CONFIG_SYS_64BIT_LBA=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_MVNETA=y
+CONFIG_MII=y
+CONFIG_MVMDIO=y
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_38X=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_ARMADA38X=y
+CONFIG_SCSI=y
+CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig
new file mode 100644
index 0000000..dcb2c96
--- /dev/null
+++ b/configs/n2350_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x00800000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
+CONFIG_TARGET_N2350=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="armada-385-thecus-n2350"
+CONFIG_SPL_TEXT_BASE=0x40000030
+CONFIG_SYS_PROMPT="N2350 > "
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK=0x4002c000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xf1012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_IDENT_STRING="\nThecus N2350"
+CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_ENV_ADDR=0x100000
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x22fd0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x40023000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_I2C=y
+CONFIG_SYS_MAXARGS=32
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPIO_READ=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=pxa3xx_nand-0:-(rootfs);spi1.0:1M(u-boot),64K@1M(u-boot-env),-(data)"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_ARP_TIMEOUT=200
+CONFIG_NET_RETRY_COUNT=50
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_LBA48=y
+CONFIG_SYS_64BIT_LBA=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_MVNETA=y
+CONFIG_MII=y
+CONFIG_MVMDIO=y
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_38X=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_ARMADA38X=y
+CONFIG_SCSI=y
+CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index cb38a3f..40ab16d 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -26,6 +26,11 @@
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
diff --git a/include/configs/ds116.h b/include/configs/ds116.h
new file mode 100644
index 0000000..031f4f6
--- /dev/null
+++ b/include/configs/ds116.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
+ *
+ */
+
+#ifndef _CONFIG_DS116_H
+#define _CONFIG_DS116_H
+
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define RELOCATION_LIMITS_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Include the common distro boot environment */
+#ifndef CONFIG_SPL_BUILD
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(SCSI, scsi, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#define KERNEL_ADDR_R __stringify(0x1000000)
+#define FDT_ADDR_R __stringify(0x2000000)
+#define RAMDISK_ADDR_R __stringify(0x2200000)
+#define SCRIPT_ADDR_R __stringify(0x1800000)
+#define PXEFILE_ADDR_R __stringify(0x1900000)
+
+#define LOAD_ADDRESS_ENV_SETTINGS \
+ "kernel_addr_r=" KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" FDT_ADDR_R "\0" \
+ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
+ "scriptaddr=" SCRIPT_ADDR_R "\0" \
+ "pxefile_addr_r=" PXEFILE_ADDR_R "\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ RELOCATION_LIMITS_ENV_SETTINGS \
+ LOAD_ADDRESS_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "console=ttyS0,115200\0" \
+ BOOTENV
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* _CONFIG_DS116_H */
diff --git a/include/configs/n2350.h b/include/configs/n2350.h
new file mode 100644
index 0000000..92b2270
--- /dev/null
+++ b/include/configs/n2350.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
+ *
+ */
+
+#ifndef _CONFIG_N2350_H
+#define _CONFIG_N2350_H
+
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define RELOCATION_LIMITS_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Include the common distro boot environment */
+#ifndef CONFIG_SPL_BUILD
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(SCSI, scsi, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#define KERNEL_ADDR_R __stringify(0x1000000)
+#define FDT_ADDR_R __stringify(0x2000000)
+#define RAMDISK_ADDR_R __stringify(0x2200000)
+#define SCRIPT_ADDR_R __stringify(0x1800000)
+#define PXEFILE_ADDR_R __stringify(0x1900000)
+
+#define LOAD_ADDRESS_ENV_SETTINGS \
+ "kernel_addr_r=" KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" FDT_ADDR_R "\0" \
+ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
+ "scriptaddr=" SCRIPT_ADDR_R "\0" \
+ "pxefile_addr_r=" PXEFILE_ADDR_R "\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ RELOCATION_LIMITS_ENV_SETTINGS \
+ LOAD_ADDRESS_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "console=ttyS0,115200\0" \
+ BOOTENV
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* _CONFIG_N2350_H */
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 6b203df..062f54a 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -1503,7 +1503,7 @@
"""Tests outputting a map of the images"""
_, _, map_data, _ = self._DoReadFileDtb('055_sections.dts', map=True)
self.assertEqual('''ImagePos Offset Size Name
-00000000 00000000 00000028 main-section
+00000000 00000000 00000028 image
00000000 00000000 00000010 section@0
00000000 00000000 00000004 u-boot
00000010 00000010 00000010 section@1
@@ -1516,7 +1516,7 @@
"""Tests that name prefixes are used"""
_, _, map_data, _ = self._DoReadFileDtb('056_name_prefix.dts', map=True)
self.assertEqual('''ImagePos Offset Size Name
-00000000 00000000 00000028 main-section
+00000000 00000000 00000028 image
00000000 00000000 00000010 section@0
00000000 00000000 00000004 ro-u-boot
00000010 00000010 00000010 section@1
@@ -1795,8 +1795,7 @@
self._DoTestFile('071_gbb.dts', force_missing_bintools='futility',
entry_args=entry_args)
err = stderr.getvalue()
- self.assertRegex(err,
- "Image 'main-section'.*missing bintools.*: futility")
+ self.assertRegex(err, "Image 'image'.*missing bintools.*: futility")
def _HandleVblockCommand(self, pipe_list):
"""Fake calls to the futility utility
@@ -1893,8 +1892,7 @@
force_missing_bintools='futility',
entry_args=entry_args)
err = stderr.getvalue()
- self.assertRegex(err,
- "Image 'main-section'.*missing bintools.*: futility")
+ self.assertRegex(err, "Image 'image'.*missing bintools.*: futility")
def testTpl(self):
"""Test that an image with TPL and its device tree can be created"""
@@ -2106,7 +2104,7 @@
tools.get_bytes(ord('d'), 8))
self.assertEqual(expect, data)
self.assertEqual('''ImagePos Offset Size Name
-00000000 00000000 00000028 main-section
+00000000 00000000 00000028 image
00000000 00000000 00000008 fill
00000008 00000008 00000004 u-boot
0000000c 0000000c 00000004 section
@@ -2259,7 +2257,7 @@
self.assertTrue(os.path.exists(map_fname))
map_data = tools.read_file(map_fname, binary=False)
self.assertEqual('''ImagePos Offset Size Name
-<none> 00000000 00000008 main-section
+<none> 00000000 00000008 image
<none> 00000000 00000004 u-boot
<none> 00000003 00000004 u-boot-align
''', map_data)
@@ -2274,7 +2272,7 @@
data, _, map_data, _ = self._DoReadFileDtb('101_sections_offset.dts',
map=True)
self.assertEqual('''ImagePos Offset Size Name
-00000000 00000000 00000038 main-section
+00000000 00000000 00000038 image
00000004 00000004 00000010 section@0
00000004 00000000 00000004 u-boot
00000018 00000018 00000010 section@1
@@ -2446,7 +2444,7 @@
force_missing_bintools='ifwitool')
err = stderr.getvalue()
self.assertRegex(err,
- "Image 'main-section'.*missing bintools.*: ifwitool")
+ "Image 'image'.*missing bintools.*: ifwitool")
def testCbfsOffset(self):
"""Test a CBFS with files at particular offsets
@@ -2633,7 +2631,7 @@
ent = entries[0]
self.assertEqual(0, ent.indent)
- self.assertEqual('main-section', ent.name)
+ self.assertEqual('image', ent.name)
self.assertEqual('section', ent.etype)
self.assertEqual(len(data), ent.size)
self.assertEqual(0, ent.image_pos)
@@ -2792,7 +2790,7 @@
expected = [
'Name Image-pos Size Entry-type Offset Uncomp-size',
'----------------------------------------------------------------------',
-'main-section 0 c00 section 0',
+'image 0 c00 section 0',
' u-boot 0 4 u-boot 0',
' section 100 %x section 100' % section_size,
' cbfs 100 400 cbfs 0',
@@ -3735,8 +3733,7 @@
self._DoTestFile('156_mkimage.dts',
force_missing_bintools='mkimage')
err = stderr.getvalue()
- self.assertRegex(err,
- "Image 'main-section'.*missing bintools.*: mkimage")
+ self.assertRegex(err, "Image 'image'.*missing bintools.*: mkimage")
def testExtblob(self):
"""Test an image with an external blob"""
@@ -3757,7 +3754,7 @@
allow_missing=True)
self.assertEqual(103, ret)
err = stderr.getvalue()
- self.assertRegex(err, "Image 'main-section'.*missing.*: blob-ext")
+ self.assertRegex(err, "Image 'image'.*missing.*: blob-ext")
self.assertIn('Some images are invalid', err)
def testExtblobMissingOkFlag(self):
@@ -3767,7 +3764,7 @@
allow_missing=True, ignore_missing=True)
self.assertEqual(0, ret)
err = stderr.getvalue()
- self.assertRegex(err, "Image 'main-section'.*missing.*: blob-ext")
+ self.assertRegex(err, "Image 'image'.*missing.*: blob-ext")
self.assertIn('Some images are invalid', err)
def testExtblobMissingOkSect(self):
@@ -3776,16 +3773,14 @@
self._DoTestFile('159_blob_ext_missing_sect.dts',
allow_missing=True)
err = stderr.getvalue()
- self.assertRegex(err, "Image 'main-section'.*missing.*: "
- "blob-ext blob-ext2")
+ self.assertRegex(err, "Image 'image'.*missing.*: blob-ext blob-ext2")
def testPackX86RomMeMissingDesc(self):
"""Test that an missing Intel descriptor entry is allowed"""
with test_util.capture_sys_output() as (stdout, stderr):
self._DoTestFile('164_x86_rom_me_missing.dts', allow_missing=True)
err = stderr.getvalue()
- self.assertRegex(err,
- "Image 'main-section'.*missing.*: intel-descriptor")
+ self.assertRegex(err, "Image 'image'.*missing.*: intel-descriptor")
def testPackX86RomMissingIfwi(self):
"""Test that an x86 ROM with Integrated Firmware Image can be created"""
@@ -3795,7 +3790,7 @@
with test_util.capture_sys_output() as (stdout, stderr):
self._DoTestFile('111_x86_rom_ifwi.dts', allow_missing=True)
err = stderr.getvalue()
- self.assertRegex(err, "Image 'main-section'.*missing.*: intel-ifwi")
+ self.assertRegex(err, "Image 'image'.*missing.*: intel-ifwi")
def testPackOverlapZero(self):
"""Test that zero-size overlapping regions are ignored"""
@@ -4009,8 +4004,7 @@
self._DoTestFile('162_fit_external.dts',
force_missing_bintools='mkimage')
err = stderr.getvalue()
- self.assertRegex(err,
- "Image 'main-section'.*missing bintools.*: mkimage")
+ self.assertRegex(err, "Image 'image'.*missing bintools.*: mkimage")
def testSectionIgnoreHashSignature(self):
"""Test that sections ignore hash, signature nodes for its data"""
@@ -4084,7 +4078,7 @@
self._DoTestFile('168_fit_missing_blob.dts',
allow_missing=True)
err = stderr.getvalue()
- self.assertRegex(err, "Image 'main-section'.*missing.*: atf-bl31")
+ self.assertRegex(err, "Image 'image'.*missing.*: atf-bl31")
def testBlobNamedByArgMissing(self):
"""Test handling of a missing entry arg"""
@@ -4490,8 +4484,7 @@
self._DoTestFile('185_compress_section.dts',
force_missing_bintools='lz4')
err = stderr.getvalue()
- self.assertRegex(err,
- "Image 'main-section'.*missing bintools.*: lz4")
+ self.assertRegex(err, "Image 'image'.*missing bintools.*: lz4")
def testCompressExtra(self):
"""Test compression of a section with no fixed size"""
@@ -5045,7 +5038,7 @@
self._DoTestFile('216_blob_ext_list_missing.dts',
allow_missing=True)
err = stderr.getvalue()
- self.assertRegex(err, "Image 'main-section'.*missing.*: blob-ext")
+ self.assertRegex(err, "Image 'image'.*missing.*: blob-ext")
def testFip(self):
"""Basic test of generation of an ARM Firmware Image Package (FIP)"""
@@ -5123,13 +5116,13 @@
shutil.rmtree(tmpdir)
lines = stdout.getvalue().splitlines()
expected = [
-'Name Image-pos Size Entry-type Offset Uncomp-size',
-'----------------------------------------------------------------',
-'main-section 0 2d3 section 0',
-' atf-fip 0 90 atf-fip 0',
-' soc-fw 88 4 blob-ext 88',
-' u-boot 8c 4 u-boot 8c',
-' fdtmap 90 243 fdtmap 90',
+'Name Image-pos Size Entry-type Offset Uncomp-size',
+'--------------------------------------------------------------',
+'image 0 2d3 section 0',
+' atf-fip 0 90 atf-fip 0',
+' soc-fw 88 4 blob-ext 88',
+' u-boot 8c 4 u-boot 8c',
+' fdtmap 90 243 fdtmap 90',
]
self.assertEqual(expected, lines)
@@ -5202,7 +5195,7 @@
with test_util.capture_sys_output() as (stdout, stderr):
self._DoTestFile('209_fip_missing.dts', allow_missing=True)
err = stderr.getvalue()
- self.assertRegex(err, "Image 'main-section'.*missing.*: rmm-fw")
+ self.assertRegex(err, "Image 'image'.*missing.*: rmm-fw")
def testFipSize(self):
"""Test a FIP with a size property"""
@@ -5267,7 +5260,7 @@
self._DoTestFile('216_blob_ext_list_missing.dts',
allow_fake_blobs=True)
err = stderr.getvalue()
- self.assertRegex(err, "Image 'main-section'.*faked.*: blob-ext-list")
+ self.assertRegex(err, "Image 'image'.*faked.*: blob-ext-list")
def testListBintools(self):
args = ['tool', '--list']
@@ -5355,8 +5348,7 @@
self._DoTestFile('220_fit_subentry_bintool.dts',
force_missing_bintools='futility', entry_args=entry_args)
err = stderr.getvalue()
- self.assertRegex(err,
- "Image 'main-section'.*missing bintools.*: futility")
+ self.assertRegex(err, "Image 'image'.*missing bintools.*: futility")
def testFitSubentryHashSubnode(self):
"""Test an image with a FIT inside"""
diff --git a/tools/binman/image.py b/tools/binman/image.py
index b84dd21..9415963 100644
--- a/tools/binman/image.py
+++ b/tools/binman/image.py
@@ -77,7 +77,7 @@
generate=True):
super().__init__(None, 'section', node, test=test)
self.copy_to_orig = copy_to_orig
- self.name = 'main-section'
+ self.name = name
self.image_name = name
self._filename = '%s.bin' % self.image_name
self.fdtmap_dtb = None