clk/qcom: handle resets and clocks in one device
Qualcomm's clock controller blocks actually do much more than it
says on the tin.. They provide clocks, resets and power domains.
Currently, U-Boot requires one to spawn 2 separate devices for
controlling clocks and resets, both spanning the same register space.
Refactor the code to make it work with just a single DT node, making
it compatible with upstream Linux bindings and dropping the dedicated
reset driver in favour of including it in the clock driver.
Heavily inspired by Renesas code for a similar hw block.
[caleb: moved drivers to clk/qcom, added reset driver and adjusted bind
logic. Imported qcom,gcc-ipq4019.h from Linux]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index 90f2a93..3bddbd2 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -13,6 +13,7 @@
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
+
#include "clock-qcom.h"
/* GPLL0 clock control registers */
@@ -116,3 +117,19 @@
{
return 0;
}
+
+static const struct udevice_id gcc_apq8016_of_match[] = {
+ {
+ .compatible = "qcom,gcc-apq8016",
+ /* TODO: add reset map */
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_apq8016) = {
+ .name = "gcc_apq8016",
+ .id = UCLASS_NOP,
+ .of_match = gcc_apq8016_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index d5388c6..64b8cdf 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -99,3 +99,19 @@
{
return 0;
}
+
+static const struct udevice_id gcc_apq8096_of_match[] = {
+ {
+ .compatible = "qcom,gcc-apq8096",
+ /* TODO: add reset map */
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_apq8096) = {
+ .name = "gcc_apq8096",
+ .id = UCLASS_NOP,
+ .of_match = gcc_apq8096_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c
index 04c9996..db869f8 100644
--- a/drivers/clk/qcom/clock-ipq4019.c
+++ b/drivers/clk/qcom/clock-ipq4019.c
@@ -12,7 +12,7 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
+#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include "clock-qcom.h"
@@ -49,3 +49,97 @@
}
}
+static const struct qcom_reset_map gcc_ipq4019_resets[] = {
+ [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
+ [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
+ [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
+ [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
+ [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
+ [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
+ [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
+ [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
+ [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
+ [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
+ [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
+ [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
+ [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
+ [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
+ [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
+ [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
+ [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
+ [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
+ [PCIE_AHB_ARES] = { 0x1d010, 10 },
+ [PCIE_PWR_ARES] = { 0x1d010, 9 },
+ [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
+ [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
+ [PCIE_PHY_ARES] = { 0x1d010, 6 },
+ [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
+ [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
+ [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
+ [PCIE_PIPE_ARES] = { 0x1d010, 2 },
+ [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
+ [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
+ [ESS_RESET] = { 0x12008, 0},
+ [GCC_BLSP1_BCR] = {0x01000, 0},
+ [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
+ [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
+ [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
+ [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
+ [GCC_BIMC_BCR] = {0x04000, 0},
+ [GCC_TLMM_BCR] = {0x05000, 0},
+ [GCC_IMEM_BCR] = {0x0E000, 0},
+ [GCC_ESS_BCR] = {0x12008, 0},
+ [GCC_PRNG_BCR] = {0x13000, 0},
+ [GCC_BOOT_ROM_BCR] = {0x13008, 0},
+ [GCC_CRYPTO_BCR] = {0x16000, 0},
+ [GCC_SDCC1_BCR] = {0x18000, 0},
+ [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
+ [GCC_AUDIO_BCR] = {0x1B008, 0},
+ [GCC_QPIC_BCR] = {0x1C000, 0},
+ [GCC_PCIE_BCR] = {0x1D000, 0},
+ [GCC_USB2_BCR] = {0x1E008, 0},
+ [GCC_USB2_PHY_BCR] = {0x1E018, 0},
+ [GCC_USB3_BCR] = {0x1E024, 0},
+ [GCC_USB3_PHY_BCR] = {0x1E034, 0},
+ [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
+ [GCC_PCNOC_BCR] = {0x2102C, 0},
+ [GCC_DCD_BCR] = {0x21038, 0},
+ [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
+ [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
+ [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
+ [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
+ [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
+ [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
+ [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
+ [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
+ [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
+ [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
+ [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
+ [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
+ [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
+ [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
+ [GCC_TCSR_BCR] = {0x22000, 0},
+ [GCC_MPM_BCR] = {0x24000, 0},
+ [GCC_SPDM_BCR] = {0x25000, 0},
+};
+
+static struct msm_clk_data ipq4019_data = {
+ .resets = gcc_ipq4019_resets,
+ .num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
+};
+
+static const struct udevice_id gcc_ipq4019_of_match[] = {
+ {
+ .compatible = "qcom,gcc-ipq4019",
+ .data = (ulong)&ipq4019_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_ipq4019) = {
+ .name = "gcc_ipq4019",
+ .id = UCLASS_NOP,
+ .of_match = gcc_ipq4019_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 5914616..a661837 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -1,8 +1,13 @@
-// SPDX-License-Identifier: BSD-3-Clause
+// SPDX-License-Identifier: BSD-3-Clause AND GPL-2.0
/*
- * Clock drivers for Qualcomm APQ8016, APQ8096
+ * Clock and reset drivers for Qualcomm platforms Global Clock
+ * Controller (GCC).
*
* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ * (C) Copyright 2020 Sartura Ltd. (reset driver)
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ * (C) Copyright 2022 Linaro Ltd. (reset driver)
+ * Author: Sumit Garg <sumit.garg@linaro.org>
*
* Based on Little Kernel driver, simplified
*/
@@ -10,9 +15,13 @@
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
+#include <reset-uclass.h>
+
#include "clock-qcom.h"
/* CBCR register fields */
@@ -137,12 +146,15 @@
static int msm_clk_probe(struct udevice *dev)
{
+ struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev);
struct msm_clk_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
+ priv->data = data;
+
return 0;
}
@@ -161,22 +173,97 @@
.enable = msm_clk_enable,
};
-static const struct udevice_id msm_clk_ids[] = {
- { .compatible = "qcom,gcc-msm8916" },
- { .compatible = "qcom,gcc-apq8016" },
- { .compatible = "qcom,gcc-msm8996" },
- { .compatible = "qcom,gcc-apq8096" },
- { .compatible = "qcom,gcc-ipq4019" },
- { .compatible = "qcom,gcc-sdm845" },
- { .compatible = "qcom,gcc-qcs404" },
- { }
-};
-
-U_BOOT_DRIVER(clk_msm) = {
- .name = "clk_msm",
+U_BOOT_DRIVER(qcom_clk) = {
+ .name = "qcom_clk",
.id = UCLASS_CLK,
- .of_match = msm_clk_ids,
.ops = &msm_clk_ops,
.priv_auto = sizeof(struct msm_clk_priv),
.probe = msm_clk_probe,
};
+
+int qcom_cc_bind(struct udevice *parent)
+{
+ struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent);
+ struct udevice *clkdev, *rstdev;
+ struct driver *drv;
+ int ret;
+
+ /* Get a handle to the common clk handler */
+ drv = lists_driver_lookup_name("qcom_clk");
+ if (!drv)
+ return -ENOENT;
+
+ /* Register the clock controller */
+ ret = device_bind_with_driver_data(parent, drv, "qcom_clk", (ulong)data,
+ dev_ofnode(parent), &clkdev);
+ if (ret)
+ return ret;
+
+ /* Bail out early if resets are not specified for this platform */
+ if (!data->resets)
+ return ret;
+
+ /* Get a handle to the common reset handler */
+ drv = lists_driver_lookup_name("qcom_reset");
+ if (!drv)
+ return -ENOENT;
+
+ /* Register the reset controller */
+ ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data,
+ dev_ofnode(parent), &rstdev);
+ if (ret)
+ device_unbind(clkdev);
+
+ return ret;
+}
+
+static int qcom_reset_set(struct reset_ctl *rst, bool assert)
+{
+ struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(rst->dev);
+ void __iomem *base = dev_get_priv(rst->dev);
+ const struct qcom_reset_map *map;
+ u32 value;
+
+ map = &data->resets[rst->id];
+
+ value = readl(base + map->reg);
+
+ if (assert)
+ value |= BIT(map->bit);
+ else
+ value &= ~BIT(map->bit);
+
+ writel(value, base + map->reg);
+
+ return 0;
+}
+
+static int qcom_reset_assert(struct reset_ctl *rst)
+{
+ return qcom_reset_set(rst, true);
+}
+
+static int qcom_reset_deassert(struct reset_ctl *rst)
+{
+ return qcom_reset_set(rst, false);
+}
+
+static const struct reset_ops qcom_reset_ops = {
+ .rst_assert = qcom_reset_assert,
+ .rst_deassert = qcom_reset_deassert,
+};
+
+static int qcom_reset_probe(struct udevice *dev)
+{
+ /* Set our priv pointer to the base address */
+ dev_set_priv(dev, (void *)dev_read_addr(dev));
+
+ return 0;
+}
+
+U_BOOT_DRIVER(qcom_reset) = {
+ .name = "qcom_reset",
+ .id = UCLASS_RESET,
+ .ops = &qcom_reset_ops,
+ .probe = qcom_reset_probe,
+};
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index c90bbef..a9f895c 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Qualcomm APQ8016, APQ8096, SDM845
- *
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
-#ifndef _CLOCK_SNAPDRAGON_H
-#define _CLOCK_SNAPDRAGON_H
+#ifndef _CLOCK_QCOM_H
+#define _CLOCK_QCOM_H
#define CFG_CLK_SRC_CXO (0 << 8)
#define CFG_CLK_SRC_GPLL0 (1 << 8)
@@ -32,10 +30,22 @@
uintptr_t D;
};
-struct msm_clk_priv {
- phys_addr_t base;
+struct qcom_reset_map {
+ unsigned int reg;
+ u8 bit;
};
+struct msm_clk_data {
+ const struct qcom_reset_map *resets;
+ unsigned long num_resets;
+};
+
+struct msm_clk_priv {
+ phys_addr_t base;
+ struct msm_clk_data *data;
+};
+
+int qcom_cc_bind(struct udevice *parent);
void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
void clk_enable_cbc(phys_addr_t cbcr);
diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c
index 80218af..10ac360 100644
--- a/drivers/clk/qcom/clock-qcs404.c
+++ b/drivers/clk/qcom/clock-qcs404.c
@@ -11,9 +11,10 @@
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,gcc-qcs404.h>
+
#include "clock-qcom.h"
-#include <dt-bindings/clock/qcom,gcc-qcs404.h>
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVE BIT(31)
@@ -235,3 +236,50 @@
return 0;
}
+
+static const struct qcom_reset_map qcs404_gcc_resets[] = {
+ [GCC_GENI_IR_BCR] = { 0x0F000 },
+ [GCC_CDSP_RESTART] = { 0x18000 },
+ [GCC_USB_HS_BCR] = { 0x41000 },
+ [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
+ [GCC_QUSB2_PHY_BCR] = { 0x4103c },
+ [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
+ [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
+ [GCC_USB3_PHY_BCR] = { 0x39004 },
+ [GCC_USB_30_BCR] = { 0x39000 },
+ [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
+ [GCC_PCIE_0_BCR] = { 0x3e000 },
+ [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
+ [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
+ [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
+ [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
+ [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
+ [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
+ [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
+ [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
+ [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
+ [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
+ [GCC_EMAC_BCR] = { 0x4e000 },
+ [GCC_WDSP_RESTART] = {0x19000},
+};
+
+static const struct msm_clk_data qcs404_gcc_data = {
+ .resets = qcs404_gcc_resets,
+ .num_resets = ARRAY_SIZE(qcs404_gcc_resets),
+};
+
+static const struct udevice_id gcc_qcs404_of_match[] = {
+ {
+ .compatible = "qcom,gcc-qcs404",
+ .data = (ulong)&qcs404_gcc_data
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_qcs404) = {
+ .name = "gcc_qcs404",
+ .id = UCLASS_NOP,
+ .of_match = gcc_qcs404_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index 95a057b..a7a43f6 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -15,6 +15,7 @@
#include <asm/io.h>
#include <linux/bitops.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+
#include "clock-qcom.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -96,3 +97,44 @@
{
return 0;
}
+
+static const struct qcom_reset_map sdm845_gcc_resets[] = {
+ [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
+ [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+ [GCC_SDCC2_BCR] = { 0x14000 },
+ [GCC_SDCC4_BCR] = { 0x16000 },
+ [GCC_UFS_CARD_BCR] = { 0x75000 },
+ [GCC_UFS_PHY_BCR] = { 0x77000 },
+ [GCC_USB30_PRIM_BCR] = { 0xf000 },
+ [GCC_USB30_SEC_BCR] = { 0x10000 },
+ [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
+ [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
+ [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
+ [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
+ [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
+ [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+
+static const struct msm_clk_data qcs404_gcc_data = {
+ .resets = sdm845_gcc_resets,
+ .num_resets = ARRAY_SIZE(sdm845_gcc_resets),
+};
+
+static const struct udevice_id gcc_sdm845_of_match[] = {
+ {
+ .compatible = "qcom,gcc-sdm845",
+ .data = (ulong)&qcs404_gcc_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_sdm845) = {
+ .name = "gcc_sdm845",
+ .id = UCLASS_NOP,
+ .of_match = gcc_sdm845_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};