* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 4a1ccb0..f7fe22e 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -38,6 +38,7 @@
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
uint pvr, svr;
+ uint fam;
uint ver;
uint major, minor;
@@ -60,6 +61,12 @@
case SVR_8560:
puts("8560");
break;
+ case SVR_8548:
+ puts("8548");
+ break;
+ case SVR_8548_E:
+ puts("8548_E");
+ break;
default:
puts("Unknown");
break;
@@ -67,13 +74,14 @@
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
pvr = get_pvr();
+ fam = PVR_FAM(pvr);
ver = PVR_VER(pvr);
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
printf("Core: ");
- switch (ver) {
- case PVR_VER(PVR_85xx):
+ switch (fam) {
+ case PVR_FAM(PVR_85xx):
puts("E500");
break;
default:
@@ -84,7 +92,7 @@
get_sys_info(&sysinfo);
- puts("Clocks Configuration:\n");
+ puts("Clock Configuration:\n");
printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
@@ -101,6 +109,13 @@
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
+#ifdef CONFIG_MPC8548
+ /*
+ * Yes, the entire PQ38 family use the same
+ * bit-representation for twice the clock divider values.
+ */
+ clkdiv *= 2;
+#endif
printf("LBC:%4lu MHz\n",
sysinfo.freqSystemBus / 1000000 / clkdiv);
} else {