Merge branch 'master' of git://git.denx.de/u-boot-sh
Minor fixes for the Alt board and PHY use on Gen2.
diff --git a/MAINTAINERS b/MAINTAINERS
index 3166ec7..f9ee428 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -439,6 +439,11 @@
M: Lukasz Majewski <lukma@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-dfu.git
+F: cmd/dfu.c
+F: cmd/usb_*.c
+F: common/dfu.c
+F: common/update.c
+F: common/usb_storage.c
F: drivers/dfu/
F: drivers/usb/gadget/
diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c
index d7997d7..f32b3c4 100644
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -61,13 +61,7 @@
void *reg = (void *)CONFIG_ROCKCHIP_BOOT_MODE_REG;
int boot_mode = readl(reg);
- /*
- * This should be handled using a driver-tree property and a suitable
- * driver which can read the appropriate settings. As it is, this
- * breaks chromebook_minnie.\
- *
- * rockchip_dnl_mode_check();
- */
+ rockchip_dnl_mode_check();
boot_mode = readl(reg);
debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c
index 6464a32..f972cc9 100644
--- a/board/technexion/pico-imx6ul/spl.c
+++ b/board/technexion/pico-imx6ul/spl.c
@@ -10,6 +10,7 @@
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
+#include <fsl_esdhc.h>
#include <linux/libfdt.h>
#include <spl.h>
@@ -141,4 +142,37 @@
void reset_cpu(ulong addr)
{
}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
#endif
diff --git a/board/technexion/pico-imx7d/README b/board/technexion/pico-imx7d/README
index 24eb97e..f21d830 100644
--- a/board/technexion/pico-imx7d/README
+++ b/board/technexion/pico-imx7d/README
@@ -26,6 +26,10 @@
Connect a USB cable between the OTG pico port and the host PC.
+Note: Some computers may be a bit strict with USB current draw and will
+shut down their ports if the draw is too high. The solution for that is
+to use an externally powered USB hub between the board and the host computer.
+
Open a terminal program such as minicom.
Copy SPL and u-boot.img to the imx_usb_loader folder.
diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
index c34c515..69c45b9 100644
--- a/configs/imx6dl_icore_nand_defconfig
+++ b/configs/imx6dl_icore_nand_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
index cf149d6..b53a501 100644
--- a/configs/imx6q_icore_nand_defconfig
+++ b/configs/imx6q_icore_nand_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 8a875a8..385efce 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -46,6 +46,7 @@
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_LED is not set
+CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index 68ad1c6..24e9971 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -16,7 +16,7 @@
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
+CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
CONFIG_IMX_WATCHDOG=y
CONFIG_DEBUG_UART=y
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 15ffe5e..7a96d17 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -28,6 +28,8 @@
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
[CLK_AHB_SPI3] = GATE(0x060, BIT(23)),
+ [CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
+
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
index 60585f3..8b6ce11 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
@@ -92,10 +92,19 @@
}
static struct rockchip_pin_bank rk3288_pin_banks[] = {
- PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
- IOMUX_SOURCE_PMU,
- IOMUX_SOURCE_PMU,
- IOMUX_UNROUTED
+ PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0",
+ IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
+ IOMUX_UNROUTED,
+ DRV_TYPE_WRITABLE_32BIT,
+ DRV_TYPE_WRITABLE_32BIT,
+ DRV_TYPE_WRITABLE_32BIT,
+ 0,
+ PULL_TYPE_WRITABLE_32BIT,
+ PULL_TYPE_WRITABLE_32BIT,
+ PULL_TYPE_WRITABLE_32BIT,
+ 0
),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
IOMUX_UNROUTED,
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index b84b079..ce93565 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -228,7 +228,13 @@
}
}
- data = (mask << (bit + 16));
+ if (mux_type & IOMUX_WRITABLE_32BIT) {
+ regmap_read(regmap, reg, &data);
+ data &= ~(mask << bit);
+ } else {
+ data = (mask << (bit + 16));
+ }
+
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
@@ -252,7 +258,8 @@
int reg, ret, i;
u32 data, rmask_bits, temp;
u8 bit;
- int drv_type = bank->drv[pin_num / 8].drv_type;
+ /* Where need to clean the special mask for rockchip_perpin_drv_list */
+ int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK);
debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
pin_num, strength);
@@ -324,10 +331,15 @@
return -EINVAL;
}
- /* enable the write to the equivalent lower bits */
- data = ((1 << rmask_bits) - 1) << (bit + 16);
- data |= (ret << bit);
+ if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) {
+ regmap_read(regmap, reg, &data);
+ data &= ~(((1 << rmask_bits) - 1) << bit);
+ } else {
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << rmask_bits) - 1) << (bit + 16);
+ }
+ data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
@@ -375,7 +387,11 @@
case RK3288:
case RK3368:
case RK3399:
- pull_type = bank->pull_type[pin_num / 8];
+ /*
+ * Where need to clean the special mask for
+ * rockchip_pull_list.
+ */
+ pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK);
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
i++) {
@@ -390,10 +406,15 @@
return ret;
}
- /* enable the write to the equivalent lower bits */
- data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
- data |= (ret << bit);
+ if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) {
+ regmap_read(regmap, reg, &data);
+ data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit);
+ } else {
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ }
+ data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
break;
default:
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
index bc80963..5a6849c 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
@@ -26,6 +26,7 @@
#define IOMUX_SOURCE_PMU BIT(2)
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
+#define IOMUX_WRITABLE_32BIT BIT(5)
/**
* Defined some common pins constants
@@ -49,6 +50,9 @@
int offset;
};
+#define DRV_TYPE_IO_MASK GENMASK(31, 16)
+#define DRV_TYPE_WRITABLE_32BIT BIT(31)
+
/**
* enum type index corresponding to rockchip_perpin_drv_list arrays index.
*/
@@ -61,6 +65,9 @@
DRV_TYPE_MAX
};
+#define PULL_TYPE_IO_MASK GENMASK(31, 16)
+#define PULL_TYPE_WRITABLE_32BIT BIT(31)
+
/**
* enum type index corresponding to rockchip_pull_list arrays index.
*/
@@ -200,6 +207,32 @@
}, \
}
+#define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \
+ iom2, iom3, drv0, drv1, drv2, \
+ drv3, pull0, pull1, pull2, \
+ pull3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .type = iom0, .offset = -1 }, \
+ { .type = iom1, .offset = -1 }, \
+ { .type = iom2, .offset = -1 }, \
+ { .type = iom3, .offset = -1 }, \
+ }, \
+ .drv = { \
+ { .drv_type = drv0, .offset = -1 }, \
+ { .drv_type = drv1, .offset = -1 }, \
+ { .drv_type = drv2, .offset = -1 }, \
+ { .drv_type = drv3, .offset = -1 }, \
+ }, \
+ .pull_type[0] = pull0, \
+ .pull_type[1] = pull1, \
+ .pull_type[2] = pull2, \
+ .pull_type[3] = pull3, \
+ }
+
#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
label, iom0, iom1, iom2, \
iom3, drv0, drv1, drv2, \
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 9dbea64..6fe1aa7 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -132,7 +132,7 @@
return -1;
}
-static void sunxi_dw_hdmi_phy_set(uint clock)
+static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
{
struct sunxi_hdmi_phy * const phy =
(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
@@ -146,7 +146,7 @@
switch (div) {
case 1:
writel(0x30dc5fc0, &phy->pll);
- writel(0x800863C0, &phy->clk);
+ writel(0x800863C0 | (phy_div - 1), &phy->clk);
mdelay(10);
writel(0x00000001, &phy->unk3);
setbits_le32(&phy->pll, BIT(25));
@@ -164,7 +164,7 @@
break;
case 2:
writel(0x39dc5040, &phy->pll);
- writel(0x80084381, &phy->clk);
+ writel(0x80084380 | (phy_div - 1), &phy->clk);
mdelay(10);
writel(0x00000001, &phy->unk3);
setbits_le32(&phy->pll, BIT(25));
@@ -178,7 +178,7 @@
break;
case 4:
writel(0x39dc5040, &phy->pll);
- writel(0x80084343, &phy->clk);
+ writel(0x80084340 | (phy_div - 1), &phy->clk);
mdelay(10);
writel(0x00000001, &phy->unk3);
setbits_le32(&phy->pll, BIT(25));
@@ -192,7 +192,7 @@
break;
case 11:
writel(0x39dc5040, &phy->pll);
- writel(0x8008430a, &phy->clk);
+ writel(0x80084300 | (phy_div - 1), &phy->clk);
mdelay(10);
writel(0x00000001, &phy->unk3);
setbits_le32(&phy->pll, BIT(25));
@@ -207,36 +207,46 @@
}
}
-static void sunxi_dw_hdmi_pll_set(uint clk_khz)
+static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
{
- int value, n, m, div = 0, diff;
- int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
-
- div = sunxi_dw_hdmi_get_divider(clk_khz * 1000);
+ int value, n, m, div, diff;
+ int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
/*
* Find the lowest divider resulting in a matching clock. If there
* is no match, pick the closest lower clock, as monitors tend to
* not sync to higher frequencies.
*/
- for (m = 1; m <= 16; m++) {
- n = (m * div * clk_khz) / 24000;
+ for (div = 1; div <= 16; div++) {
+ int target = clk_khz * div;
- if ((n >= 1) && (n <= 128)) {
- value = (24000 * n) / m / div;
- diff = clk_khz - value;
- if (diff < best_diff) {
- best_diff = diff;
- best_m = m;
- best_n = n;
+ if (target < 192000)
+ continue;
+ if (target > 912000)
+ continue;
+
+ for (m = 1; m <= 16; m++) {
+ n = (m * target) / 24000;
+
+ if (n >= 1 && n <= 128) {
+ value = (24000 * n) / m / div;
+ diff = clk_khz - value;
+ if (diff < best_diff) {
+ best_diff = diff;
+ best_m = m;
+ best_n = n;
+ best_div = div;
+ }
}
}
}
+ *phy_div = best_div;
+
clock_set_pll3_factors(best_m, best_n);
debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
- clk_khz, (clock_get_pll3() / 1000) / div,
- best_n, best_m, div);
+ clk_khz, (clock_get_pll3() / 1000) / best_div,
+ best_n, best_m, best_div);
}
static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
@@ -244,7 +254,7 @@
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ);
+ int div = clock_get_pll3() / edid->pixelclock.typ;
struct sunxi_lcdc_reg *lcdc;
if (mux == 0) {
@@ -276,8 +286,10 @@
static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
{
- sunxi_dw_hdmi_pll_set(mpixelclock/1000);
- sunxi_dw_hdmi_phy_set(mpixelclock);
+ int phy_div;
+
+ sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
+ sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
return 0;
}
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index a121064..ad45b10 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -23,7 +23,7 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* Dev kit SD card */
+
/* Ethernet Configs */
#define CONFIG_FEC_XCV_TYPE RMII
@@ -43,10 +43,10 @@
"console=" CONSOLE_DEV "\0" \
"mmcdev=1\0" \
"mmcpart=1\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
"mmcargs=setenv bootargs console=${console},${baudrate}" \
- " root=${mmcroot} ${mtdparts}\0" \
+ " root=PARTUUID=${uuid} rootwait rw\0 ${mtdparts}\0" \
"nandargs=setenv bootargs console=${console},${baudrate}" \
" ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \
"ramargs=setenv bootargs console=${console},${baudrate}" \
@@ -60,8 +60,8 @@
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdt_file}\0" \
"loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr_r}" \
" ${ramdisk_file}; setenv ramdisksize ${filesize}\0" \
- "mmcboot=echo Booting from mmc...; run mmcargs; run loadimage;" \
- " run loadfdt; bootz ${loadaddr} - ${fdt_addr_r}\0" \
+ "mmcboot=echo Booting from mmc...; run finduuid; run mmcargs;" \
+ "run loadimage; run loadfdt; bootz ${loadaddr} - ${fdt_addr_r}\0" \
"mmcramboot=run ramargs; run loadimage;" \
" run loadfdt; run loadramdisk;" \
" bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 2d4b9c9..b06c909 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -94,7 +94,7 @@
"run set_con_hdmi; " \
"else " \
"run set_con_serial; " \
- "fi;"
+ "fi"
#endif /* CONFIG_USB_KEYBOARD */
#endif /* CONFIG_CMD_USB */
@@ -142,12 +142,12 @@
"console=ttymxc0\0" \
"fan=gpio set 92\0" \
"set_con_serial=setenv stdout serial; " \
- "setenv stderr serial;\0" \
+ "setenv stderr serial\0" \
"set_con_hdmi=setenv stdout serial,vga; " \
- "setenv stderr serial,vga;\0" \
- "stderr=serial,vga;\0" \
- "stdin=serial,usbkbd;\0" \
- "stdout=serial,vga;\0"
+ "setenv stderr serial,vga\0" \
+ "stderr=serial,vga\0" \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vga\0"
#define CONFIG_BOOTCOMMAND \
"mmc rescan; " \