| commit | da84f33b046fe99c5fbb6f7d8f8b03c7333b260d | [log] [tgz] |
|---|---|---|
| author | Gabor Juhos <juhosg@openwrt.org> | Wed Jun 12 18:02:46 2013 +0200 |
| committer | Tom Rini <trini@ti.com> | Wed Jul 24 09:51:05 2013 -0400 |
| tree | cae25d170f59261651ca5ff9f2b6aeb2501f94d2 | |
| parent | b1a14c471cb4ea633746e7249e468a86a69f2495 [diff] |
MIPS: mips32/cache.S: remove superfluous register assignment The t4 register already holds the cache line size, and the value of the register is not changed in mips_init_icache. Get the cache line size value from t4 for mips_init_dcache as well and remove the superfluous assignment of t5 register. Signed-off-by: Gabor Juhos <juhosg@openwrt.org>