arc: cache - utilize IO coherency (AKA IOC) engine
With release of ARC HS38 v2.1 new IO coherency engine could be built-in
ARC core. This hardware module ensures coherency between DMA-ed data
from peripherals and L2 cache.
With L2 and IOC enabled there's no overhead for L2 cache manual
maintenance which results in significantly improved IO bandwidth.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 667f218..cf999b0 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -53,6 +53,13 @@
#define ARC_AUX_SLC_INVALIDATE 0x905
#define ARC_AUX_SLC_IVDL 0x910
#define ARC_AUX_SLC_FLDL 0x912
+#define ARC_BCR_CLUSTER 0xcf
+
+/* IO coherency related auxiliary registers */
+#define ARC_AUX_IO_COH_ENABLE 0x500
+#define ARC_AUX_IO_COH_PARTIAL 0x501
+#define ARC_AUX_IO_COH_AP0_BASE 0x508
+#define ARC_AUX_IO_COH_AP0_SIZE 0x509
#ifndef __ASSEMBLY__
/* Accessors for auxiliary registers */