ppc_4xx: Apply new HW register names
Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c
index c3665da..a58db04 100644
--- a/post/cpu/ppc4xx/ether.c
+++ b/post/cpu/ppc4xx/ether.c
@@ -115,11 +115,11 @@
sync ();
#endif
/* reset emac */
- out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
+ out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
sync ();
for (i = 0;; i++) {
- if (!(in_be32 ((void*)(EMAC_M0 + hw_addr)) & EMAC_M0_SRST))
+ if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST))
break;
if (i >= 1000) {
printf ("Timeout resetting EMAC\n");
@@ -134,15 +134,15 @@
mode_reg = 0x0;
if (sysinfo.freqOPB <= 50000000);
else if (sysinfo.freqOPB <= 66666667)
- mode_reg |= EMAC_M1_OBCI_66;
+ mode_reg |= EMAC_MR1_OBCI_66;
else if (sysinfo.freqOPB <= 83333333)
- mode_reg |= EMAC_M1_OBCI_83;
+ mode_reg |= EMAC_MR1_OBCI_83;
else if (sysinfo.freqOPB <= 100000000)
- mode_reg |= EMAC_M1_OBCI_100;
+ mode_reg |= EMAC_MR1_OBCI_100;
else
- mode_reg |= EMAC_M1_OBCI_GT100;
+ mode_reg |= EMAC_MR1_OBCI_GT100;
- out_be32 ((void*)(EMAC_M1 + hw_addr), mode_reg);
+ out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
@@ -210,40 +210,40 @@
/* set internal loopback mode */
#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
- out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | 0 |
- EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
- EMAC_M1_MF_100MBPS | EMAC_M1_IST |
- in_be32 ((void*)(EMAC_M1 + hw_addr)));
+ out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 |
+ EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
+ EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
+ in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
#else
- out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | EMAC_M1_ILE |
- EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
- EMAC_M1_MF_100MBPS | EMAC_M1_IST |
- in_be32 ((void*)(EMAC_M1 + hw_addr)));
+ out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE |
+ EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
+ EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
+ in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
#endif
/* set transmit enable & receive enable */
- out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_TXE | EMAC_M0_RXE);
+ out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE);
/* enable broadcast address */
- out_be32 ((void*)(EMAC_RXM + hw_addr), EMAC_RMR_BAE);
+ out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE);
/* set transmit request threshold register */
- out_be32 ((void*)(EMAC_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */
+ out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */
/* set receive low/high water mark register */
#if defined(CONFIG_440)
/* 440s has a 64 byte burst length */
- out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x80009000);
+ out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000);
#else
/* 405s have a 16 byte burst length */
- out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
+ out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
#endif /* defined(CONFIG_440) */
- out_be32 ((void*)(EMAC_TXM1 + hw_addr), 0xf8640000);
+ out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000);
/* Set fifo limit entry in tx mode 0 */
- out_be32 ((void*)(EMAC_TXM0 + hw_addr), 0x00000003);
+ out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003);
/* Frame gap set */
- out_be32 ((void*)(EMAC_I_FRAME_GAP_REG + hw_addr), 0x00000008);
+ out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008);
sync ();
}
@@ -270,7 +270,7 @@
udelay (1000);
}
/* emac reset */
- out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
+ out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* remove clocks for EMAC internal loopback */
@@ -300,7 +300,7 @@
flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
sync ();
- out_be32 ((void*)(EMAC_TXM0 + hw_addr), in_be32 ((void*)(EMAC_TXM0 + hw_addr)) | EMAC_TXM0_GNP0);
+ out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0);
sync ();
}