imx: imx-common: introduce Resource Domain Controller support
Introduce Resource Domain Controller support for i.MX.
Now i.MX6SX and i.MX7D supports this feature to assign masters
and peripherals to different domains.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
index 229623922..c4f48bb 100644
--- a/arch/arm/imx-common/Kconfig
+++ b/arch/arm/imx-common/Kconfig
@@ -3,3 +3,11 @@
config ROM_UNIFIED_SECTIONS
bool
+
+config IMX_RDC
+ bool "i.MX Resource domain controller driver"
+ depends on ARCH_MX6 || ARCH_MX7
+ help
+ i.MX Resource domain controller is used to assign masters
+ and peripherals to differet domains. This can be used to
+ isolate resources.
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index e7190c3..568f41c 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -27,6 +27,7 @@
obj-y += cache.o init.o
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
+obj-$(CONFIG_IMX_RDC) += rdc-sema.o
obj-$(CONFIG_SECURE_BOOT) += hab.o
endif
ifeq ($(SOC),$(filter $(SOC),vf610))
diff --git a/arch/arm/imx-common/rdc-sema.c b/arch/arm/imx-common/rdc-sema.c
new file mode 100644
index 0000000..dcb5c41
--- /dev/null
+++ b/arch/arm/imx-common/rdc-sema.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/rdc-sema.h>
+#include <asm/arch/imx-rdc.h>
+#include <asm-generic/errno.h>
+
+/*
+ * Check if the RDC Semaphore is required for this peripheral.
+ */
+static inline int imx_rdc_check_sema_required(int per_id)
+{
+ struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&imx_rdc->pdap[per_id]);
+ /*
+ * No semaphore:
+ * Intial value or this peripheral is assigned to only one domain
+ */
+ if (!(reg & RDC_PDAP_SREQ_MASK))
+ return -ENOENT;
+
+ return 0;
+}
+
+/*
+ * Check the peripheral read / write access permission on Domain [dom_id].
+ */
+int imx_rdc_check_permission(int per_id, int dom_id)
+{
+ struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&imx_rdc->pdap[per_id]);
+ if (!(reg & RDC_PDAP_DRW_MASK(dom_id)))
+ return -EACCES; /*No access*/
+
+ return 0;
+}
+
+/*
+ * Lock up the RDC semaphore for this peripheral if semaphore is required.
+ */
+int imx_rdc_sema_lock(int per_id)
+{
+ struct rdc_sema_regs *imx_rdc_sema;
+ int ret;
+ u8 reg;
+
+ ret = imx_rdc_check_sema_required(per_id);
+ if (ret)
+ return ret;
+
+ if (per_id < SEMA_GATES_NUM)
+ imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
+ else
+ imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
+
+ do {
+ writeb(RDC_SEMA_PROC_ID,
+ &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+ reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+ if ((reg & RDC_SEMA_GATE_GTFSM_MASK) == RDC_SEMA_PROC_ID)
+ break; /* Get the Semaphore*/
+ } while (1);
+
+ return 0;
+}
+
+/*
+ * Unlock the RDC semaphore for this peripheral if main CPU is the
+ * semaphore owner.
+ */
+int imx_rdc_sema_unlock(int per_id)
+{
+ struct rdc_sema_regs *imx_rdc_sema;
+ int ret;
+ u8 reg;
+
+ ret = imx_rdc_check_sema_required(per_id);
+ if (ret)
+ return ret;
+
+ if (per_id < SEMA_GATES_NUM)
+ imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
+ else
+ imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
+
+ reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+ if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID)
+ return 1; /*Not the semaphore owner */
+
+ writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+
+ return 0;
+}
+
+/*
+ * Setup RDC setting for one peripheral
+ */
+int imx_rdc_setup_peri(rdc_peri_cfg_t p)
+{
+ struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+ u32 reg = 0;
+ u32 share_count = 0;
+ u32 peri_id = p & RDC_PERI_MASK;
+ u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
+
+ /* No domain assigned */
+ if (domain == 0)
+ return -EINVAL;
+
+ reg |= domain;
+
+ share_count = (domain & 0x3)
+ + ((domain >> 2) & 0x3)
+ + ((domain >> 4) & 0x3)
+ + ((domain >> 6) & 0x3);
+
+ if (share_count > 0x3)
+ reg |= RDC_PDAP_SREQ_MASK;
+
+ writel(reg, &imx_rdc->pdap[peri_id]);
+
+ return 0;
+}
+
+/*
+ * Setup RDC settings for multiple peripherals
+ */
+int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
+ unsigned count)
+{
+ rdc_peri_cfg_t const *p = peripherals_list;
+ int i, ret;
+
+ for (i = 0; i < count; i++) {
+ ret = imx_rdc_setup_peri(*p);
+ if (ret)
+ return ret;
+ p++;
+ }
+
+ return 0;
+}
+
+/*
+ * Setup RDC setting for one master
+ */
+int imx_rdc_setup_ma(rdc_ma_cfg_t p)
+{
+ struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+ u32 master_id = (p & RDC_MASTER_MASK) >> RDC_MASTER_SHIFT;
+ u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
+
+ writel((domain & RDC_MDA_DID_MASK), &imx_rdc->mda[master_id]);
+
+ return 0;
+}
+
+/*
+ * Setup RDC settings for multiple masters
+ */
+int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count)
+{
+ rdc_ma_cfg_t const *p = masters_list;
+ int i, ret;
+
+ for (i = 0; i < count; i++) {
+ ret = imx_rdc_setup_ma(*p);
+ if (ret)
+ return ret;
+ p++;
+ }
+
+ return 0;
+}