| commit | decaba6f5cf386d569ac3997bebb871b966c6b18 | [log] [tgz] |
|---|---|---|
| author | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | Tue Mar 25 21:30:07 2008 +0900 |
| committer | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | Tue Mar 25 21:30:07 2008 +0900 |
| tree | 71f09ba3ea48d9ae4a00d7e6735f71980e7fa2f5 | |
| parent | d43d43ef2845af309c25a64bb9c2c5fb3261bc23 [diff] |
[MIPS] Cleanup CP0 Status initialization Add setup_c0_status from Linux. For the moment we disable interrupts, set CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for reset-time configuration and will work well across most processors. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>